KR20010060271A - Multi-layered wiring board and semiconductor device using such a board - Google Patents

Abstract

PURPOSE: Provided is a multilayer wiring board at low manufacturing cost, without having to use wiring board in which conductor layers are formed on both faces and which is composed of an insulating layer and without using an electroless plating treatment. CONSTITUTION: In a plurality of wiring layers(12) and insulating layers(10), a plurality of wiring boards(26) in which the wiring layers(12) are formed only on surfaces, on one side of the sheet-like insulating layers(10) are laminated in such a way that the wiring layers(12) and the insulating layers(10) on the wiring boards(26) are arranged alternately. A connection part(28) is formed, in such a way that a part of the wiring layer(12) on the wiring board(26) on one side is bent inside a communication part(16) formed to communicate with the surface and the rear of the insulating layer(10), and that bend parts(30) are formed in the insulating layer(10) in at least one wiring board(26) among the plurality of wiring boards(26). The bend parts(30) and the wiring layer(12) on the wiring board(26), on the other side are laminated so as to be adjacent to the side of the insulating layer(10) on the wiring board(26) on one side are connected electrically via first conductors(32) other than conductors which are formed through plating.

Description

Multi-layered wiring board and semiconductor device using the same {MULTI-LAYERED WIRING BOARD AND SEMICONDUCTOR DEVICE USING SUCH A BOARD}

The present invention relates to a multilayer wiring board and a semiconductor device using such wiring board.

With reference to FIGS. 22A-22D, the structure of the conventional multilayer wiring board is demonstrated with the manufacturing method. Such a multilayer wiring board can be used, for example, to form a semiconductor package constituting a semiconductor device.

First, a plate-like or sheet-like insulating substrate 10 is prepared, and each surface of the insulating substrate 10 is coated with a conductive layer such as copper foil. A resinous material such as polyimide is one example of the material for the insulating substrate 10.

Thereafter, the conductor layer on the insulating substrate 10 is etched to form a predetermined wiring pattern (wiring layer) 12 on each surface of the insulating substrate 10, thereby as shown in FIG. 22A. 14)

Then, as shown in FIG. 22B, through holes 16 are formed through the wiring layer 12 and the insulating substrate 10, and the wiring substrates on the respective surfaces of the substrate 10 at the positions ( The wiring layers 12 on the 14 are connected to each other.

Thereafter, the inner wall of the through hole 16 and the outer surface of the wiring layer 12 are plated with copper, for example, so that the wiring layers 12 on each surface of the insulating substrate 10 are electrically connected to each other. This connection 18 forms what is called a via. In this regard, when the inner wall of the through hole 16 is plated, electroless plating is first applied, and then electroplating is performed.

Such a plurality of insulating substrates 10, that is, the wiring substrates 14 having the wiring pattern 12 and the connecting portion 18, are laminated with each other through an adhesive 20.

In order to electrically connect the wiring layers 12 formed in the wiring board 14 to each other, the optional connecting parts 18 provided in the wiring board 14 are arranged in a row so that the connecting parts 18 are adjacent to each other. do. Thereafter, the alloys (first conductor) 22 such as solder are poured into the connection connecting portions 18, so that the connecting portions 18 are electrically connected to each other.

Thereby, the multilayer wiring board 23 in which the wiring layers 12 in the wiring board 14 were electrically connected to each other is obtained, respectively.

However, the conventional multilayer wiring board needs to use the wiring board which has a conductor layer on both surfaces of an insulated substrate, respectively, and there exists a problem that the cost of components increases.

In addition, it is necessary to perform electroless plating in the connecting portion forming step, and there is also a problem that the manufacturing cost increases.

In addition, since the wiring boards having the conductor layers on both sides of the insulating board must be laminated with each other, there is another problem that the multilayer wiring board obtained is thick.

It is therefore an object of the present invention to provide a multilayer wiring board which can be manufactured at a reasonable cost, and a semiconductor device using the same.

BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows the structure of one Example of the multilayer wiring board by this invention.

2A to 2E are explanatory diagrams showing the manufacturing steps of Examples of the multilayer wiring board according to the present invention.

3 to 9 are plan views showing various shapes of extensions of wiring layers extending into through-holes.

10A to 10B are explanatory diagrams of a step of bending an extension part when the length bent into the through hole exceeds the thickness of the insulating substrate.

Fig. 11 is a perspective view showing a main portion of a connecting portion constituted by bending the extending portion into a notch formed on the outer circumference of the insulating substrate.

12 is a plan view of an essential part of a semiconductor device according to the present invention as viewed from the side of a wiring layer.

FIG. 13 is a cross-sectional view taken along the line W-W in FIG. 12; FIG.

Fig. 14 is a sectional view showing the structure of still another embodiment of semiconductor device according to the present invention;

Fig. 15 is a plan view showing a main part of an embodiment of a semiconductor device according to the present invention when viewed from the side of a wiring layer.

FIG. 16 is a cross-sectional view taken along the line W-W in FIG. 15; FIG.

Fig. 17 is a plan view showing a main part of still another embodiment of the semiconductor device according to the present invention as viewed from the side of the wiring layer.

FIG. 18 is a cross-sectional view taken along the line W-W in FIG. 17; FIG.

Fig. 19 is a plan view showing an essential part of still another embodiment of the semiconductor device according to the present invention as viewed from the side of the wiring layer.

FIG. 20 is an enlarged plan view of a circular portion Y including a bump in FIG. 19. FIG.

FIG. 21 is a cross-sectional view taken along the line W-W in FIG. 19; FIG.

22A to 22D are explanatory diagrams showing a manufacturing process of a conventional multilayer wiring board.

According to the present invention, a plurality of plate or sheet shaped insulating substrates each having surfaces and a wiring layer formed on one of the surfaces of the insulating substrate, respectively, the insulating substrate and the wiring layer A plurality of wiring boards stacked so as to be alternately positioned;

Communication means provided in at least one of the insulating substrates, and a bending extension portion formed by bending a portion of the wiring layer on the one insulating substrate toward the opposite side of the one insulating substrate through the connecting means. multilayer wiring including at least one electrical connection having a bent extension and a first conductor for electrically connecting the bent extension to the wiring layer on the insulating substrate adjacent to the one insulating substrate. A substrate is provided.

The connecting means may be through holes provided in the insulating substrate. Alternatively, the connecting means may be a notch provided at the peripheral end of the insulating substrate. The first conductor may be a solder or an electro-conductive paste.

According to still another aspect of the present invention, there is provided a plurality of plate or sheet-shaped insulating substrates each having surfaces, and a wiring layer formed on one of the surfaces of the insulating substrate, wherein the insulating substrate and the wiring layer are alternately provided. A plurality of wiring boards stacked to be positioned; Connecting means provided in at least one of the insulating substrates, and one end is formed as a lead and the other end is bent toward the opposite side of the one insulating substrate through the connecting means to form a bent extension portion. A multilayer wiring board comprising a layer and at least one electrical connection having a first conductor for electrically connecting the bent extension to the wiring layer on the insulating substrate adjacent to the one insulating substrate, wherein the insulating substrate Has a semiconductor element accommodation recess—and,

There is provided a semiconductor device including a semiconductor element disposed in the semiconductor element accommodating recess and having an electrode electrically connected to the lead of the wiring layer.

The electrode of the semiconductor element is preferably bonded to the lead of the wiring layer and electrically connected. Alternatively, a bump may be formed on the electrode of the semiconductor element and be bonded to and electrically connected to the lead of the wiring layer.

According to still another aspect of the present invention, there is provided a plurality of plate or sheet-shaped insulating substrates each having surfaces, and a wiring layer formed on one of the surfaces of the insulating substrate, wherein the insulating substrate and the wiring layer are alternately provided. A plurality of wiring boards stacked to be positioned; Connecting means provided in at least one of the insulating substrates, the wiring layer having one end formed as a lead and the other end bent toward the opposite surface of the one insulating substrate through the connecting means to form a bent extension portion; A multilayer wiring board comprising at least one electrical connection portion having a first conductor for electrically connecting the bending extension portion to the wiring layer on the insulating substrate adjacent the one insulating substrate; There is provided a semiconductor device including a semiconductor element disposed on at least one of the wiring boards so that an electrode terminal forming surface faces the wiring layer, and having an electrode electrically connected to the lead of the wiring layer.

It is preferable that a bump is formed on the electrode of the semiconductor element, and the bump is attached to the lead of the wiring layer and electrically connected thereto.

According to still another aspect of the present invention, there is provided a plurality of plate or sheet-shaped insulating substrates each having surfaces, and a wiring layer formed on one of the surfaces of the insulating substrate, wherein the insulating substrate and the wiring layer are alternately provided. A plurality of wiring boards stacked to be positioned; At least one electrical connection including a via hole provided in at least one of the insulating substrates, wherein one end of the wiring layer is formed as a lead and the other end is located in the via hole. A multilayer wiring board

A semiconductor device having a bump on an electrode, disposed on at least one of the wiring boards, such that an electrode forming surface faces an opposite side of the wiring layer, wherein the bump is connected to the lead of the wiring layer through the via hole. And electrically connected. The via hole is preferably filled with solder.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, with reference to an accompanying drawing, preferable Example of the multilayer wiring board and semiconductor device by this invention is described in detail.

(Multilayer Wiring Board)

The multilayer wiring board according to the present invention is characterized by etching the conductor layer by using a plurality of wiring boards each having a conductor layer on only one surface, and forming a connection portion on the wiring board without using electroless plating. The wiring layers in the wiring boards are connected to each other.

It will be described in detail below.

First, a multilayer wiring board 24 according to an embodiment of the present invention will be described. The same or similar components as those in the prior art shown in FIGS. 22A to 22D are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 1, the multilayer wiring board 24 includes a plurality of (two in the case of FIG. 1) plate- or sheet-shaped insulating substrates 10, each of which insulates the substrate 10. The wiring board 26 is formed by forming a layer and providing the wiring layer 12 only on one surface (the upper surface of FIG. 1), where the insulating substrate 10 and the wiring layer 12 are alternately stacked.

The connection part 28 which electrically connects the wiring layers 12 to each other in at least one pair of adjacent wiring boards 26 is made of the wiring layer 12 in one wiring board (the lower one in FIG. 1). The stretched portion 30, which is a portion, is bent into a connecting portion provided in the insulating substrate 10, for example, through the through hole 16 to connect the front and rear surfaces to each other, and formed of a first conductor (plated with plating) in the through hole 16. In addition, it is formed by connecting the wiring layer 12 and the bending extension portion 30 in another wiring substrate (the lower one in FIG. 1) through a solder or an electro-conductive paste.

According to this configuration, each of the conventional wiring boards includes a conductor layer on one side of an insulating layer (for example, a tape substrate covered with copper foil on one side) and an insulation layer having a conductor layer on the opposite side. In comparison, a multilayer wiring board can be manufactured from a plurality of inexpensive wiring boards, and the connection part 28 for connecting the wiring board 12 with the insulating board 10 interposed with the insulating layer is formed without using electroless plating. By forming one multilayer wiring board, manufacturing cost can be reduced significantly.

Next, the manufacturing process of the multilayer wiring board 24 is demonstrated.

In FIG. 2A, an insulating substrate 10 having a conductor layer such as copper foil integrally covered on one surface is prepared, and the conductor layer is patterned by etching using a lithography method to form the surface of the insulating substrate 10. The wiring board 26 having the wiring layer 12 is formed on it.

A feature of the structure of the wiring layer 12 is that a part of the wiring layer 12 protrudes as the extension part 30 into the region where the through hole 16 is formed in the insulating substrate 10.

Examples of the planar shape of the extension part 30 in the wiring layer 12 protruding into the region where the through hole or the via hole 16 are formed will be described with reference to FIGS. 3 to 9. In this regard, most of the planar shape of the through hole 16 (the area where it is formed) and the land 12a formed as part of the wiring layer 12 on the outer circumference of the through hole 16 is circular, but FIG. 9. Other shapes, such as square or polygon, as shown in FIG.

In FIG. 3, the planar shape of the extension part 30 of the wiring layer 12 is a ring shape extending at an equidistant distance from the outer periphery of the region where the through hole 16 is formed toward its center.

In FIG. 4, the planar shape of the extension part 30 of the wiring layer 12 blocks the through hole 16, from the center of the region where the through hole 16 is formed in the outer circumference (the outer circumference of the through hole 16). It has a shape having a plurality of extended slits 16. In FIG. 4, four slits 34 are arranged at an equiangular shape to form a cross shape as a whole. However, the number and arrangement of slits 34 can be arbitrarily selected. The slit 34 facilitates evenly splitting of the elongation 30 along the slit 34 when the elongation 30 is bent into the through hole 16. This function of the slit 34 is the same in the embodiment described later.

In FIG. 5, the planar shape of the extension part 30 of the wiring layer 12 is a semicircle covering half of the region where the through hole 16 is formed, and the single slit 34 extending in the radial direction in the middle region thereof. It is a shape having. In such a configuration, it is not necessary to cover the entire outer circumference of the through hole. Here, the number of slits 34 is not limited to one, but may be two, three or more.

In FIG. 6, the planar shape of the extension portion 30 of the wiring layer 12 is a fan shape covering one quarter of the through hole 16. Although there is no slit 34 in FIG. 6, the slit 34 may be provided.

In FIG. 7, the extension 30 of the wiring layer 12 covers the entirety of the through hole 16 and has no slit 34.

In FIG. 8, the planar shape of the elongate portion 30 of the wiring layer 12 is a shape having four protrusions extending inwards, which are arranged at an angle (here 90 degrees) on the outer circumference of the through hole 16. . The number of protrusions may be at least one, and if there are a plurality of protrusions, they may be arranged at the same pitch or different pitches.

In the above example, the area in which the through hole 16 is formed or its planar shape was circular, but as shown in Fig. 9, it may be a polygon (for example, a quadrangle). The example shown in FIG. 9 is almost identical in structure to the example shown in FIG. 4, wherein the slits 34 are formed on the diagonal of the through hole 16 so that each of the extension portions 30 of the wiring layer 12 has a triangular shape. Becomes Although not shown, the polygonal through hole 16 may be provided with an extension portion 30 different from that shown in FIG. 4, that is, an extension portion 30 shown in any of FIGS. 3 and 5 to 8.

2B shows a state in which the through hole 16 is formed by using a laser beam generated from the side of the insulating substrate 10 opposite to the wiring layer 12. The region in which the through hole 16 is formed is located inside the planar region of the land 12a, as shown in FIGS. Alternatively, first, through holes are formed in the insulating substrate 10 by, for example, punches, etc., and then the wiring layer 12 having the elongated portion 30 is formed by covering the copper foil on the insulating substrate 10. You may also do it.

In FIG. 2C, the extension 30 of the wiring layer 12 extending into the region where the through hole 16 is formed is bent in the through hole 16. The length of the elongate portion 30 is selected such that the tip of the elongate portion 30 protrudes out from the through hole 16 but does not cross the opposite side of the insulating substrate 10. In order to reliably connect the extension part 30 to the wiring layer 12 of the lower wiring board 26 via the first conductor while suppressing an increase in the thickness of the multilayer wiring board 24, It is preferable that the tip of the bend extension 30 is flush with the opening of the other through hole 16. However, if the wiring layer 12 and the extension part 30 of the lower wiring board 26 can be electrically connected by the first conductor 32, the tip of the bend extension part 30 and the lower wiring board 26 are electrically connected. There may be a gap between the wiring layers 12.

As shown in FIG. 10A, in accordance with the relationship between the planar shape of the through hole 16 and the thickness of the insulating substrate 10, the tip of the bent extension 30 of the wiring layer 12 is formed of the insulating substrate 10. It may be the case of protruding out of the through hole 16 beyond the opposite side. In order to handle such a protruding end portion, as shown in FIG. 10B, the protruding end of the extending portion 30 is bent into the through hole 16 as shown in FIG. It is bent along the outer periphery of the through hole 16 on the opposite side of the. This method requires a step of bending the protruding end of the extension portion 30 and is manufactured by laminating a plurality of wiring boards 26 with each other, so that the overall thickness of the multilayer wiring board 24 becomes large. Since the bent tip of the extension part 30 comes into close contact with the wiring layer 12 in the lower wiring board 26, there is an advantage that a reliable connection can be obtained between the adjacent wiring layers 12.

As a second method, it is also possible to insert the tip end of the elongate portion 30 projecting out of the through hole 16 (that is, not to bend on the other side of the insulating substrate 10). According to this method, the process of bending the front-end | tip of the extension part 30 is unnecessary, and the increase of the thickness of the multilayer wiring board 24 which arises by laminating | stacking the some wiring board 26 can also be prevented. However, also in this method, the process of bending the front-end | tip of the extension part 30 on the opposite surface of the insulated substrate 10 in the lowest wiring board is needed.

FIG. 2D shows a state in which the steps shown in FIGS. 2A to 2C are repeated on a plurality of wiring boards 26 (two in the present embodiment) to be stacked later. By bonding the wiring boards 26 to each other with an adhesive 20, the through holes 16 of the wiring boards 26 are aligned and connected to each other to form the connecting portion 28. In this regard, each of the wiring boards 26 has through holes 16 having a predetermined shape, but as shown in FIG. 1, the through holes 16 may not be provided in the lowermost wiring boards 26.

In FIG. 2E, conductors 32 (hereinafter simply referred to as “first conductors”) that can be melted in a flow state by heating, such as solder, are connected to each other from the through holes 16 in the uppermost wiring substrate 26. Pour into the series of through holes 16 to form connection portions 28 that electrically connect the wiring layers 12 in the wiring board 26 to each other. As a result, a multilayer wiring board 24 is obtained, wherein the wiring layers 12 in the wiring board 26 are electrically connected to each other between the respective layers.

Instead of the solder, a conductive paste in which conductive particles are diffused may be used as the first conductor 32.

Instead of the through holes 16 provided in each of the wiring boards 26 described above, as shown in FIG. 11, the notches 36 having a semicircular planar shape are provided on the outer circumference of the wiring board 26, respectively. ) May be formed. Although not shown, by stacking a plurality of wiring boards 26 each having a notch 36 and an extension portion 30, the inner walls of the notch 36 are continuous with each other, and the first conductor 32 into the notch 36. Is poured so that the extension part 30 in the laminated wiring board 26 is electrically connected. Therefore, a multilayer wiring board 24 in which the wiring layers 12 are electrically connected to each other is obtained.

(Semiconductor device)

The structure of the semiconductor device using the multilayer wiring board 24 mentioned above with reference to FIGS. 12-21 is demonstrated. In this regard, except in the case shown in FIG. 14, the connection portions 28 each have a notch 36 on the outer periphery of the wiring board 26, and the extension portion 30 formed at the end of the wiring layer 12. ) Is formed in the notch 36, where the elongate portion 30 is longer than the thickness of the insulated substrate 10, and the tip of the elongated portion 30 is bent on the other side of the insulated substrate 10. . Although not described in detail, there is another structure in which the length of the extension part 30 is equal to or shorter than the thickness of the insulating substrate 10 so that the tip of the extension part 30 does not need to be bent. In addition, there is another structure in which the connection portion 28 is provided on the outer circumference of the wiring board 26, and the internal portion of the wiring board 26, such as a via, is provided.

The semiconductor device 38 includes a plurality of wiring boards 26 each having a wiring layer 12 on only one surface of the insulating substrate 10 and stacked so that the wiring layer 12 and the insulating substrate 10 are alternately arranged. The multilayer wiring board 24 is formed.

According to the embodiment shown in FIGS. 12-14, the accommodation recessed part 42 is each provided in the insulated substrate 10 of the wiring board 26, and accommodates the semiconductor chip 40. FIG. The accommodation recess 42 is an opening provided in the insulating substrate 10, and the wiring layer 12 is exposed on the bottom surface thereof. The conductive layer in the receiving recess 42 is removed by etching except for the region where the lead and the attachment layer 54, which will be described later, will be formed, and the window portion 44 through the wiring substrate 26 is formed. In other words, the conductor layer portions corresponding to the leads and the chip mounting region are left as they are.

One end of the wiring layer 12 (as shown in FIGS. 12 and 13, the left end) extends into the recess 42 to form a lead 48 connected to the electrode terminal 46 of the semiconductor chip 40. On the other hand, the other end (as shown in Figs. 12 and 13, the right end) is the notch 36 formed on the outer circumference of the insulating substrate 10 in close contact with the inner surface of the notch 36 due to the bent portion 30 is bent. Stretches into the area. It should be noted that the wiring layer 12 has a chip mounting portion and a lead 48.

The semiconductor chips 40 are respectively accommodated in the receiving recesses 42 in the wiring board 26, whereby the surface 40a (electrode terminal forming surface) on which the electrode terminals 46 are formed is guided to the wiring layer 12, The lead 48 of the wiring layer 12 is connected to the electrode terminal 46 exposed on the electrode terminal forming surface 40a.

In each of the wiring boards 26, the semiconductor chip 40 is mounted in the receiving recess 42, so that the side, the electrode terminal forming surface 40a of the semiconductor chip 40, and the leads 48 in the wiring layer 12 are removed. After shielding, the resinous material 50 is filled in the receiving recess 42.

The wiring boards 26 are stacked on each other, so that the corresponding notches 36 are aligned and connected to each other, and the elongated portion 30 bent along the inner side of the notch 36 is a first conductor, such as solder or conductive paste. The semiconductor device 38 is formed by being electrically connected to each other by (32).

Reference numeral 54 denotes an adhesion layer for attaching the semiconductor chip 40 to the wiring layer 12, and reference numeral 56 denotes an adhesion layer for attaching the wiring layer 12 to the insulating substrate 10.

In the semiconductor device 38, the semiconductor chip 40 is mounted in the receiving recess 42 formed in the wiring board 26, and the wiring boards 26 are stacked on each other, which is a plurality of sub-semiconductor devices (sub). semiconductor) 52 is stacked to form a new single semiconductor device 38. In addition, it can be considered that the wiring board 26 which has the accommodating recessed part 42 comprises the semiconductor package in the sub-semiconductor apparatus 52, respectively.

FIG. 14 shows another embodiment of the present invention in which the notch 36 of the connecting portion 28 of the semiconductor device 38 shown in FIG. 13 is replaced by the above-described through hole 16. The inner lead 62 of the lead frame 60 is inserted into the connection hole 58 in which the through hole 16 constituting the connecting portion 28 of the sub-semiconductor device 52 is formed, respectively, and the first conductor (solder or conductive) is inserted. Paste) 32 is poured into the connection hole 58 to bond the inner lead 62 to the first conductor 32, and then the entire stacked secondary semiconductor device 52 is shielded with the resinous material 64. Thereafter, the outer lead 66 of the lead frame 60 protruding from the resinous material 64 is formed into, for example, a seagull wing type (L-shaped lead type) to form a small outline package (SOP) type semiconductor device 68. Get In this regard, the shape of the external lead 66 is not limited to the L-shaped lead type, but may be a J-shaped lead type or an I-shaped lead type.

Since the semiconductor device 68 has such a lead, the present IC assembly device can be used. The inner lead 62 may be plated with solder in advance like the first conductor 32.

In the embodiment shown in Figs. 12 to 14, although the accommodation recess 42 for accommodating the semiconductor chip 40 is provided in the insulating substrate 10, another embodiment of the present invention is not provided with such an accommodation recess. This will be described with reference to FIGS. 15 to 21.

The semiconductor devices of these embodiments each have a wiring layer 12 on only one surface, and the multilayer wiring board 24 composed of a plurality of wiring boards 26 in which the wiring layer 12 and the insulating substrate 10 are alternately stacked. 12 and 13, the notches 36 are formed on the outer periphery of the wiring board 26, respectively, and the elongate portion 30 formed at the end of the wiring layer 12 is formed. By bending into the notch 36, the connecting portion 28 is formed, and the length of the extending portion 30 is greater than the thickness of the insulating substrate 10 so that the tip of the extending portion 30 is on the opposite side of the insulating substrate 10. Bends Although not described, the length of the extension part 30 may be selected to be within the thickness of the insulating substrate 10 as described above so that the tip of the extension part 30 does not necessarily need to be bent. Alternatively, the connecting portion 28 may be provided as a via in the inner region, not on the outer circumference of the wiring board 26.

In the embodiment shown in FIG. 13, although the wiring boards are mutually bonded by the adhesive agent 20, the adhesive agent 20 is not necessarily essential as mentioned later. The adhesive brings a firm fixation between the wiring boards but has the disadvantage of requiring an adhesion process. The wiring board may be sufficiently bonded together via the electrical connecting portion 32 without using an adhesive.

15 and 16 illustrate yet another embodiment of the semiconductor device, and only the differences from the previous embodiment will be described. According to the present embodiment, the semiconductor chips 40 are mounted on the wiring boards 26 via the adhesive 54, respectively. The semiconductor chip 40 is positioned on the wiring board 26 such that the electrode terminal forming surface directly contacts the wiring board 26. In this case, the wiring board 26 has a shape in which the wiring layer 12 faces the semiconductor chip 40. The electrode terminal 46 of the semiconductor collection 40 is connected to the lead 48 of the wiring layer 12 to make an electrical connection between the semiconductor chip 40 and the wiring board 26. In this regard, the wiring layer 12 extends from the lead 48 once into the interior of the wiring board 26 and reaches while bypassing the notches 36 provided on the outer periphery of the wiring board 26, where the stretched portion The 30 is bent and joined to the notch 36 by the first conductor 32 such as solder or solder paste to form an interlayer connection.

When the wiring boards 26 are stacked, a strip-shaped solder resist 70 is disposed between adjacent wiring boards 26 parallel to the periphery at a position near the region where the peripheral notches 36 are provided. Thereby, when an interlayer connection part is comprised by the 1st conductor 32, such as solder, molten solder is prevented from flowing into the inside of a semiconductor device.

Although the shape of the wiring board 26 in this embodiment is a shape in which the semiconductor chip 40 is mounted on the wiring layer 12, the semiconductor chip 40 may be mounted on the insulating substrate 10.

According to still another embodiment shown in FIGS. 17 and 18, bumps 72 are formed on the electrode terminals 46 of the semiconductor chip 40 and connected to the leads 48 of the wiring board 26. The semiconductor chip 40 is mounted so that its electrode terminal formation surface directly contacts the wiring layer 12 of the wiring board 26. The wiring layer 12 extends from the lead 48 directly to the notch 36 provided on the outer periphery of the wiring board 26 to provide an interlayer connection as in the preceding embodiment. As in the previous embodiment, a band-shaped solder resist 70 is disposed between the adjacent wiring boards 26 at a position near the region where the peripheral notches 36 are provided.

In another embodiment of the semiconductor device shown in FIGS. 19 to 21, except for the structure of the wiring board 26 and the surface of the wiring board 26 on which the semiconductor chip 40 is mounted, FIGS. 17 and 18. In the same manner as in the embodiment shown in FIG. 6, bumps 72 are formed on the electrode terminals 46 and leads 48 of the wiring board 26 are connected to the bumps 72.

That is, the semiconductor chip 40 is mounted on the insulating substrate 10 of the wiring board 26, and the bump 72 is electrically connected to the lead 48 on the rear surface through the opening provided through the insulating substrate 10. Will be connected. In this regard, when the semiconductor chip 40 is mounted on the wiring board 26 to electrically connect the electrode terminal 46 of the semiconductor chip 40 to the lead 48 of the wiring layer 12, insulation The solder 76 is supplied into the opening 74 of the substrate 10 to fix the bump 72. The semiconductor chip 40 and the wiring board 26 are bonded to each other by providing a thin adhesive layer 50 therebetween.

In Figs. 18 and 21, bumps 72 whose end portions are connected to electrode terminals 46 having a large diameter substantially equal to the diameters of the electrode terminals 46, and whose distal ends are connected to leads 48 having small diameters, respectively. Is formed. In the embodiment shown in FIGS. 19 to 21, the solder resist 70 is applied to the insulating substrate 10 (the side where the semiconductor chip 40 is not mounted) of the wiring board 26 so as to cover almost the entire surface thereof. Cover.

While only some preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention.

According to the multi-layered wiring board and the semiconductor device of the present invention, each of the wiring boards, which has a conductor layer on only one side of the insulating layer and which is inexpensive compared with the conventional wiring board having a conductor layer on both sides of the insulating layer, It is possible to manufacture a multilayer wiring board, and also to form a connection portion capable of obtaining interlayer connections between wiring layers by etching the conductor layer without using electroless plating. Thereby, the manufacturing cost can be greatly reduced, thus reducing the product cost and also the thickness of the product.

Claims (17)

In a multi-layered wiring board, A plurality of plate or sheet shaped insulating substrates each having surfaces, and a wiring layer formed on one of the surfaces of the insulating substrate, respectively, so that the insulating substrate and the wiring layer are alternately positioned A plurality of wiring boards stacked; (2) bending means formed by communication means provided in at least one of the insulating substrates, and a part of the wiring layer on the one insulating substrate bent toward the opposite side of the one insulating substrate through the connecting means; At least one electrical connection having a bent extension and a first conductor for electrically connecting the bent extension to the wiring layer on the insulated substrate adjacent to the one insulated substrate Multilayer wiring board comprising a. The method of claim 1, The connecting means is a multilayer wiring board, characterized in that the through hole (through hole) provided in the insulating substrate. The method of claim 1, And the connecting means is a notch provided at a peripheral edge of the insulating substrate. The method of claim 1, And said first conductor is a solder. The method of claim 1, And said first conductor is an electro-conductive paste. In a semiconductor device, ① multilayer wiring board-where the multilayer wiring board is A plurality of plate or sheet-shaped insulating substrates each having surfaces, and a plurality of wiring substrates each having a wiring layer formed on one of the surfaces of the insulating substrate, and stacked such that the insulating substrate and the wiring layer are alternately positioned. and, Ⓑ the connecting means provided in at least one of the insulating substrates, one end being formed as a lead and the other end being bent toward the opposite side of the one insulating substrate via the connecting means to form a bent extension portion; And at least one electrical connection having a wiring layer and a first conductor for electrically connecting the bent extension to the wiring layer on the insulating substrate adjacent to the one insulating substrate, The insulating substrate has a semiconductor element accommodation recess; A semiconductor element disposed in the semiconductor element accommodating recess and having an electrode electrically connected to the lead of the wiring layer A semiconductor device comprising a. The method of claim 6, The connecting device is a semiconductor device, characterized in that the through hole provided in the insulating substrate. The method of claim 6, And the connecting means is a notch provided at a peripheral end of the insulating substrate. The method of claim 6, The first conductor is a semiconductor device, characterized in that the solder. The method of claim 6, And the first conductor is a conductive paste. The method of claim 6, The semiconductor element is disposed in the semiconductor element accommodating recess so that an electrode forming surface of the semiconductor element faces the wiring layer. The method of claim 11, And the electrode of the semiconductor element is bonded to and electrically connected to the lead of the wiring layer. The method of claim 11, And a bump formed on the electrode of the semiconductor element, the bump being adhered to and electrically connected to the lead of the wiring layer. In a semiconductor device, ① multilayer wiring board-where the multilayer wiring board is A plurality of plate or sheet-shaped insulating substrates each having surfaces, and a plurality of wiring substrates each having a wiring layer formed on one of the surfaces of the insulating substrate, and stacked such that the insulating substrate and the wiring layer are alternately positioned. and, Ⓑ the connecting means provided in at least one of the insulating substrates, the one end being formed as a lead and the other end being bent toward the opposite side of the one insulating substrate via the connecting means to form a bent extension portion; At least one electrical connection having a first conductor for electrically connecting the flex extension to the wiring layer on the insulating substrate adjacent to the one insulating substrate; (2) a semiconductor element having an electrode arranged on at least one of the wiring boards so that an electrode terminal forming surface faces the wiring layer, and electrically connected to the lead of the wiring layer; A semiconductor device comprising a. The method of claim 14, And a bump formed on the electrode of the semiconductor element, the bump being adhered to and electrically connected to the lead of the wiring layer. In a semiconductor device, ① multilayer wiring board-where the multilayer wiring board is A plurality of plate or sheet-shaped insulating substrates each having surfaces, and a plurality of wiring substrates each having a wiring layer formed on one of the surfaces of the insulating substrate, and stacked such that the insulating substrate and the wiring layer are alternately positioned. and, Ⓑ have at least one electrical connection including a via hole provided in at least one of the insulating substrates, One end of the wiring layer is formed as a lead and the other end is located in the via hole; (2) a semiconductor element having bumps on an electrode, disposed on at least one of the wiring boards, so that the electrode forming surface faces the opposite side of the wiring layer Including; And the bump is electrically connected to the lead of the wiring layer through the via hole. The method of claim 16, The via hole is filled with solder, characterized in that the semiconductor device.