KR20010058618A - A method for inter-dielectric planarization of film in semiconductor device - Google Patents

A method for inter-dielectric planarization of film in semiconductor device Download PDF

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KR20010058618A
KR20010058618A KR1019990065970A KR19990065970A KR20010058618A KR 20010058618 A KR20010058618 A KR 20010058618A KR 1019990065970 A KR1019990065970 A KR 1019990065970A KR 19990065970 A KR19990065970 A KR 19990065970A KR 20010058618 A KR20010058618 A KR 20010058618A
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South Korea
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film
interlayer insulating
insulating film
semiconductor device
bpsg
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KR1019990065970A
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Korean (ko)
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김진현
서윤석
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990065970A priority Critical patent/KR20010058618A/en
Publication of KR20010058618A publication Critical patent/KR20010058618A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

Abstract

PURPOSE: A method for flattening an interlayer insulating film is provided to minimize a side effect depending on the thermal load due to lowered temperature of a thermal process and efficiently improve the process time and the equipment operation. CONSTITUTION: A method for flattening an interlayer insulating film forms a borophosphoric silicate glass(BPSG) film on a given underlying layer. The BPSG film is flowed by implementing a rapid thermal annealing process under vapor atmospHere. The process of forming the BPSG film includes forming a conductive line on a given underlying layer and depositing the BPSG film in 5000-10000Å. At this time, the doping concentration of P ions and B ions are controlled to form an undoped silicate glass film into which P ions and B ions are not doped in 1500-2500Å.

Description

반도체 소자의 층간절연막 평탄화 방법{A method for inter-dielectric planarization of film in semiconductor device}A method for inter-dielectric planarization of film in semiconductor device

본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 층간절연막 형성방법에 관한 것이다.The present invention relates to semiconductor technology, and more particularly to a method for forming an interlayer insulating film of a semiconductor device.

일반적으로, 다양한 토폴로지(topology)를 갖는 반도체 기판에 패턴 형성을 위한 포토리소그래피 공정을 수행하기 위해서는 기판 표면을 균일하게 평탄화 시켜야 마스크 공정을 안정화할 수 있다.In general, in order to perform a photolithography process for pattern formation on a semiconductor substrate having various topologies, the surface of the substrate must be uniformly planarized to stabilize the mask process.

그러나, 반도체 소자의 고집적화에 따라 전도라인을 비롯한 패턴의 선폭이 갈수록 작아지고 있으며, 패턴간의 간격 또한 패턴 선폭에 비례하여 작아지고 있다. 전도라인의 선폭이 작아짐에 따라 전도라인의 저항은 증가하게 된다. 이러한저항의 증가는 전도라인의 두께를 두껍게 확보함으로써 보상할 수 있다. 그 결과, 전도라인간의 간격은 매우 좁아지게 되고 전도라인의 높이는 높아지는 양상을 띠게 되었다. 즉, 전도라인의 단차비(aspect ratio)가 증가하게 되었다.However, with high integration of semiconductor devices, line widths of patterns including conductive lines are becoming smaller, and the spacing between patterns is also decreasing in proportion to the pattern line width. As the line width of the conducting line decreases, the resistance of the conducting line increases. This increase in resistance can be compensated by securing a thicker conductive line thickness. As a result, the gap between the conduction lines becomes very narrow and the height of the conduction lines becomes high. In other words, the aspect ratio of the conduction line is increased.

층간절연막 평탄화 공정은 흔히 BPSG(borophosphoric silicate glass)로 알려진 물질을 가장 많이 이용하는데, BPSG는 점성이 작아서 고온 열처리를 행하면 쉽게 플로우(flow)를 일으켜 패턴화 특성이 우수한 장점이 있다.The interlayer insulating film planarization process is most commonly used as a material known as borophosphoric silicate glass (BPSG). BPSG has a low viscosity and has an excellent patterning property because it easily flows when subjected to high temperature heat treatment.

통상적으로, BPSG를 플로우시키기 위한 열처리 방법으로 노(Furnace)를 이용한 N2분위기에서의 열처리를 이용하고 있다.Typically, heat treatment in an N 2 atmosphere using a furnace is used as a heat treatment method for flowing BPSG.

그러나, 이러한 열처리는 로트 배치(Lot Batch)방식으로 6 로트(웨이퍼 150장)를 한꺼번에 진행하여야 한다. 따라서, 장비의 효율적인 운용을 고려하면 최소 4 로트(Lot)가 되어야 하며 노(Furnace)안의 균일한 온도구배를 위하여 진행할 로트가 6로트가 안될 경우 추가적으로 로트를 투입하여 진행하여야 한다.However, this heat treatment should be performed at 6 batches (150 wafers) at once by lot batch method. Therefore, considering the efficient operation of the equipment, it should be at least 4 lots. If the lot to be processed is not 6 lots for uniform temperature gradient in the furnace, additional lot should be added.

또한, 공정시간의 실제 진행시간은 5 ~ 30분 정도 이지만, 노의 특성상 웨이퍼 로딩/언로딩(wafer loding/unloding)시 온도와 분위기가 실제공정조건과 유사한 상태에서 실시되어야 하므로 전체시간은 최소 5시간 정도가 소요된다.In addition, the actual running time of the process time is about 5 to 30 minutes, but due to the characteristics of the furnace, the total time should be at least 5 because the temperature and the atmosphere should be carried out under conditions similar to the actual process conditions during wafer loding / unloding. It takes time.

즉, BPSG막의 평탄화를 노 열처리로 실시하는 경우 공정시간이 길어진다는 문제점과 로트 배치 방식으로 인하여 장비의 효율이 비효율적이라는 문제점이 있다.That is, when the BPSG film is planarized by furnace heat treatment, there is a problem that the process time is long and the efficiency of the equipment is inefficient due to the lot arrangement method.

본 발명은 열처리의 온도를 낮게하여 열적 부담에 따른 부작용을 최소화하고, 공정시간과 장비운용을 효율적으로 개선할 수 있는 BPSG막을 이용한 반도체 소자의 층간절연막 평탄화 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for planarizing an interlayer insulating film of a semiconductor device using a BPSG film, which can minimize the side effects due to thermal burden by lowering the temperature of heat treatment and efficiently improving the process time and equipment operation.

도1은 본 발명의 일실시예에 따른 BPSG막의 플로우를 위한 급속열처리(Rapid Thermal Annealing, RTA)의 온도조건을 도시한 도면.1 is a view showing the temperature conditions of Rapid Thermal Annealing (RTA) for the flow of the BPSG film according to an embodiment of the present invention.

상기 목적을 달성하기 위하여 본 발명은, 반도체 소자의 층간절연막 평탄화 방법에 있어서, 소정의 하부층 상에 BPSG(Borophosphoric Silicate Glass)막을 형성하는 제1 단계; 및 수증기 분위기에서 급속열처리를 실시하여 상기 BPSG막을 플로우시키는 제2 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of planarizing an interlayer insulating film of a semiconductor device, the method comprising: forming a BPSG (Borophosphoric Silicate Glass) film on a predetermined lower layer; And a second step of flowing the BPSG film by performing rapid heat treatment in a steam atmosphere.

또한, 바람직하게 본 발명은, 반도체 소자의 층간절연막 평탄화 방법에 있어서, 소정의 하부층 상에 SOG(Spin On Glass)막을 형성하는 제1 단계; 및 수증기 분위기에서 급속열처리를 실시하여 상기 SOG막을 큐어링하는 제2 단계를 포함하여 이루어진다.Also preferably, the present invention provides a method of planarizing an interlayer insulating film of a semiconductor device, the method comprising: forming a spin on glass (SOG) film on a predetermined lower layer; And a second step of curing the SOG film by performing rapid heat treatment in a steam atmosphere.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

본 발명의 일실시예에 따른 BPSG막 형성공정은 소정의 하부층 상에 전도라인을 형성하고, 그 상부에 층간절연막으로 BPSG막을 5000 ~ 10000Å정도 증착한다. 이때, P이온과 B이온의 도핑농도를 조절하여 BPSG막의 상부층에 캡핑레이어(Capping Layer) 역할을 할 수 있는 P이온과 B이온이 도핑되지 않은 USG(Undoped Silicate Glass)막을 1500Å 내지 2500Å정도 형성시켜 후속 열처리 시 발생할 수 있는 BPSG막 내부로의 수분침투에 의한 열화현상을 방지할 수 있도록 한다. 한편, USG막이 아님 다른 별도의 막으로 캡핑 레이어를 형성할 수도 있다.In the BPSG film forming process according to an embodiment of the present invention, a conductive line is formed on a predetermined lower layer, and a BPSG film is deposited on the upper portion of the BPSG film with an interlayer insulating film on the order of 5000 to 10000 Å. At this time, by adjusting the doping concentration of P and B ions to form a P- and B-doped USG (Undoped Silicate Glass) film that can act as a capping layer (Capping Layer) on the upper layer of the BPSG film to about 1500Å to 2500Å It is possible to prevent deterioration due to moisture penetration into the BPSG film that may occur during subsequent heat treatment. On the other hand, the capping layer may be formed by a separate film other than the USG film.

다음으로, BPSG막의 평탄화를 위한 플로우 공정 수행을 급속열처리공정을 적용하여 수행하게 된다.Next, a flow process for planarizing the BPSG film is performed by applying a rapid heat treatment process.

도1은 본 발명의 일실시예에 따른 BPSG막의 플로우를 위한 급속열처리(Rapid Thermal Annealing, RTA)의 온도조건을 도시한 도면이다.1 is a view showing the temperature conditions of Rapid Thermal Annealing (RTA) for the flow of the BPSG film according to an embodiment of the present invention.

도1에 도시된 바와 같이 RTA를 두 단계로 나누어 진행하되, 제1RTA구간 및 제2RTA구간으로 구분하여 2회에 걸쳐 중복 실시하게 된다.As shown in FIG. 1, the RTA is divided into two stages, and the RTA is divided into a first RTA section and a second RTA section to be repeatedly executed twice.

먼저, 제1RTA구간은 크게 제1완화단계 및 제1열처리단계의 두 단계로 구분할 수가 있다. 여기서, 제1완화단계는 최초의 램프-업(lamp-up)구간을 거쳐 이르게 되는데, 10 ~ 90sec 동안 300 ~ 600℃ 정도의 온도를 유지하게 된다. 이는, 급격한 온도상승에 따른 소자의 열적손상을 방지하기 위한 단계라 할 수 있다.First, the first RTA section can be largely divided into two stages: the first relaxation step and the first heat treatment step. Here, the first relaxation step is led through the first ramp-up period, to maintain a temperature of about 300 ~ 600 ℃ for 10 ~ 90sec. This may be referred to as a step for preventing thermal damage of the device due to a sudden temperature rise.

다음으로, 다시 램프-업(lamp-up)구간을 거쳐 BPSG막을 플로우 시킬 수 있는 온도를 제공하는 제1열처리단계를 거치게 된다. 여기서, 10 ~ 90 sec 동안 600 ~ 1000℃ 정도의 온도조건에서 BPSG막을 플로우시켜 평탄화를 시키게 된다.Next, a first heat treatment step is provided to provide a temperature at which the BPSG film can be flowed again through a ramp-up period. Here, the BPSG film is flowed and planarized at a temperature of about 600 to 1000 ° C. for 10 to 90 sec.

계속하여, 램프-다운(lamp-down)구간을 거쳐 제1RTA구간을 마침과 동시에, 바로 제2RTA 구간을 위한 제2완화단계를 거치게 된다. 여기서도, 제1완화단계와 마찬가지로 급격한 온도상승에 따른 열적손상을 방지하기 위하여 10 ~ 90 sec 동안300 ~ 600℃ 정도의 온도를 유지하게 된다.Subsequently, at the same time as completing the first RTA section through a ramp-down section, a second relaxation step for the second RTA section is immediately performed. Here, as in the first relaxation step to maintain a temperature of about 300 ~ 600 ℃ for 10 ~ 90 sec to prevent thermal damage due to rapid temperature rise.

다음으로, 제1RTA구간에서와 마찬가지로 다시 램프-업(lamp-up)구간을 거쳐 BPSG막을 플로우 시킬 수 있는 온도를 제공하는 제2열처리단계를 거치게 된다. 여기서, 10 ~ 90 sec 동안 600 ~ 1000℃ 정도의 온도조건에서 BPSG막을 플로우시켜 평탄화를 시키게 된다.Next, as in the first RTA section, a second heat treatment step is performed to provide a temperature for flowing the BPSG film through the ramp-up section again. Here, the BPSG film is flowed and planarized at a temperature of about 600 to 1000 ° C. for 10 to 90 sec.

또한, 제1RTA구간 및 제2RTA구간에서의 열처리 시 수증기(steam, H2O)분위기에서 열처리를 수행하도록 하여 종래기술에 비해 BPSG막의 평탄화 온도를 100 ~ 150℃정도 낮출수 있도록 한다. 그리고, RTA시 승온속도(Raping rate)는 초당 50 ~ 150℃ 정도로 한다.In addition, the heat treatment in the atmosphere (steam, H 2 O) at the time of the heat treatment in the 1RTA section and the 2RTA section to lower the planarization temperature of the BPSG film by 100 ~ 150 ℃ compared to the prior art. And, the Rapping rate during RTA is about 50 ~ 150 ℃ per second.

한편, 반도체 소자 제조 공정 시 금속배선 형성에 텅스텐을 사용하거나 대머신(Damascene) 공정에서 구리와 같은 녹는점이 높은 금속을 사용할 시의 SOG(Spin On Glass)막 큐어링(Curing) 대신에 본 발명의 일실시예인 2단계로 나눈 급속열처리공정을 2회 실시하는 방법이 적용될 수 있다.In the meantime, instead of the SOG (Spin On Glass) film curing in the case of using tungsten to form metal wiring in the semiconductor device manufacturing process or using a metal having a high melting point such as copper in the damascene process, In one embodiment, a method of performing the rapid heat treatment process divided into two stages twice may be applied.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아니다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 층간절연막의 평탄화 공정 시 발생할 수 있는 열적부담에 따른 부작용을 최소화할 수 있는 효과 및 공정 시간과 장비운용을 효율적으로 개선할 수 있는 효과가 있다.The present invention has the effect of minimizing the side effects due to the thermal burden that can occur during the planarization of the interlayer insulating film and the effect of efficiently improving the process time and equipment operation.

Claims (5)

반도체 소자의 층간절연막 평탄화 방법에 있어서,In the method of planarizing the interlayer insulating film of a semiconductor device, 소정의 하부층 상에 BPSG(Borophosphoric Silicate Glass)막을 형성하는 제1 단계; 및A first step of forming a BPSG (Borophosphoric Silicate Glass) film on a predetermined lower layer; And 수증기 분위기에서 급속열처리를 실시하여 상기 BPSG막을 플로우시키는 제2 단계A second step of flowing the BPSG film by performing rapid heat treatment in a steam atmosphere 를 포함하여 이루어지는 반도체 소자의 층간절연막 평탄화 방법.An interlayer insulating film planarization method of a semiconductor device comprising a. 반도체 소자의 층간절연막 평탄화 방법에 있어서,In the method of planarizing the interlayer insulating film of a semiconductor device, 소정의 하부층 상에 SOG(Spin On Glass)막을 형성하는 제1 단계; 및Forming a spin on glass (SOG) film on a predetermined lower layer; And 수증기 분위기에서 급속열처리를 실시하여 상기 SOG막을 큐어링하는 제2 단계A second step of curing the SOG film by performing rapid heat treatment in a steam atmosphere 를 포함하여 이루어지는 반도체 소자의 층간절연막 평탄화 방법.An interlayer insulating film planarization method of a semiconductor device comprising a. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 급속열처리를 2회 실시하는 것Performing the rapid heat treatment twice 을 특징으로 하는 반도체 소자의 층간절연막 평탄화 방법.An interlayer insulating film planarization method of a semiconductor device, characterized in that. 제3항에 있어서,The method of claim 3, 상기 급속열처리는,The rapid heat treatment, 10 ~ 90초 동안 300 ~ 600℃의 온도를 유지하는 단계; 및Maintaining a temperature of 300 to 600 ° C. for 10 to 90 seconds; And 10 ~ 90초 동안 600 ~ 1000℃의 온도를 유지하는 단계Maintaining a temperature of 600 to 1000 ° C. for 10 to 90 seconds 로 이루어지는 것을 특징으로 하는 반도체 소자의 층간절연막 평탄화 방법.The interlayer insulating film planarization method of the semiconductor element characterized by the above-mentioned. 제3항에 있어서,The method of claim 3, 상기 급속열처리의 승온속도는 초당 50 ~ 150℃도로 하는 것을 특징으로 하는 반도체 소자의 층간절연막 평탄화 방법.The temperature increase rate of the rapid heat treatment is 50 ~ 150 ℃ per second interlayer insulating film planarization method of a semiconductor device.
KR1019990065970A 1999-12-30 1999-12-30 A method for inter-dielectric planarization of film in semiconductor device KR20010058618A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113226887A (en) * 2019-04-29 2021-08-06 惠普发展公司，有限责任合伙企业 Corrosion-resistant microcomputer electric fluid injection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113226887A (en) * 2019-04-29 2021-08-06 惠普发展公司，有限责任合伙企业 Corrosion-resistant microcomputer electric fluid injection device

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