KR20010057688A - Method for forming titanium salicide of semiconductor device - Google Patents
Method for forming titanium salicide of semiconductor device Download PDFInfo
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- KR20010057688A KR20010057688A KR1019990061061A KR19990061061A KR20010057688A KR 20010057688 A KR20010057688 A KR 20010057688A KR 1019990061061 A KR1019990061061 A KR 1019990061061A KR 19990061061 A KR19990061061 A KR 19990061061A KR 20010057688 A KR20010057688 A KR 20010057688A
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- silicon wafer
- titanium
- thin film
- salicide
- semiconductor device
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 239000010936 titanium Substances 0.000 title claims abstract description 43
- 229910052719 titanium Inorganic materials 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 21
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000004904 shortening Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 20
- 229910021341 titanium silicide Inorganic materials 0.000 description 11
- 239000010408 film Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010406 interfacial reaction Methods 0.000 description 2
- 101000857634 Homo sapiens Receptor-transporting protein 1 Proteins 0.000 description 1
- 101000635752 Homo sapiens Receptor-transporting protein 2 Proteins 0.000 description 1
- 102100025426 Receptor-transporting protein 1 Human genes 0.000 description 1
- 102100030850 Receptor-transporting protein 2 Human genes 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자 콘택부의 저항을 감소시키기 위한 티타늄 샐리사이드(self-aligned silicide, salicide)를 형성하는 방법에 관한 것이다.The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method of forming a titanium salicide (salicide) for reducing the resistance of the semiconductor device contact portion.
일반적으로 모스 구조의 전계 효과 트랜지스터에서는 트랜지스터 구동 회로의 콘택(contact) 저항을 낮추기 위하여 실리사이드 기술을 이용하고 한다. 즉, 반도체 소자에서 실리콘과 금속의 접촉 저항을 낮추기 위하여 사용되는 실리사이드는 녹는점이 매우 높고 저항이 낮아서, 주로 높은 온도에서 공정을 진행해야 하는 초집적 회로나 반도체 장치 등에 이용되고 있다.In general, silicide technology is used to reduce the contact resistance of a transistor driving circuit in a MOS field effect transistor. That is, the silicide used to lower the contact resistance of silicon and metal in a semiconductor device has a very high melting point and low resistance, and is mainly used in a super integrated circuit or a semiconductor device that needs to be processed at a high temperature.
특히 서브 미크론(sub-micron) 사이즈의 모스형 전계 효과 트랜지스터에 있어서, 폴리 라인 및 콘택 접합에서의 저항을 낮추기 위하여 티타늄 또는 코발트 등의 샐리사이드 형성 공정이 주류로 되고 있다. 게다가 장래의 반도체 소자 축소화에 대응하여 폴리 저항에 영향을 주는 저저항 티타늄 또는 코발트 등의 샐리사이드 형성이 더욱 중요하게 인식되고 있다.In particular, in the sub-micron sized MOS type field effect transistor, a salicide formation process such as titanium or cobalt has become a mainstream in order to lower the resistance at the poly line and the contact junction. In addition, the formation of salicides such as low-resistance titanium or cobalt, which affects polyresistance in response to shrinking semiconductor devices in the future, is more importantly recognized.
그러면, 첨부된 도 1a와 도 1e를 참조하여 종래 반도체 소자의 티타늄 샐리사이드를 형성하는 공정을 개략적으로 설명한다.Next, a process of forming a titanium salicide of a conventional semiconductor device will be described with reference to FIGS. 1A and 1E.
먼저 도 1a에 도시한 바와 같이, LOCOS(local oxidation of silicon) 방법이나 STI(shallow trench isolation) 방법에 의해 소자 분리 영역(2)이 정의된 실리콘웨이퍼(1)를 열산화하여 게이트 산화막(3)을 형성하고, 그 상부에 폴리 실리콘(4)을 증착한다. 그리고, 폴리 실리콘(4)과 게이트 산화막(3)을 패터닝하여 게이트 전극(3, 4)을 형성한다. 이후, 게이트 전극(3, 4)을 마스크로 실리콘웨이퍼(1)에 P형 또는 N형 도펀트를 이온 주입하고 어닐링하여 게이트 전극(3, 4)의 양측 하부 실리콘웨이퍼에 소스/드레인(5)을 형성한다. 그리고, 실리콘웨이퍼(1) 전면에 절연막을 증착하고 등방성 식각하여 게이트 전극(3, 4)의 측벽에 측벽 스페이서(6)를 형성한다.First, as shown in FIG. 1A, the silicon oxide 1 in which the device isolation region 2 is defined is thermally oxidized by a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method. And polysilicon 4 is deposited thereon. The polysilicon 4 and the gate oxide film 3 are patterned to form the gate electrodes 3 and 4. Then, the P / N type dopant is ion-implanted and annealed to the silicon wafer 1 using the gate electrodes 3 and 4 as a mask, and the source / drain 5 is applied to both lower silicon wafers of the gate electrodes 3 and 4. Form. An insulating film is deposited on the entire surface of the silicon wafer 1 and isotropically etched to form sidewall spacers 6 on sidewalls of the gate electrodes 3 and 4.
그 다음 도 1b에 도시한 바와 같이, 실리콘웨이퍼(1) 전면에 실리사이드 형성을 위한 티타늄 박막(7)을 증착한다.Then, as shown in FIG. 1B, a titanium thin film 7 for silicide formation is deposited on the entire surface of the silicon wafer 1.
그 다음 도 1c에 도시한 바와 같이, 실리콘웨이퍼(1)를 빠른 열처리(rapid thermal processing, RTP) 장비에 장입하여 750℃ 이하의 온도로 빠른열처리(RTP1)한다. 그러면, 티타늄 박막(7)과 게이트 전극(3, 4) 상부의 폴리 실리콘 및 소스/드레인(5) 상부의 실리콘 계면 반응에 의해 티타늄 실리사이드(8)가 형성된다. 이때, 형성되는 티타늄 실리사이드(8)는 C49상으로 면저항이 높다.Then, as shown in FIG. 1C, the silicon wafer 1 is charged into rapid thermal processing (RTP) equipment and subjected to rapid thermal treatment (RTP1) at a temperature of 750 ° C. or lower. Then, the titanium silicide 8 is formed by the interfacial reaction of the silicon thin film on the titanium thin film 7 and the gate electrodes 3 and 4 and the silicon on the source / drain 5. At this time, the titanium silicide 8 formed has a high sheet resistance on the C49 phase.
그 다음 도 1d에 도시한 바와 같이, 습식 스트립(strip) 방법에 의해 티타늄 실리사이드(8)로 형성되지 않고 잔류하는 티타늄 박막(7)을 제거한다.Then, as shown in FIG. 1D, the titanium thin film 7 remaining without being formed into the titanium silicide 8 by the wet strip method is removed.
그 다음 도 1e에 도시한 바와 같이, 실리콘웨이퍼(1)를 재차 빠른 열처리 장비에 장입하여 750℃ 이상의 빠른 열처리(RTP2)한다. 그러면 C49상의 면저항이 높은 티타늄 실리사이드가 상전이를 하여 면저항이 낮은 C54상의 티타늄 실리사이드(9)가 된다.Then, as shown in FIG. 1E, the silicon wafer 1 is loaded into the rapid heat treatment equipment again and subjected to rapid heat treatment (RTP2) of 750 ° C. or higher. Then, the titanium silicide having a high sheet resistance of C49 phase undergoes phase transition to form the titanium silicide 9 of C54 phase having a low sheet resistance.
이러한 종래의 방법에서는 티타늄 박막의 증착 이후 티타늄 실리사이드를 형성하기 위하여 빠른 열처리를 750℃ 이하와 750℃ 이상의 두번에 걸쳐 진행하여야 하므로 열처리 공정 시간이 길어질 뿐만 아니라 두번의 빠른 열처리를 위한 빠른 열처리 장비 및 열처리 공정이 증가되는 문제점이 있다.In this conventional method, since the rapid heat treatment must be performed two times or less than 750 ° C. and 750 ° C. or more to form titanium silicide after the deposition of the titanium thin film, the heat treatment time is not only long, but also rapid heat treatment equipment and heat treatment for two quick heat treatments. There is a problem that the process is increased.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 티타늄 실리사이드 형성을 위한 열처리 시간을 단축하며, 열처리 공정을 단축할 수 있도록 하는 반도체 소자의 티타늄 샐리사이드 형성 방법을 제공하는 데 있다.The present invention is to solve such a problem, an object of the present invention is to provide a method for forming titanium salicide of a semiconductor device to shorten the heat treatment time for forming the titanium silicide, and to shorten the heat treatment process.
도 1a 내지 도 1e는 종래 반도체 소자의 티타늄 샐리사이드를 형성하는 방법을 개략적으로 도시한 공정도이고,1A to 1E are process diagrams schematically illustrating a method of forming titanium salicide of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따라 반도체 소자의 티타늄 샐리사이드를 형성하는 방법을 개략적으로 도시한 공정도이다.2A to 2D are schematic views illustrating a method of forming titanium salicide of a semiconductor device according to an embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 실리사이드 형성을 위한 티타늄 박막 증착 이후 750℃ 내지 800℃ 온도로 빠른 열처리하여 1번의 열처리만으로 면저항이 낮은 티타늄 샐리사이드를 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by forming a titanium salicide with low sheet resistance by only one heat treatment by rapid heat treatment at a temperature of 750 ℃ to 800 ℃ after the deposition of the titanium thin film for silicide formation.
따라서, 본 발명은 실리콘웨이퍼에 게이트 전극, 소스/드레인, 측벽 스페이서를 포함하는 모스 패턴을 형성하고, 실리콘웨이퍼 상부에 티타늄 박막을 증착한다. 그리고, 실리콘웨이퍼를 750℃ 내지 800℃의 온도로 빠른 열처리하여 티타늄 샐리사이드를 형성한 후, 습식 스트립에 의해 티타늄 샐리사이드 형성에 이용되지 않고 잔류하는 티타늄 박막을 제거하는 것을 특징으로 한다.Accordingly, the present invention forms a MOS pattern including a gate electrode, a source / drain, and sidewall spacers on the silicon wafer, and deposits a titanium thin film on the silicon wafer. After the silicon wafer is rapidly heat treated at a temperature of 750 ° C. to 800 ° C. to form titanium salicide, the wet thin film is used to remove the remaining titanium thin film without being used to form titanium salicide.
상기에서 티타늄 박막을 증착하는 이전에 실리콘웨이퍼를 불산 세정하여 실리콘웨이퍼 상부의 자연 산화막을 제거하는 것이 바람직하다.It is preferable to remove the native oxide film on the silicon wafer by hydrofluoric acid cleaning the silicon wafer prior to depositing the titanium thin film.
또한, 티타늄 박막을 증착은 스퍼터링 방식에 의해 수행하는 것이 바람직하다.In addition, the deposition of the titanium thin film is preferably carried out by a sputtering method.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따라 반도체 소자의 티타늄 샐리사이드를 형성하는 방법을 개략적으로 도시한 공정도이다.2A to 2D are schematic views illustrating a method of forming titanium salicide of a semiconductor device according to an embodiment of the present invention.
먼저 도 2a에 도시한 바와 같이, LOCOS 공정이나 STI 공정 등에 의해 소자 분리 영역(12)이 정의된 실리콘웨이퍼(11)를 열산화하여 게이트 산화막(13)을 형성하고, 게이트 산화막(13) 상부에 폴리 실리콘(14)을 증착한다. 그리고, 폴리 실리콘(14)과 게이트 산화막(13)을 패터닝하여 게이트 전극(13, 14)을 형성한다. 이후, 게이트 전극(13, 14)을 마스크로 드러난 실리콘웨이퍼(11)에 P형 또는 N형 도펀트를 이온 주입하고 어닐링하여 게이트 전극(13, 14)의 양측 하부 실리콘웨이퍼에 소스/드레인(15)을 형성한다. 그리고, 실리콘웨이퍼(11) 전면에 질화막 등의 절연막을 증착하고 등방성 식각하여 게이트 전극(13, 14)의 측벽에 측벽 스페이서(16)를 형성함으로써 실리콘웨이퍼(11)에 모스 패턴(13, 14, 15, 16)을 형성한다.First, as illustrated in FIG. 2A, the silicon wafer 11 in which the device isolation region 12 is defined is thermally oxidized by a LOCOS process, an STI process, or the like to form a gate oxide film 13, and is formed on the gate oxide film 13. Polysilicon 14 is deposited. The polysilicon 14 and the gate oxide film 13 are patterned to form the gate electrodes 13 and 14. Subsequently, a P-type or N-type dopant is ion-implanted and annealed to the silicon wafer 11 exposed as the mask of the gate electrodes 13 and 14 to source / drain 15 to lower silicon wafers on both sides of the gate electrodes 13 and 14. To form. In addition, an insulating film such as a nitride film is deposited on the entire surface of the silicon wafer 11 and isotropically etched to form sidewall spacers 16 on the sidewalls of the gate electrodes 13 and 14, thereby forming the MOS patterns 13, 14, and the like. 15, 16).
그 다음 도 2b에 도시한 바와 같이, 실리콘웨이퍼(11)를 스퍼터 시스템에 장입하여 스퍼터링 방식에 의해 실리콘웨이퍼(11) 상부 전면에 실리사이드 형성을 위한 티타늄 박막(17)을 증착한다. 이때, 티타늄 박막(17)의 증착 이전에 불산(HF) 세정에 의해 실리콘웨이퍼(11) 표면에 존재하는 자연 산화막을 불산으로 세정하여 제거하는 것이 바람직하다.Next, as shown in FIG. 2B, a silicon wafer 11 is charged into the sputter system to deposit a titanium thin film 17 for silicide formation on the entire upper surface of the silicon wafer 11 by sputtering. At this time, it is preferable to clean and remove the native oxide film present on the surface of the silicon wafer 11 by hydrofluoric acid (HF) cleaning before the deposition of the titanium thin film 17 with hydrofluoric acid.
그 다음 도 2c에 도시한 바와 같이, 실리콘웨이퍼(11)를 빠른 열처리 장비에 장입하여 750℃ 내지 800℃의 온도로 빠른 열처리한다. 그러면, 티타늄 박막(17)과 게이트 전극(13, 14) 상부 폴리 실리콘 및 소스/드레인(15) 상부 실리콘의 계면 반응에 의해 티타늄 실리사이드(18)가 형성된다. 그리고, 형성되는 티타늄 실리사이드(18)는 종래와는 달리 면저항이 낮은 C54상이 된다. 따라서, 종래에서의 2차 빠른 열처리 공정을 생략할 수 있다. 이때, 빠른 열처리 온도를 750℃ 보다 낮은 온도로 할 경우에는 종래와 같이 C49상의 티타늄 실리사이드가 형성되어 면저항이 증가되며, 800℃ 보다 높은 온도로 할 경우에는 후속 공정에서의 잔류 티타늄 박막(17)의 제거가 어렵게 된다.Then, as shown in Figure 2c, the silicon wafer 11 is charged into a rapid heat treatment equipment to be quickly heat treated at a temperature of 750 ℃ to 800 ℃. Then, titanium silicide 18 is formed by the interfacial reaction between the titanium thin film 17 and the upper silicon of the gate electrodes 13 and 14 and the upper silicon of the source / drain 15. The titanium silicide 18 to be formed is a C54 phase having a low sheet resistance unlike the conventional art. Therefore, the conventional second rapid heat treatment step can be omitted. At this time, when the fast heat treatment temperature is lower than 750 ° C, titanium silicide of C49 phase is formed as in the prior art, and the sheet resistance is increased. When the temperature is higher than 800 ° C, the residual titanium thin film 17 in the subsequent process is It is difficult to remove.
그 다음 도 2d에 도시한 바와 같이, 습식 스트립 방법에 의해 티타늄 실리사이드(18)로 형성되지 않고 실리콘웨이퍼(11) 상부에 잔류하는 티타늄 박막(17)을 제거함으로써 반도체 소자의 샐리사이드를 완성한다.Then, as shown in FIG. 2D, the salicide of the semiconductor device is completed by removing the titanium thin film 17 remaining on the silicon wafer 11 and not formed of the titanium silicide 18 by the wet strip method.
이와 같이 본 발명은 티타늄 박막 증착 이후 1번의 빠른 열처리 공정에 의해 면저항이 낮은 티타늄 샐리사이드를 형성할 수 있으므로 종래에 비해 열처리 공정 시간을 단축할 수 있어 생산성을 향상시킬 수 있으며, 빠른 열처리 공정의 단축으로 인하여 빠른 열처리 장비를 줄일 수 있을 뿐만 아니라 반도체 소자의 열에 의한 손상을 감소시킬 수 있다.As described above, the present invention can form titanium salicide having low sheet resistance by one fast heat treatment process after the deposition of a titanium thin film, so that the heat treatment process time can be shortened as compared with the conventional one, and thus the productivity can be improved, and the quick heat treatment process can be shortened. Due to this, not only the rapid heat treatment equipment can be reduced but also heat damage of the semiconductor device can be reduced.
Claims (4)
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| KR1019990061061A KR20010057688A (en) | 1999-12-23 | 1999-12-23 | Method for forming titanium salicide of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142424A (en) * | 1993-11-16 | 1995-06-02 | Toshiba Corp | Fabrication of semiconductor device |
| JPH09232254A (en) * | 1996-02-23 | 1997-09-05 | Sumitomo Metal Ind Ltd | Electrode material and its manufacture |
| KR19980084129A (en) * | 1997-05-21 | 1998-12-05 | 윤종용 | Ti silicide manufacturing method |
| JPH11330003A (en) * | 1998-05-06 | 1999-11-30 | Ind Technol Res Inst | Metal silicide forming method by laser radiation |
-
1999
- 1999-12-23 KR KR1019990061061A patent/KR20010057688A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142424A (en) * | 1993-11-16 | 1995-06-02 | Toshiba Corp | Fabrication of semiconductor device |
| JPH09232254A (en) * | 1996-02-23 | 1997-09-05 | Sumitomo Metal Ind Ltd | Electrode material and its manufacture |
| KR19980084129A (en) * | 1997-05-21 | 1998-12-05 | 윤종용 | Ti silicide manufacturing method |
| JPH11330003A (en) * | 1998-05-06 | 1999-11-30 | Ind Technol Res Inst | Metal silicide forming method by laser radiation |
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