KR100315451B1 - Method for forming gate electrode and salicide contact of semiconductor devices - Google Patents
Method for forming gate electrode and salicide contact of semiconductor devices Download PDFInfo
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- KR100315451B1 KR100315451B1 KR1019990013040A KR19990013040A KR100315451B1 KR 100315451 B1 KR100315451 B1 KR 100315451B1 KR 1019990013040 A KR1019990013040 A KR 1019990013040A KR 19990013040 A KR19990013040 A KR 19990013040A KR 100315451 B1 KR100315451 B1 KR 100315451B1
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- gate electrode
- silicon wafer
- amorphous silicon
- cobalt
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 36
- 239000010941 cobalt Substances 0.000 claims abstract description 36
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 14
- 239000002019 doping agent Substances 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 230000004913 activation Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 125000006850 spacer group Chemical group 0.000 claims abstract description 4
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000007669 thermal treatment Methods 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 2
- 238000010406 interfacial reaction Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 29
- 230000000873 masking effect Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
반도체 소자의 게이트 전극 열화를 방지함과 동시에 코발트 실리사이드를 균일하게 형성하기 위하여, 소자 분리 영역이 정의된 실리콘웨이퍼에 게이트 산화막과 비정질 실리콘으로 게이트 전극을 형성한 후, 실리콘웨이퍼를 열산화하여 게이트 전극 외벽 및 실리콘웨이퍼 표면에 희생산화막을 형성한다. 그리고, 게이트 측벽 스페이서를 형성하고, 실리콘웨이퍼를 습식 세정하여 게이트 전극 상부 및 드러난 실리콘웨이퍼 상부의 희생산화막을 제거한다. 이후, UHV 화학 기상 증착으로 게이트 전극 상부 및 드러난 실리콘웨이퍼 상부에 P형 또는 N형 도펀트가 도핑된 비정질 실리콘을 증착한 후, 스퍼터링에 의해 실리콘웨이퍼 전면에 코발트층을 형성하고, 급속 열처리하여 콘택 샐리사이드를 위한 코발트 실리사이드를 형성함과 동시에 비정질 실리콘에 도핑된 도펀트의 확산 및 활성화에 의해 게이트 전극 및 소스/드레인을 형성한다. 따라서, 게이트 전극을 그레인 바운드리가 없는 비정질 실리콘으로 형성함으로써 게이트 전극에 가해지는 전계가 균일하게 되어 게이트 열화를 방지할 수 있으며, 비정질 실리콘과 코발트의 계면 반응에 의해 코발트 실리사이드를 형성하므로 균일한 실리사이드를 형성할 수 있다.In order to prevent deterioration of the gate electrode of the semiconductor device and to form cobalt silicide uniformly, a gate electrode is formed of a gate oxide film and amorphous silicon on a silicon wafer having a device isolation region, and then the silicon wafer is thermally oxidized to form a gate electrode. A sacrificial oxide film is formed on the outer wall and the silicon wafer surface. The gate sidewall spacer is formed, and the silicon wafer is wet-cleaned to remove the sacrificial oxide film on the gate electrode and the exposed silicon wafer. Subsequently, after depositing amorphous silicon doped with P-type or N-type dopant on the gate electrode and the exposed silicon wafer by UHV chemical vapor deposition, a cobalt layer is formed on the entire surface of the silicon wafer by sputtering, followed by rapid heat treatment. The gate electrode and source / drain are formed by diffusion and activation of dopants doped in amorphous silicon while forming cobalt silicide for the side. Therefore, by forming the gate electrode made of amorphous silicon without grain boundaries, the electric field applied to the gate electrode becomes uniform to prevent gate deterioration, and cobalt silicide is formed by the interfacial reaction between amorphous silicon and cobalt to form uniform silicide. Can be formed.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 게이트 전극 및 콘택(contact)에 있어서의 쇼트키(shottky) 저항을 저감하기 위한 샐리사이드 콘택을 형성하는 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for forming a salicide contact for reducing a shottky resistance in a gate electrode and a contact of a semiconductor device. .
일반적으로 상보형 모스 구조의 전계 효과 트랜지스터에서 게이트 전극으로서 폴리 실리콘이 이용되고 있는 데, 폴리 실리콘 전극에서의 그레인 바운드리(grain boundary)는 게이트 구동시에 폴리 그레인과 그레인 바운드리의 고유 저항차에 의해 전계가 불균일하게 작용하게 되므로 게이트 열화의 원인이 된다.In general, polysilicon is used as a gate electrode in a field effect transistor having a complementary MOS structure. The grain boundary of the polysilicon electrode is caused by an intrinsic resistance difference between polygrain and grain boundary when the gate is driven. Is non-uniformly acting, causing gate degradation.
한편, 전계 효과 트랜지스터 구동 회로의 콘택부의 저항을 낮추기 위하여 티타늄 실리사이드(TiSi2) 형성 기술이 이용되고 있다.Meanwhile, in order to lower the resistance of the contact portion of the field effect transistor driving circuit, a titanium silicide (TiSi 2 ) forming technique is used.
그러나, 반도체 소자의 미세화에 따른 폴리 배선 폭과 콘택부의 면적 감소 등에 반하여 티타늄 실리사이드의 형성은 무척 어렵게 되므로 반도체 소자의 미세화에 한계가 있다. 따라서 최근에는 티타늄(Ti) 대신에 코발트(Co)로써 실리사이드를 형성하는 기술이 개발되고 있으나 코발트 실리사이드(CoSi2) 형성에도 여러가지 결점이 존재한다.However, the formation of titanium silicide is very difficult in contrast to the poly wiring width and the decrease in the area of the contact portion due to the miniaturization of the semiconductor device, thereby limiting the miniaturization of the semiconductor device. Therefore, in recent years, a technique for forming silicide with cobalt (Co) instead of titanium (Ti) has been developed, but there are various defects in forming cobalt silicide (CoSi 2 ).
특히, 코발트층과 실리콘웨이퍼의 계면의 평탄화 정도에 민감하게 반응한다. 즉, 코발트 실리사이드 형성시 하부 실리콘웨이퍼의 실리콘 그레인 사이즈에 응집 현상(agglomeration) 등이 발생하여 코발트 실리사이드가 균일하게 생성되지 않으므로 콘택부의 저항 편차폭이 커지는 문제점이 발생한다.In particular, it reacts sensitively to the leveling of the interface between the cobalt layer and the silicon wafer. That is, when cobalt silicide is formed, an agglomeration phenomenon occurs in the silicon grain size of the lower silicon wafer, and cobalt silicide is not uniformly generated.
그리고, 최근에는 반도체 소자의 축소화에 따라서 얕은 접합(shallow junction)의 필요성이 요구되고 있으며, 이에 따라 고농도의 서브(sub)-KeV 영역의 이온 주입이 가능하여야 하나, 현재로서는 이온 주입 장비의 한계가 존재한다. 더욱이 이온 주입 후, 이온 주입된 도펀트의 활성화를 위한 어닐(anneal) 동안의 TED(transient enhanced diffusion) 발생이 문제점으로 대두되고 있다.Recently, the need for shallow junctions is required in accordance with the shrinkage of semiconductor devices. Accordingly, high concentration of sub-KeV regions should be implanted, but the limitation of ion implantation equipment is currently limited. exist. Furthermore, after ion implantation, the generation of transient enhanced diffusion (TED) during annealing for activation of the ion implanted dopant has become a problem.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 반도체 소자의 게이트 전극 열화를 방지함과 동시에 콘택부의 쇼트키 저항을 저감하기 위한 코발트 실리사이드를 균일하게 형성하기 위한 샐리사이드 콘택 형성 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and an object thereof is to provide a method of forming a salicide contact for uniformly forming cobalt silicide for preventing a gate electrode deterioration of a semiconductor device and at the same time reducing a Schottky resistance of a contact portion. There is.
도 1a 내지 도 1e는 본 발명에 따라 상보형 모스 트랜지스터의 게이트 전극 및 샐리사이드를 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.1A to 1E are cross-sectional views of silicon wafers schematically illustrating a process of forming gate electrodes and salicides of complementary MOS transistors according to the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 소자 분리 영역이 정의된 실리콘웨이퍼에 게이트 산화막과 비정질 실리콘으로 게이트 전극을 형성한 후, 실리콘웨이퍼를 열산화하여 게이트 전극 외벽 및 실리콘웨이퍼 표면에 희생산화막을 형성한다. 그리고, 게이트 전극 측벽에 측벽 스페이서를 형성한 후, 실리콘웨이퍼를 습식 세정하여 게이트 전극 상부 및 드러난 실리콘웨이퍼 상부의 희생산화막을 제거한다.In order to achieve the above object, the present invention forms a gate electrode with a gate oxide film and amorphous silicon on a silicon wafer in which the device isolation region is defined, and then thermally oxidizes the silicon wafer to form a sacrificial oxide film on the outer wall of the gate electrode and the silicon wafer surface. To form. After the sidewall spacers are formed on the sidewalls of the gate electrode, the silicon wafer is wet-cleaned to remove the sacrificial oxide film on the gate electrode and the exposed silicon wafer.
이후, UHV(ultra high vacuum) 화학 기상 증착으로 게이트 전극 상부 및 드러난 실리콘웨이퍼 상부에 P형 또는 N형 도펀트가 도핑된 비정질 실리콘을 증착한다. 이때, UHV 화학 기상 증착은 1mmTorr 내지 100mmTorr 압력, 600℃ 내지 650℃ 온도 조건에서 실시하는 것이 바람직하다. 그리고, UHV 화학 기상 증착 중, 인 시투 공정으로 비정질 실리콘에 P형 또는 N형 도펀트를 도핑하는 것이 바람직하다.Thereafter, ultra high vacuum (UHV) chemical vapor deposition deposits amorphous silicon doped with P-type or N-type dopants on the gate electrode and the exposed silicon wafer. At this time, the UHV chemical vapor deposition is preferably carried out at 1mmTorr to 100mmTorr pressure, 600 ℃ to 650 ℃ temperature conditions. In addition, during UHV chemical vapor deposition, it is preferable to dope the P-type or N-type dopant to the amorphous silicon in an in-situ process.
이후, 실리콘웨이퍼 전면에 코발트를 스퍼터링하여 코발트층을 형성하고, 실리콘웨이퍼를 급속 열처리하여 콘택 샐리사이드를 위한 코발트 실리사이드를 형성함과 동시에 비정질 실리콘에 도핑된 도펀트의 확산 및 활성화에 의해 게이트 전극 및 소스/드레인을 형성한다.Afterwards, a cobalt layer is formed by sputtering cobalt on the entire surface of the silicon wafer, and the silicon wafer is rapidly heat-treated to form cobalt silicide for contact salicide, and at the same time, diffusion and activation of a dopant doped with amorphous silicon causes a gate electrode and a source. Form a drain.
이때, 급속 열처리에 의한 콘택 샐리사이드 및 게이트 전극, 소스/드레인 형성을 위하여 바람직하게는, 먼저, 실리콘웨이퍼를 600℃ 이하의 온도로 1차 급속 열처리하여 코발트 실리사이드(CoSi)를 형성하고, 코발트 실리사이드(CoSi) 형성에 이용되지 않고 잔류하는 코발트층을 제거한다. 그리고, 실리콘웨이퍼를 750℃ 이상의 온도로 2차 급속 열처리하여 코발트 실리사이드(CoSi)를 상 변이하여 안정한 코발트 실리사이드(CoSi2)를 형성함과 동시에 비벙질 실리콘에 도핑된 도펀트를 확산 및 활성화시킴으로써 게이트 전극 및 소스/드레인을 형성한다.In this case, in order to form contact salicide, gate electrode, and source / drain by rapid heat treatment, first, first, the silicon wafer is first rapidly heat-treated to a temperature of 600 ° C. or less to form cobalt silicide (CoSi), and then cobalt silicide The remaining cobalt layer is removed without being used for (CoSi) formation. The silicon wafer is subjected to a second rapid heat treatment at a temperature of 750 ° C. or higher to phase-shift cobalt silicide (CoSi) to form stable cobalt silicide (CoSi 2 ), and simultaneously diffuse and activate the dopant doped with the agitated silicon. And source / drain.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명에 따라 상보형 모스 트랜지스터의 게이트 전극 및 샐리사이드를 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.1A to 1E are cross-sectional views of silicon wafers schematically illustrating a process of forming gate electrodes and salicides of complementary MOS transistors according to the present invention.
먼저 도 1a에 도시한 바와 같이, 필드 산화막이나 트렌치에 의해 소자 분리 영역(2)을 정의하였으며, 각 소자 영역에 선택적 이온 주입을 통해 P모스 영역과 N모스 영역을 각각 정의한 실리콘웨이퍼(1)를 열산화하여 각 모스 영역 실리콘웨이퍼 상부에 게이트 산화막(3)을 각각 형성한다. 그리고, 실리콘웨이퍼(1) 전면에 비정질 실리콘층을 증착한 후, 게이트 패턴이 형성된 마스크로 비정질 실리콘층 및 게이트 산화막을 패터닝(patterning)하여 P모스 영역과 N모스 영역에 각각 비정질 실리콘의 P모스 게이트 패턴(4)과 N모스 게이트 패턴(5)을 형성한다. 이후, 실리콘웨이퍼(1)를 열산화하여 각 게이트 패턴 외벽 및 실리콘웨이퍼 표면에 희생 산화막(6)을 형성하고, 각 게이트 패턴(4)(5)의 측벽에 측벽 스페이서(7)를 형성한다.First, as shown in FIG. 1A, the device isolation region 2 is defined by a field oxide film or a trench, and the silicon wafer 1 defining the P-MOS region and the N-MOS region is selectively formed through selective ion implantation into each device region. By thermal oxidation, a gate oxide film 3 is formed on each MOS region silicon wafer, respectively. After depositing an amorphous silicon layer on the entire surface of the silicon wafer 1, the amorphous silicon layer and the gate oxide layer are patterned with a mask on which a gate pattern is formed to form PMOS gates of amorphous silicon in the PMOS region and the NMOS region, respectively. The pattern 4 and the N-MOS gate pattern 5 are formed. Thereafter, the silicon wafer 1 is thermally oxidized to form a sacrificial oxide film 6 on each gate pattern outer wall and the surface of the silicon wafer, and sidewall spacers 7 are formed on sidewalls of the gate patterns 4 and 5.
그 다음 도 1b에 도시한 바와 같이, P모스 영역만 드러나도록 N모스 영역을 마스킹하는 마스크 패턴(8)을 형성하고, 실리콘웨이퍼(1)를 습식 세정(wetcleaning)하여 드러난 희생 산화막을 제거함으로써 P모스 게이트 패턴(4) 상부의 비정질 실리콘 및 P모스 영역의 소스/드레인이 형성될 실리콘웨이퍼의 표면이 드러나도록 한다. 그리고, UHV(ultra high vacuum) 화학 기상 증착(CVD ; chemical vapor deposition)으로 P모스 게이트 패턴(4) 상부 및 P모스 영역의 드러난 실리콘웨이퍼 상부에 비정질 실리콘(9)를 증착한다. 이때, UHV 화학 기상 증착은 1mmTorr 내지 100mmTorr 정도의 압력, 600℃ 내지 650℃ 정도의 온도에서 실시한다. 그리고, UHV 화학 기상 증착에 의한 비정질 실리콘(9)의 증착시, 인 시투(IN-SITU) 공정으로 보론과 같은 P형 도펀트(dopant)를 비정질 실리콘에 도핑(doping)한다.Then, as shown in FIG. 1B, a mask pattern 8 for masking the N-MOS region is formed so that only the P-MOS region is exposed, and the silicon wafer 1 is wet-cleaned to remove the exposed sacrificial oxide film by wet cleaning. The surface of the silicon wafer on which the source / drain of the amorphous silicon and P-MOS region on the MOS gate pattern 4 is to be formed is exposed. In addition, amorphous silicon 9 is deposited on the P-MOS gate pattern 4 and on the exposed silicon wafer in the P-MOS region by ultra high vacuum (CVD) chemical vapor deposition (UHV). At this time, UHV chemical vapor deposition is carried out at a pressure of about 1mmTorr to 100mmTorr, a temperature of about 600 ℃ to 650 ℃. When the amorphous silicon 9 is deposited by UHV chemical vapor deposition, a P-type dopant such as boron is doped into the amorphous silicon by an IN-SITU process.
그 다음 도 1c에 도시한 바와 같이, N모스 영역을 마스킹하는 마스크 패턴을 제거하고, 재차 N모스 영역만 드러나도록 P모스 영역을 마스킹하는 마스크 패턴(10)을 형성하고, 실리콘웨이퍼(1)를 습식 세정하여 드러난 희생 산화막을 제거함으로써 N모스 게이트 패턴(5) 상부의 비정질 실리콘 및 N모스 영역의 소스/드레인이 형성될 실리콘웨이퍼의 표면이 드러나도록 한다. 그리고, UHV 화학 기상 증착으로 N모스 게이트 패턴(5) 상부 및 N모스 영역의 드러난 실리콘웨이퍼 상부에 비정질 실리콘(11)을 증착한다. 이때, UHV 화학 기상 증착은 1mmTorr 내지 100mmTorr 정도의 압력, 600℃ 내지 650℃ 정도의 온도에서 실시한다. 그리고, UHV 화학 기상 증착에 의한 비정질 실리콘(11)의 증착시, 인 시투 공정으로 인과 같은 N형 도펀트를 비정질 실리콘(11)에 도핑한다.Next, as shown in FIG. 1C, the mask pattern for masking the N-MOS region is removed, and the mask pattern 10 for masking the P-MOS region is formed again so that only the N-MOS region is exposed, and the silicon wafer 1 is formed. By removing the sacrificial oxide film exposed by wet cleaning, the surface of the silicon wafer on which the amorphous silicon and the source / drain of the NMOS region on the NMOS gate pattern 5 are to be formed is exposed. In addition, the amorphous silicon 11 is deposited on the N-MOS gate pattern 5 and the exposed silicon wafer in the N-MOS region by UHV chemical vapor deposition. At this time, UHV chemical vapor deposition is carried out at a pressure of about 1mmTorr to 100mmTorr, a temperature of about 600 ℃ to 650 ℃. In the deposition of the amorphous silicon 11 by UHV chemical vapor deposition, an N-type dopant such as phosphorus is doped into the amorphous silicon 11 in an in-situ process.
그 다음 도 1d에 도시한 바와 같이, P모스 영역을 마스킹하는 마스크 패턴을 제거하고, 실리콘웨이퍼(1) 전면에 코발트(Co)를 스퍼터링(sputtering)하여 코발트층(12)을 형성한다.Next, as shown in FIG. 1D, the mask pattern masking the P-MOS region is removed, and the cobalt layer 12 is formed by sputtering cobalt (Co) on the entire surface of the silicon wafer 1.
그 다음 도 1e에 도시한 바와 같이, 실리콘웨이퍼(1)를 600℃ 이하의 온도에서 급속 열처리(RTA ; rapid thermal anneal)한다. 이때, 코발트층의 코발트는 코발트층 하부의 비정질 실리콘과 반응하여 코발트 실리사이드(CoSi)를 형성하게 된다. 이후, 코발트 실리사이드(CoSi) 형성에 이용되지 않고 잔류하는 코발트층을 제거하고, 코발트 실리사이드(CoSi)를 저저항화하기 위하여 재차 750℃ 이상의 온도에서 실리콘웨이퍼(1)를 급속 열처리한다. 그러면, 코발트 실리사이드(CoSi)는 상 변이되어 안정한 코발트 실리사이드(CoSi2)(13)를 형성하게 되며, 비정질 실리콘에 도핑된 각 도펀트는 각 게이트 패턴(4)(5) 및 실리콘웨이퍼(1)로 확산됨과 동시에 활성화되어 각 모스 영역의 소스/드레인(14)(15)을 형성함과 동시에 저저항화된 P모스 및 N모스 게이트 전극(4)(5)을 형성하게 된다.Then, as shown in FIG. 1E, the silicon wafer 1 is subjected to rapid thermal annealing (RTA) at a temperature of 600 ° C. or lower. At this time, cobalt of the cobalt layer reacts with amorphous silicon under the cobalt layer to form cobalt silicide (CoSi). Thereafter, the remaining cobalt layer, which is not used to form cobalt silicide (CoSi), is removed, and the silicon wafer 1 is rapidly heat-treated again at a temperature of 750 ° C. or higher in order to reduce the resistance of the cobalt silicide (CoSi). Cobalt silicide (CoSi) is then phase-transformed to form stable cobalt silicide (CoSi 2 ) 13, with each dopant doped in amorphous silicon to each gate pattern (4) (5) and silicon wafer (1). The diffusion and activation are performed to form the source / drain 14 and 15 of each MOS region and to form the PMOS and NMOS gate electrodes 4 and 5 having low resistance.
이와 같이 본 발명은 반도체 소자의 게이트 전극을 그레인 바운드리가 없는 비정질 실리콘으로 형성함으로써 게이트 전극에 가해지는 전계가 균일하게 되어 게이트 열화를 방지할 수 있으며, 비정질 실리콘과 코발트의 계면 반응에 의해 코발트 실리사이드를 형성하므로 균일한 실리사이드를 형성할 수 있어 콘택에 있어서의 쇼트키 저항을 낮출 수 있을 뿐만 아니라 TED 현상을 방지하여 얕은 접합의 형성이 가능하게 된다.As described above, according to the present invention, the gate electrode of the semiconductor device is formed of amorphous silicon having no grain boundaries, so that an electric field applied to the gate electrode is uniform, thereby preventing gate deterioration. As a result, a uniform silicide can be formed, which not only lowers the Schottky resistance in the contact but also prevents the TED phenomenon, thereby making it possible to form a shallow junction.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07231091A (en) * | 1994-02-17 | 1995-08-29 | Nec Corp | Manufacture of semiconductor device |
| KR970067719A (en) * | 1996-03-15 | 1997-10-13 | 세끼자와 다다시 | Manufacturing Method of Semiconductor Device |
| JPH10242079A (en) * | 1997-02-24 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR19980053694A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | How to make MOSFET |
| KR19980058438A (en) * | 1996-12-30 | 1998-10-07 | 김영환 | Silicide Formation Method of Semiconductor Device |
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| JPH07231091A (en) * | 1994-02-17 | 1995-08-29 | Nec Corp | Manufacture of semiconductor device |
| KR970067719A (en) * | 1996-03-15 | 1997-10-13 | 세끼자와 다다시 | Manufacturing Method of Semiconductor Device |
| KR19980053694A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | How to make MOSFET |
| KR19980058438A (en) * | 1996-12-30 | 1998-10-07 | 김영환 | Silicide Formation Method of Semiconductor Device |
| JPH10242079A (en) * | 1997-02-24 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
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| US9735016B2 (en) | 2014-11-17 | 2017-08-15 | Samsung Electronics Co., Ltd. | Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof |
| US10361208B2 (en) | 2014-11-17 | 2019-07-23 | Samsung Electronics Co., Ltd. | Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof |
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