JPH09232254A - Electrode material and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently form a TiSi2 layer even in a fine electrode and to suppress the resistivity from being increased by a method wherein a material which is composed of Ti/Si/Ge and whose composition ratio is specific is used as an electrode material. SOLUTION: Source-drain diffusion layers 2, 2 are formed in a plurality of prescribed places on an Si substrate 1, and a gate oxide film 3 is formed between the source-drain diffusion layers 2, 2 on the Si substrate 1. A polycrystalline Si layer 4 is formed on the gate oxide film 3. A Ti1-y Gey layer 5 is formed on the polycrystalline Si layer 4 and in a prescribed place on the source-drain diffusion layers 2, 2 on the Si substrate 1. The film thickness of the Ti1-y Gey layer 5 is set in such a way that the value of (x) in Ti(Si1-x Gex )2 thin wires 6 becomes a range of 0.01<=x<=0.25. In addition, an evaporation source 13, in a film formation operation, whose composition is identical to that of the Ti1-y Gey layers 5 is used. Then, when an annealing treatment is executed to it, the Ti(Si1-x Gex )2 thin wires 6 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode material and a manufacturing method thereof, and more particularly to an electrode material for forming electrodes (including wiring) in a silicon semiconductor integrated circuit (LSI) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Silicon semiconductor integrated circuits (LSI: Larg
Logic LSI that is one of the e Scale Integrated circuits)
In order to achieve higher speed and lower power consumption, element miniaturization is underway. Changes in the geometrical shape and electrical characteristics of the device due to miniaturization follow the "scaling rule" (Reference 1; IEEE Trans. On Electron Devices ED-31, [4] (198)
4) G. Baccarani et al. P. 452, Reference 2; IEEE J. Solid-St.
ate Circuits, SC-9, [5] Oct. (1974) RHDennard et al.
p.256). That is, a MOSFET (Metal Oxide Semiconductor Fie), which is the most typical element that constitutes an LSI.
ld Effect Transistor) as an example, if the substrate doping concentration is multiplied by κ when the device three-dimensional dimension is 1 / κ, the gate delay time (τ) becomes 1 / κ and the power consumption (VI) becomes It is expected to be improved to 1 / κ ² . However, in reality, since the contact resistance (Rc) is κ ² times and the wiring resistance (R) is κ times in the wiring portion, there is a problem that the RC delay increases and the operation speed of the element becomes slow ( Reference 3; SP Murarka, "Silicides f
or VLSI Applications ", (1983) Academic Press p.9-14,
Reference 4: SMSze, Nannichi, Kawabe, Hasegawa Translated "Semiconductor Device" (1987) Sangyo Tosho, p.394). Such an increase in RC delay is caused by Al or polycrystalline Si used as an electrode material.
The main causes are the resistance (R) of itself and the increase of the contact resistance (Rc) between them and the source / drain diffusion layers.

In order to solve the RC delay problem, a so-called "silicidation technique", in which a metal silicide is used for the gate electrode and the source / drain electrodes, has been actively studied (References 3 and 4). The electrode material conditions are (1) low resistivity (R), (2) low contact resistance (Rc) with the source / drain diffusion layer,
(3) The electrical characteristics are not deteriorated during the heat treatment for activating the dopant or flattening the interlayer insulating film, which is performed after the electrode formation. A refractory metal (IV-
A, VA, VI-A group) silicide and VIII-A group metal silicide. Among them, titanium silicide (TiSi ₂ ) has many excellent features such as low resistance and high heat resistance temperature, and is said to be most suitable as an electrode material (Reference 5; Materials Science and Enginee).
ring, R11 (1993) K. Maex p.53).

12A and 12B show a salicide process for forming TiSi ₂ on a Si substrate and polycrystalline Si: (S
FIG. 1 is a schematic cross-sectional view showing (elf-Aligned Slicidation), in which 1 indicates a Si substrate. A source / drain diffusion layer 2 is formed at a predetermined portion of the Si substrate 1,
A gate oxide film 3 and a sidewall oxide film 3 ′ are formed between the source / drain diffusion layers 2 and 2 on the Si substrate 1. Further, polycrystalline S is formed above the gate oxide film 3.
The i layer 4 is formed with an element isolation oxide film 3 ″ having a predetermined thickness on both ends of the element. These source / drain diffusion layers 2
A Ti layer 7 and a Ti-Si layer 7'on the top and the polycrystalline Si layer 4
Is formed (a), and an unreacted film on SiO ₂ is removed in a self-aligned manner by annealing treatment to form a TiSi ₂ layer 9 (b). The TiSi ₂ layer 9 formed on the source / drain diffusion layer 2 constitutes a source / drain electrode, and the TiSi ₂ layer 9 formed on the gate oxide film 3.
Constitutes a gate electrode.

To form the Ti layer 7 and the Ti-Si layer 7 ',
Usually, a sputtering method, an electron beam evaporation method or the like is used. The sputtering method is a method in which a target such as Ti or Si is sputtered with Ar ions to form a film on a substrate placed at a position facing the target. The electron beam evaporation method is a method in which an evaporation source such as Ti or Si is heated by an electron beam to evaporate these and form a film.

FIG. 13 is a schematic cross-sectional view showing an apparatus used for the above-mentioned sputtering method, and 11 in the drawing shows a vacuum chamber. A vacuum exhaust system 11a is connected to the vacuum chamber 11, and the vacuum exhaust system 11a is driven to maintain the inside of the vacuum chamber 11 at a desired degree of vacuum. The Si substrate 1 is fixed to a predetermined position in the vacuum chamber 11 via a holding means (not shown), and a heater 12 for heating the Si substrate 1 to a predetermined temperature is arranged above the Si substrate 1. . Further, an evaporation source 13 as a target is arranged at a position facing the Si substrate 1 in the lower part of the vacuum chamber 11.

The Ti layer 7 and the Ti--S are formed by the apparatus having the above-mentioned structure.
In order to form the i layer 7 ', first, the cleaned Si substrate 1 is carried in and fixed to a predetermined location of the vacuum chamber 11, and then the vacuum exhaust system 11a is driven to bring the vacuum chamber 11 to a desired vacuum degree. Set. Next, the evaporation source 13 is sputtered with Ar ions, the Si substrate 1 is heated to a predetermined temperature by the heater 12, and the sputtered evaporation substance is applied to the lower surface of the Si substrate 1.

FIGS. 14 (a) to 14 (f) show stepwise how the Ti layer 7 formed on the Si substrate 1 or the polycrystalline Si layer 4 changes into the TiSi ₂ layer 10 having the C54 structure by the annealing treatment. It is the typical expanded sectional view shown.

The Si substrate 1 has been subjected to an RCA cleaning treatment. The RCA cleaning is performed by a first cleaning treatment using a mixed solution of hydrogen peroxide water and a high-pH alkaline liquid, and a hydrogen peroxide water treatment. The second cleaning process using a mixed solution with a low pH acid solution is performed separately. A Ti layer 7 is formed on the Si substrate 1 or the polycrystalline Si layer 4 by a sputtering method or the like (a). When the Si substrate 1 or the polycrystalline Si layer 4 on which the Ti layer 7 is formed is annealed, first, Si is diffused into the Ti layer 7 and Ti is deposited on the Si substrate 1 or the polycrystalline Si layer 4.
-Si layer 7'is formed (b). Next, a TiSi ₂ microcrystal 9a having a C49 structure is formed by the agglutination reaction due to the annealing treatment (c), and using this as a nucleus, a T49 having a C49 structure
The iSi ₂ layer 9 is formed (d). Next, T of C49 structure
TiSi ₂ microcrystals 10a having a C54 structure in the iSi ₂ layer 9
(E) is formed, and with this as a nucleus, TiS having a C54 structure is formed.
The i ₂ layer 10 is formed (f).

As described above, the formation of the TiSi ₂ layer 10 having the C54 structure by the annealing treatment is performed by (1) the Ti layer 7 of Si.
Diffusion into the inside, (2) formation of a TiSi ₂ layer 9 having a C49 structure, and (3) formation of a TiSi ₂ layer 10 having a C54 structure (Reference 6; Appl. Phys. Lett. 51 [ 14] ( 198
7) JCHensel et al. P. 1100). Here, T of C54 structure
The resistivity (up to 15 μΩ · cm) of the iSi ₂ layer (hereinafter, simply referred to as C54 layer) 10 is the resistivity (up to 100 μΩ · cm) of the TiSi ₂ layer having a C49 structure (hereinafter, simply referred to as C49 layer) 9.
Since it is smaller than the cm) by an order of magnitude, it is necessary to efficiently advance the phase transition from the C49 phase to the C54 phase in silicidation.

[0011]

However, in the above-mentioned conventional method of forming a TiSi layer, when the electrodes are miniaturized with the miniaturization of the element, the C49 phase to the C54 phase are reduced.
There is a problem that the phase transition to the phase is suppressed, and as a result, the resistivity increases. There are many unclear points about the mechanism of suppressing the phase transition, but at this stage, the compressive stress generated during silicidation and the grain size of the C49 layer are considered to be the main factors affecting the phase transition suppression. (Reference 7; Nikkei Microdevices, 1994.6, p.52, Reference 8; Proceedings of the 41st Joint Lecture on Applied Physics 30a-ZH-3 (1
994) Ouchi et al., P. 730).

The present invention has been made in view of the above problems, and an electrode material capable of efficiently forming a C54 layer even in a miniaturized electrode and suppressing an increase in resistivity, and the same. It is intended to provide a manufacturing method.

[0013]

Means for Solving the Problem and Its Effect As one of the methods for promoting the phase transition from the C49 phase to the C54 phase, a method of adding a substance other than Ti and Si to TiSi ₂ is considered. The conditions of the added substance are TiSi
_It is required to form the C54 structure at a lower annealing temperature than the case of ₂ , the formed C54 layer has a low resistance, and the like.

Materials other than TiSi ₂ that form a C54 structure include TiGe ₂ and ZrSn ₂ (Reference 9; WBPearson, "A Hand Book of Lattice Spacin").
g and Structures of Materials and Alloys ", (1958) Pe
rgamon Press, London p. 251). Of these, TiGe ₂
Has a eutectic point lower than that of TiSi ₂ by 400 ° C. or more (TiSi ₂ : 1330 ° C., TiGe ₂ : 900 ° C., Ref. 10; TBMassalski, “Binary Alloy Phase Diagram
s ", 3 (1990) ASM International, p.2012-2013,3367,337
0-3371) and low resistance (20 to 35 μΩ · cm) (Reference 11; NATOASI Series E: Applied Sciences 22).
2 (1992) (US) SPAshburn and MCOzuturk, p.375).

Further, several examples of using germanide instead of silicide as an electrode material have been reported (Reference 5). Germanidation is performed in the same manner as silicidation, and the germanidation process is similar to that of silicidation (Reference 12; Mat.Res. Soc. Symp. Proc. 47 ( 1
985) ED Marshall et al. P. 161). Maex (Reference 5)
According to the report, germanide is generally formed at a lower temperature than silicide, and like CoGe ₂ , CoSi ₂
Some are formed at annealing temperatures as low as about 300 ° C. below.

When Ti (Si _1-x Ge _x ) ₂ obtained by adding Ge to TiSi ₂ is used for forming an electrode, the present inventors have found that when x is within a predetermined range, the C49 phase to the C5 phase.
It was found that the phase transition temperature to the 4-phase is lowered and the C54 layer is efficiently formed even in the miniaturized electrode.
The present invention has been completed.

That is, the electrode material according to the present invention is Ti
(Si _1-x Ge _x ) ₂ ; 0.01 ≦ x ≦ 0.25.

With respect to the Ge concentration x of Ti (Si _1-x Ge _x ) ₂ , x = 0%, 30%, and 50%, it is reported that the phase transition temperature hardly changes as compared with TiSi ₂ ( References 11 and 12). However, in the electrode material according to the present invention, the Ge concentration x is in the range of 0.01 ≦ x ≦ 0.25, and by suppressing the Ge concentration to a relatively low range, the volume expansion after silicidation is suppressed, and Ti ( Si
_The compressive stress generated in the _1-x Ge _x ) ₂ layer is reduced and C
The phase transition from the 49th phase to the C54 phase is promoted. Therefore, the C54 layer can be efficiently formed even in the miniaturized electrode, and the increase in resistivity can be suppressed.

Further, the method for producing an electrode material according to the present invention is characterized in that a Ti-Ge alloy layer is formed and this is silicified.

As a method of forming a Ti (Si _1-x Ge _x ) ₂ layer, a method of sequentially forming a Ge layer and a Ti layer on Si and silicidation has been reported (Reference 11).

FIGS. 15 (a) and 15 (b) are schematic cross-sectional views shown for explaining the method, and 14 in the drawing shows a Ge layer. The Ge layer 14 is formed on the Si substrate 1 and the polycrystalline Si layer 4, and the Ti layer 7 is formed on the Ge layer 14.
Are formed (a). This is annealed to form Ti (Si _1-x Ge _x ) ₂ thin wires 6 (b).

However, in the method shown in FIGS. 15 (a) and 15 (b), Ti is caused by volume expansion after silicidation.
(Si _1-x Ge _x ) _{2 A} thin wire 6 is subjected to compressive stress and C4
The phase transition from the 9th phase to the C54 phase may be suppressed.

According to the method for producing an electrode material of the present invention, a Ti _1-y Ge _y alloy layer having a volume expansion coefficient after silicidation smaller than that of the Ti layer 7 is formed and annealed. As a result of the silicidation, the compressive stress due to the volume expansion after silicidation is reduced, and the phase transition from the C49 phase to the C54 phase can be efficiently promoted.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an electrode material according to an embodiment of the present invention and a manufacturing method thereof will be described with reference to the drawings. The components having the same functions as the conventional ones are designated by the same reference numerals.

FIGS. 1A and 1B are schematic cross-sectional views showing the method of manufacturing an electrode material according to the embodiment in the order of steps. In the figure, reference numeral 1 denotes a Si substrate that has been subjected to RCA cleaning, and source / drain diffusion layers 2 are formed at a plurality of predetermined locations on the Si substrate 1. A gate oxide film 3 having a predetermined thickness is formed on the Si substrate 1 between the source / drain diffusion layers 2 and 2. LP is formed on the gate oxide film 3.
A polycrystalline Si layer 4 having a predetermined film thickness by the CVD (Low Pressure Chemical Vapor Deposition) method and then having a predetermined line width is formed by a lithography process.
In the method of manufacturing the electrode material according to the embodiment, Ti ₁ is sputtered on the polycrystalline Si 4 and at predetermined locations on the source / drain diffusion layer 2 of the Si substrate 1 by using the apparatus shown in FIG. _-y Ge _y layer 5 is formed to a predetermined thickness (a).

The thickness of the Ti _1-y Ge _y layer 5 is Ti (Si
_1-x Ge _x ) ₂ The value of x in the thin wire 6 is 0.01 ≦ x ≦
The value is set based on Table 1 described below so as to be in the range of 0.25. As the evaporation source 13 (FIG. 13) at the time of film formation, _one having the same composition as the Ti _1-y Ge _y layer 5 is used. Next, this is annealed to form Ti (Si _1-x Ge _x ) ₂ thin wires 6 (b).

The Ge concentration to be added and the film thickness of the Ti _1-y Ge _y layer can be easily estimated by the following calculation.

[0028] _{<Ti (Si 1-x Ge} x) calculation of Ti _1-y Ge composition ratio of _y y and the thickness h to form a _{2> where, Ti (Si 1-x Ge} x) 2 Phase is Ti _1-x Si
Since it is considered that two phases, the _{2 (1-x)} phase and the Ti _x Ge _2x phase, are in solid solution, it is assumed that the lattice constant after solid solution complies with the Vegard law. At this time, Ti (Si
_In the case of forming _1-x Ge _x ) ₂ , for each phase before solid solution, 1) Ti film thickness: (1-x) t [Equation 1] in Ti _1-x Si _{2 (1-x)} phase Si film thickness: 2.27 (1-x) t [Equation 2] is required, and Ti _1-x Si _{2 (1-x)} phase with film thickness 2.51 (1-x) t [Equation 3] Is formed.

2) In the Ti _x Ge _2x phase, Ti film thickness: xt [Equation 4] Ge film thickness: 2.36 xt [Equation 5] is required, and Ti _x Ge _2x having a film thickness of 2.62 xt [Equation 6] is required. A phase is formed.

Here, the film thicknesses of the Ge layer and the Ti _x Ge _2x layer were obtained from the lattice constant differences with Si and TiSi ₂ , respectively. The thickness of the formed Ti (Si _1-x Ge _x ) ₂ layer is the sum of [Equation 3] and [Equation 6]: 2.51 (1-x) t + 2.62xt = (2.51 + 0.11x ) T [Equation 7] is given.

By using the above calculation method, for example, the Ti (Si _1-x Ge _x ) ₂ layer is formed from the film thickness and Ge concentration of the Ti (Si _1-x Ge _x ) ₂ layer after silicidation. Required for achieving Ti _1-y Ge _y layer thickness h and composition ratio y
Can be obtained as follows.

For example, Ti (Si _1-x G) with a film thickness of 70 nm
In the case of forming a silicide layer of e _x ) ₂ (Ge concentration x = 0.01), this layer is Ti _0.01 Ge _0.02 and Ti _0.99 Si.
Assuming that the two layers of _1.98 are formed as a solid solution, the required thickness t of the Ti layer is (2.51 + 0.11 × 0.01) t = 70 from the above [Equation 7].
= 27.88 nm. If this is used, the film thickness of the Ti _0.01 Ge _0.02 layer will be 2.62 × 0.01 × 27.88 = 0.73 (nm) of the Ti layer required for forming the Ti _0.99 Si _1.98 layer from [Equation 6]. From [Equation 1], the film thickness is (1-0.01) × 27.88 = 27.60 (nm). Here, the Ti _1-y Ge _y phase before silicidation is a state in which two phases of Ti for forming the Ti _0.01 Ge _0.02 phase and the Ti _0.99 Si _1.98 phase are in solid solution, and the lattice constant thereof is Vegard. Assuming that the rule is followed, the thickness of the Ti _1-y Ge _y layer formed before silicidation is given by the sum of the thicknesses of the two layers.

0.73 + 27.60 = 28.33 Therefore, h = 28.33 (nm) On the other hand, the composition ratio of Ti and Ge after silicidation is Ti: Ge = 1: 0.02. Since y is (1-y): y = 1: 0.02, y = 0.02.

From the above results, for example, in order to form a silicide layer of Ti (Si _1-x Ge _x ) ₂ (Ge concentration x = 0.01) having a film thickness of 70 nm, T
A film having a composition of i _0.98 Ge _0.02 may be grown to a film thickness of 28.33 nm.

Similarly, the conditions for forming a Ti (Si _1-x Ge _x ) ₂ layer (Ge concentration 0 ≦ x ≦ 0.50) having a film thickness of 70 nm when the Ge concentration x is changed are as follows: ) Ti (Si _1-x Ge _x ) ₂ is added to Ti layer, Ge layer and S
In the case of forming a multilayer film of the i layer, 2) when Ti (Si _1-x Ge _x ) ₂ is formed of the Ti _1-y Ge _y layer and the Si layer, each is shown in Table 1 below. No. in Table 1 Is each composition No. And the range of Ge concentration x according to the example is marked with *. Further, the data of Ge concentration x and Si layer film thickness in Table 1 are data common to both cases 1) and 2).

[0036]

[Table 1]

Generally, when forming a film of a compound, an alloy, or the like by a sputtering method or an electron beam evaporation method, the composition between the evaporation source and the formed thin film is different due to the difference in vapor pressure of the substances constituting the evaporation source. It is known that the deviation of However, in the case of Ti and Ge, since the difference in vapor pressure is small, the compositional deviation can be ignored. Therefore, for example, Ti _1-y Ge _y (0.02 ≦ y ≦ 0.
In order to form a film of composition 33), Ti _1-y Ge _y (0.02 ≦ y ≦), which is an evaporation source having the same composition as this film composition, is formed.
0.33) may be used.

On the other hand, as an evaporation source for forming the Ti _1-y Ge _y layer, a method of simultaneous sputtering or simultaneous vapor deposition of two evaporation sources of Ti and Ge can be considered, but the cost of the evaporation source and the apparatus cost Considering such points, Ti _1-y
It is desirable to use one evaporation source of Ge _y composition.

[0039]

EXAMPLES AND COMPARATIVE EXAMPLES Examples and comparative examples of the electrode material and the manufacturing method thereof shown in FIGS. 1A and 1B will be described based on Experimental Examples 1 to 4 below.

<Experimental Example 1> FIGS. 2A to 2D are schematic sectional views showing a method for manufacturing an electrode material in Experimental Example 1. In Experimental Example 1, the composition Nos. 1 to 1
2, the thickness of the polycrystalline Si layer 4, the Ti _1-y Ge _y layer 5
Based on the data on the film thickness h and the composition ratio y of Ti (S
The i _1-x Ge _x ) ₂ thin wire 6 was produced. The above composition No. Comparative Example 1 (x = 0), Examples 1-6 (x = 0.01,
0.05, 0.10, 0.15, 0.20, 0.2
5), Comparative Examples 2 to 6 (x = 0.30, 0.35, 0.4
0, 0.45, 0.50).

First, RCA-cleaned p-Si (10
0) A thermal oxide film (SiO ₂ ) 3a having a film thickness of 70 nm is formed on a substrate (diameter 6 inches, resistivity 10 Ω · cm) 1, and a polycrystalline Si layer 4 is formed thereon by LPCVD.
Was formed to have the film thicknesses shown in Table 1 (a). Next, the polycrystalline Si layer 4 is subjected to a lithography process to form a wiring pattern 4a having a line width of 0.2 to 0.8 μm.
Was formed (b). This wiring pattern 4a is subjected to the following steps, and Ti (Si _1-x Ge _x ) ₂ thin wires 6 (x = 0 to 0.
50) respectively.

First, using the apparatus shown in FIG. 13, Ti _1-y
Composition _{Ge y (y = 0~0.50) Ti} 1-y Ge y layer 5 thickness h by a sputtering method using a vapor source 13 the composition of shown in each of Table 1 No. It was formed to have a value of 1 to 12 (c). RF power during film formation is 2k
W, Ar gas pressure 8 mTorr, substrate temperature room temperature (25
° C).

Next, the above sample was subjected to RTP (Rapid Thermal Pr
o ss) and then annealed at 850 ° C. for 20 seconds to form Ti (Si _1-x Ge _x ) with a film thickness of about 70 nm.
_Two fine lines 6 were formed (d).

Unreacted Ti _1-y Ge _y on the thermal oxide film 3a
Was removed with dilute HF.

The prepared Ti (Si _1-x Ge _x ) ₂ thin wire 6
The composition was measured by Auger electron spectroscopy (AES), and it was confirmed that the composition was almost the same as the target composition.

(1) Line Width Dependence of Ratio Z of C54 Phase Ti (Si _1-x Ge _x ) prepared in Experimental Example 1 above
₂ The crystal structure of the thin line 6 was examined by the X-ray diffraction (XRD) method. The C49 phase is on the (131) plane, and the C54 phase is (31
They were strongly oriented in the 1) plane. Where Ti (Si
_In order to evaluate the proportion of the C54 phase in the _1-x Ge _x ) ₂ thin wire 6, a parameter Z (hereinafter, simply referred to as Z) as shown in the following [Formula 8] was defined.

[0047]

(Equation 8)

Here, I _C54 (311) and I _C49 (1
31) is the C54 phase (311) plane and C49 phase, respectively.
The X-ray diffraction intensity from the (131) plane of the phase is shown.

FIG. 3 shows the Ti (S
i _1-x Ge _x ) ₂ thin line 6 (for example, Comparative Example 1 (x =
0), Example 1 (x = 0.01), Example 4 (x = 0.
15), Example 6 (x = 0.25), Comparative Example 6 (x =
6 is a graph showing the relationship between the ratio Z of the C54 phase and the line width in the case (0.50)).

As is apparent from FIG. 3, when Ge was not added (Comparative Example 1 (x = 0)), the line width was about 0.5.
When the line width was 0.2 μm or less, the ratio Z of the C54 phase decreased sharply, and Z = 0 when the line width was 0.20 μm or less. When Ge is added more than necessary (Comparative Example 6
(X = 0.50)), when the line width is about 0.45 μm or less, the ratio Z of the C54 phase sharply decreases.
When the thickness was 20 μm or less, the ratio Z of the C54 phase was about 0.4 or less. On the other hand, when Ge is added in a predetermined amount (Examples 1, 4, 6 (x = 0.01, 0.15,
0.25)) has a line width in the range of 0.2 to 0.8 μm and the ratio Z of the C54 phase is 0.5 or more.
The value was better than that of the electrode material according to 6 (x = 0, 0.50).

As explained above, the Ge concentration X is 0.0
Examples 1 to 6 in which 1 ≦ X ≦ 0.25 (composition N
o. In the electrode materials according to 2 to 7), since the phase transition from the C49 phase to the C54 phase is promoted, it was possible to efficiently form the C54 phase even in the miniaturized electrode.

(2) Line Width Dependence of Sheet Resistance R Ti (Si _1-x Ge _x ) produced in Experimental Example 1 above
The sheet resistance R of the ₂ wire 6 was determined by Kelvin method is a kind of four-terminal method.

FIG. 4 shows the Ti (S
i _1-x Ge _x ) ₂ thin line 6 (for example, Comparative Example 1 (x =
0), Example 1 (x = 0.01), Example 4 (x = 0.
15), Example 6 (x = 0.25), Comparative Example 6 (x =
6 is a graph showing the relationship between the sheet resistance R and the line width in the case (0.50)).

As is clear from FIG. 4, the relationship between the sheet resistance R and the line width corresponds to the relationship between the ratio Z of the C54 phase Z and the line width described in FIG. 3, and Ge was not added. In the case (Comparative Example 1 (x = 0)), the sheet resistance sharply increases when the line width is about 0.5 μm or less, and particularly the line width is 0.20.
When the thickness is less than μm, the sheet resistance R is about 60Ω ・ c
m. Also, when Ge is added more than necessary (Comparative Example 6 (x = 0.50)), the sheet resistance sharply increases when the line width is about 0.45 μm or less, and particularly, the line width of 0.
When the thickness is 20 μm or less, the sheet resistance R is about 30Ω
・ It became cm. On the other hand, when a predetermined amount of Ge was added (Examples 1, 4, 6 (x = 0.01, 0.15, 0.
25)) has a sheet resistance R of 10 Ω · cm or less in the line width range of 0.2 to 0.8 μm.
The value was better than that of the electrode material according to No. 6 (x = 0, 0.50).

As described above, the Ge concentration X is 0.01 ≦ X ≦ 0.2.
In the electrode materials according to Examples 1 to 6 (composition Nos. 2 to 7) in the range of 5, the increase rate of sheet resistance could be suppressed to a low level even when the line width was reduced.

<Experimental Example 2> In the following, Ti (Si _1-x Ge)
The stress in the Ti (Si _1-x Ge _x ) ₂ phase when the Ge concentration x in the _x ) ₂ phase is changed within the range of 0 ≦ x ≦ 0.50 will be described with reference to FIGS.

In Experimental Example 2, composition Nos.
1-12 film thickness of polycrystalline Si layer 4, Ti _1-y Ge
_{Based on} the data on the film thickness and composition of the _y layer 5, Ti (S
An i _1-x Ge _x ) ₂ layer 6 ′ was prepared. The above composition No. Comparative Example 7 (x = 0) and Examples 7-12 (x = 0.0)
1, 0.05, 0.10, 0.20, 0.25), Comparative Examples 8 to 12 (x = 0.30, 0.35, 0.40, 0.
50).

FIGS. 5A and 5B show T in Experimental Example 2.
FIG. 6 is a schematic cross-sectional view showing a method of manufacturing an i (Si _1-x Ge _x ) ₂ layer 6 ′ in the order of steps.

First, p-Si (10
0) A thermal oxide film (SiO ₂ ) 3a having a film thickness of 70 nm is formed on a substrate (diameter 6 inches, resistivity 10 Ω · cm) 1, and a polycrystalline Si layer 4 is formed thereon by LPCVD.
Were formed on the entire surface of the thermal oxide film 3a so that the film thicknesses thereof were the values shown in Table 1. Ti _1-y G is formed on the polycrystalline Si layer 4.
A Ti _1-y Ge _y layer 5 is formed by targeting e _y (y is each value in Table 1) (a), and this is silicidized to form a Ti (Si _1-x Ge _x ) ₂ layer 6 ′ ( x formed the respective values in Table 1) (b). 8 for silicidation
It was performed by annealing at 50 ° C. for 20 seconds.

The Ti (Si
The stress of the _1-x Ge _x ) ₂ layer 6 ′ was measured by the Newton ring method. Further, the crystal structure was examined by an X-ray diffraction (XRD) method, and the ratio of C54 phase was obtained. The ratio of the C54 phase was evaluated by the above parameter Z.

FIG. 6 shows the Ti (S
9 is a graph showing the relationship between the Ge concentration x of the i _1-x Ge _x ) ₂ layer 6 ′ and the stress. In the figure, A indicates the range of the example, and in particular, from the left in the graph, comparative example 7 (x = 0), example 7 (x = 0.01), example 9 (x = 0.10), Example 10 (x = 0.15), Example 11 (x = 0.2)
0), Example 12 (x = 0.25), Comparative Example 10 (x =
0.40) and Comparative Example 12 (x = 0.50) are shown as data points.

As is clear from FIG. 6, Ti (Si _1-x
The stress of Ge _x ) ₂ layer 6 ′ is such that the value of Ge concentration x is 0 ≦ x ≦
In the range of 0.15, it decreases with the increase of x, and x is 0.1
5 (Example 10), the minimum value (10 ⁹ dyne / cm ²⁾
Below). Further, the value of Ge concentration x is 0.15 ≦ x
In the range of ≦ 0.50, the stress increases with the increase of x, and x
Was larger than 0.25 (Example 12), the stress was larger than that when Ge was not added (Comparative Example 7). That is, it was found that the stress was reduced by adding Ge when the Ge concentration x was in the range of 0.01 ≦ x ≦ 0.25.

FIG. 7 shows the Ti (S
It is a figure showing ratio Z of C54 phase to Ge concentration x of i _1-x Ge _x ) ₂ layer 6 '. In the figure, A shows the range of the example, and the same data points as in the case of FIG. 6 are shown in the graph.

As is apparent from FIG. 7, when the Ge concentration x is 0.01 ≦ x ≦ 0.25 (Examples 7 to 12)
(Composition Nos. 2 to 7)), the ratio Z of the C54 phase was approximately 1, and good results were obtained.

FIG. 8 shows the Ti (S
It is a figure showing the relation between the stress of the i _1-x Ge _x ) ₂ layer 6 ′ and the ratio Z of the C54 phase. Data points similar to those in the case of FIG. 6 are shown in the graph.

As is clear from FIG. 8, the ratio Z of the C54 phase increases as the stress decreases, and for example, the stress becomes 10
Ratio of C54 phase when it is ¹⁰ dyne / cm ² or less Z
Is approximately 1. That is, the decrease in stress makes the phase transition from the C49 phase to the C54 phase smooth.

As described above, Ti (Si _1-x Ge
_x ) When the Ge concentration x of the _two- layer 6 ′ is in the range of 0.01 ≦ x ≦ 0.25 (Examples 7 to 12 (composition No. 2 to
7)), the stress in the Ti (Si _1-x Ge _x ) ₂ layer 6 ′ is reduced to, for example, 10 ¹⁰ dyne / cm ² or less, and the ratio Z of the C54 phase is good at about 1 due to the decrease in the stress. Value.

<Experimental Example 3> Ti _{1-y is formed} before silicidation.
The following experiment was conducted in order to investigate the effect of forming the Ge _y layer. In Experimental Example 3, composition Nos. Film thickness of polycrystalline Si layer 4 in 1 to 7, Ti _1-y
A Ti (Si _1-x Ge _x ) ₂ thin wire was prepared based on the data on the film thickness h of the Ge _y layer 5 and the composition ratio y, and the composition N
o. Comparative Example 13 and Examples 13 to 18 (x = 0, 0.
01, 0.05, 0.10, 0.15, 0.20, 0.
25).

Regarding the method for producing the Ti (Si _1-x Ge _x ) ₂ thin wire, the following new method was adopted.

FIGS. 9A and 9B show T in Experimental Example 3.
FIG. 3 is a schematic cross-sectional view showing a method for manufacturing an i (Si _1-x Ge _x ) ₂ thin wire, in which 7 denotes a Ti layer and 8 denotes a Ge layer.

In the method shown in FIG. 9A, first, Ti is deposited on the polycrystalline Si layer 4 by a sputtering method.
And a Ge target were used to sequentially form a Ti layer 7 and a Ge layer 8. Further, in the method shown in FIG. 9B, first, the Ge layer 8 and the T layer are formed on the polycrystalline Si layer 4 by a sputtering method using Ge and Ti targets.
The i layer 7 was sequentially formed.

In each case, an annealing process is performed thereafter to form the Ti (Si _1-x Ge _x ) ₂ thin wire (x = 0 to 0.25) in Experimental Example 3.

The RF power, the Ar gas pressure, the substrate temperature, and the subsequent annealing treatment conditions at the time of film formation by sputtering are the same as in Experimental Example 1.

The evaluation of the produced Ti (Si _1-x Ge _x ) ₂ thin wire was performed by the X-ray diffraction (XRD) method and the Kelvin method, as in the case of Experimental Example 1.

(1) Line Width Dependence of C54 Phase Ratio Z FIG. 10 shows Ti produced by the method shown in FIG.
(Si _1-x Ge _x ) ₂ thin line (for example, Comparative Example 13 (x =
0), Example 16 (x = 0.15), Example 18 (x =
0.25)), the line width and the C54 phase ratio Z
FIG. 11 is a diagram showing a relationship with the relationship between FIG. 11 and FIG. 11 in a Ti (Si _1-x Ge _x ) ₂ thin wire (for example, similar to the case of FIG. 10) manufactured by the method shown in FIG. 9B. Line width and C
It is the figure which showed the relationship with the ratio Z of 54 phases.

Ti (Si _1-x Ge) in FIGS.
_x ) ₂ thin lines (for example, Comparative Example 13 (x = 0), Example 1)
6 (x = 0.15), Example 18 (x = 0.25)) and the Ti (Si _1-x Ge _x ) ₂ thin wire 6 in FIG. 3 (Comparative Example 1 (x = 0) as an example). , Example 4 (x = 0.
15) and the comparison with Example 6 (in the case of x = 0.25)), Ti (Si _1-x produced in Experimental Example 3 is clear.
In the Ge _x ) ₂ thin wire (Comparative Example 13, Examples 13 to 18), the Ti (Si _1-x Ge _x ) ₂ thin wire 6 (Comparative Example 1 produced in Experimental Example 1 and having the same composition as Experimental Example 3 was compared. Than in Example 1 and Examples 1-6), the proportion Z of C54 phase with decreasing line width
The rate of decrease of each was large.

As described above, in the manufacturing method in which the Ti layer 7 and the Ge layer 8 are sequentially formed and then silicidized, or the Ge layer 8 and the Ti layer 7 are sequentially formed and then silicidized, the manufactured Ti (Si The stress of the _1-x Ge _x ) ₂ thin wire cannot be sufficiently reduced, and the phase transition from the C49 phase to the C54 phase cannot be sufficiently promoted. On the other hand, as a layer formed before silicidation, Ti _1-y Ge _{y is formed.}
By forming the layer 5 (Experimental example 1), the phase transition from the C49 phase to the C54 phase can be sufficiently promoted.

<Experimental Example 4> In the method of forming the Ti _1-y Ge _y layer 5, Ti _1-y Ge was used as the evaporation source 13 (FIG. 13).
To investigate the effect of using _y alloy, Ti and Ge
Ti (Si _1-x Ge _x ) ₂ thin wire 6 by simultaneous sputtering (not shown) using two evaporation sources of
A Ti (Si _1-x Ge _x ) ₂ thin wire similar to that shown in FIG. 2D was prepared. The Ti (Si _1-x Ge _x ) ₂ thin wire has composition No. 1 in Table 1. 2 to 7, the thickness of the polycrystalline Si layer 4, T
It was prepared based on the data on the film thickness and composition of the i _1-y Ge _y layer 5. Example 19 in order
-24 (x = 0.01, 0.05, 0.10, 0.1
5, 0.20, 0.25).

Ti _1-y Ge _y was used as the evaporation source 13,
In the case of the above-mentioned Experimental Example 1 in which sputtering was performed (Example 1
6) and two evaporation sources of Ti and Ge as the evaporation source 13, the cost of the evaporation source 13 and the sputtering apparatus in both of the cases of Experimental Example 4 (Examples 19 to 24) in which co-sputtering was performed. The cost of and the comparison result are explained below.

(1) Cost of evaporation source (target) When two evaporation sources of Ti and Ge are used (Examples 19 to 19)
In the case of 24), the cost was about twice that of the case of using Ti _1-y Ge _y as the evaporation source (Examples 1 to 6).
Further, when the two evaporation sources are arranged in the sputtering apparatus, the cost is further increased due to the necessity of bonding the evaporation sources.

(2) Cost of thin film forming apparatus (sputtering apparatus) When two targets of Ti and Ge are simultaneously sputtered (Examples 19 to 24), Ti _1-y Ge _y is sputtered (Example 1). ~ 6), the control device for sputtering is complicated and the vacuum chamber 11 (Fig. 13)
The cost has increased by 1.5 to 2 times due to the increase in size.

As described above, in the method of forming the Ti _1-y Ge _y phase, the cost is reduced by using the Ti _1-y Ge _y alloy containing two kinds of elements, Ti and Ge, as the evaporation source. I was able to.

As described in detail above, in the electrode materials according to the examples, the Ge concentration X is in the range of 0.01 ≦ X ≦ 0.25, and the Ge concentration is suppressed to a relatively low range, and after the silicidation, Volume expansion of Ti (Si
_The compressive stress generated in the _1-x Ge _x ) ₂ thin wire 6 is reduced, and the phase transition from the C49 phase to the C54 phase is promoted. Therefore, the C54 phase can be efficiently formed even in the miniaturized electrode, and the increase in resistivity can be suppressed.

Further, according to the method of manufacturing the electrode material in the example, the Ti _1-y Ge _y layer 5 having a volume expansion coefficient after silicidation smaller than that of Ti is formed, and the annealing treatment is performed on the Ti _1-y Ge _y layer 5. Since silicidation is performed, compressive stress due to volume expansion after silicidation is reduced, and C49 phase to C
The phase transition to the 54 phase can be efficiently promoted. Further, by using Ti _1-Y Ge _Y containing two kinds of elements, Ti and Ge, as the evaporation source for forming the electrode material, the cost of the evaporation source and the cost of the sputtering apparatus can be reduced. Further, by setting the composition ratio to Ti _1-Y Ge _Y (0.02 ≦ y ≦ 0.33) shown in Table 1, after the silicidation, Ti (Si _1-x Ge _Y
A given electrode material having a composition of _x ) ₂ (0.01 ≦ x ≦ 0.25) can be manufactured.

[Brief description of drawings]

1A and 1B are schematic cross-sectional views showing, in the order of steps, a method for manufacturing an electrode material according to an embodiment of the present invention.

2A to 2D are schematic cross-sectional views showing a method of manufacturing an electrode material according to an experimental example in the order of steps.

FIG. 3 shows the width of Ti (Si _1-x Ge _x ) ₂ thin wire and C54.
7 is a graph showing the relationship with the phase ratio Z.

FIG. 4 is a graph showing a relationship between a line width of a Ti (Si _1-x Ge _x ) ₂ thin wire and a sheet resistance.

5A and 5B are schematic cross-sectional views showing, in the order of steps, a method for manufacturing an electrode material according to another experimental example.

FIG. 6 Ge concentration x and Ti (Si _1-x Ge _x ) to be added
It is a graph showing the relationship with the stress of _two layers.

FIG. 7 is a graph showing the relationship between the added Ge concentration x and the ratio Z of the C54 phase.

FIG. 8 is a graph showing the relationship between the stress of the Ti (Si _1-x Ge _x ) ₂ layer and the proportion Z of the C54 phase.

9 (a) and 9 (b) are still another experimental example.
FIG. 3 is a schematic cross-sectional view showing a method of forming different Ti (Si _1-x Ge _x ) ₂ thin wires.

FIG. 10 shows Ti (Si _1-x G in yet another experimental example.
3 is a graph showing the relationship between the line width of the e _x ) ₂ thin line and the ratio Z of the C54 phase.

FIG. 11 shows Ti (Si _1-x G in yet another experimental example.
3 is a graph showing the relationship between the line width of the e _x ) ₂ thin line and the ratio Z of the C54 phase.

12A and 12B are schematic cross-sectional views showing a general method for forming a TiSi ₂ layer.

FIG. 13 is a schematic cross-sectional view showing a general device used in a sputtering method.

FIG. 14 is a schematic enlarged cross-sectional view showing a state of a phase transition from a C49 phase to a C54 phase.

15 (a) and 15 (b) are conventional Ti (Si _1-x Ge).
_x ) ₂ is a schematic cross-sectional view showing a method for forming a thin wire.

[Explanation of symbols]

5 Ti _1-y Ge _y layer (Ti-Ge alloy layer)

Claims (2)

[Claims] 1. Ti (Si _1-x Ge _x ) ₂ ; 0.01 ≦
An electrode material for a semiconductor device, wherein x ≦ 0.25. 2. The method for producing an electrode material according to claim 1, further comprising the step of forming a Ti—Ge alloy layer and siliciding it.