KR20010055226A - Field Emission Display Device and Method of Fabricating the same - Google Patents

Abstract

PURPOSE: A field emission display element having an enhanced light emitting uniformity and a method of producing the same is provided to improve the emission uniformity by mounting resistors having uniform value at an electrode. CONSTITUTION: The field emission display element includes a plurality of pixels. These pixels comprise a planar emitter for emitting an electron with the aid of voltage applied between an anode(72) and a gate electrode(74), the planar emitter being formed between the anode(72) and the gate electrode(74); and an upper electrode formed on the anode(72) and the gate electrode(74) through an insulated layer. At this time, the upper electrode is connected with the gate electrode(74) through a hole(80) formed at the insulated layer. The pixels further comprise a resistance material layer(82) is connected with the anode(72) or the gate electrode(74) in series. Thereby, the pixels uniformly emit the electron, respectively.

Description

Field emission display device and method of manufacturing the same {Field Emission Display Device and Method of Fabricating the same}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a field emission display device and a method of manufacturing the same, and more particularly, to a field emission display device having improved light emission uniformity and a method of manufacturing the same.

Compared to cathode ray tubes (hereinafter referred to as "CRTs"), which have been mainly used for display means, research into flat panel display devices, which are next-generation display devices capable of low weight and thinness, is being actively conducted. In particular, there is a growing interest in field emission display devices (hereinafter referred to as "FEDs") that can solve problems caused by viewing angles and luminance of liquid crystal displays (LCDs) among flat panel display devices. FED has a disadvantage in that it is more difficult to make a larger screen than a liquid crystal display or a plasma display panel (PDP) .However, like the CRT, FED uses the light emitted from the phosphor by the electron beam. The advantage is that it can be implemented as a reputation. In general, the FED uses a sharp cold cathode instead of the hot cathode used in the conventional CRT as a means for emitting accelerated electrons to excite the phosphor. That is, by concentrating the high field on the emitter constituting the cold cathode, electrons are emitted by the quantum mechanical tunnel effect.

1 is a longitudinal cross-sectional view showing the basic structure of a FED having a conventional tip-type emitter. Referring to FIG. 1, a conventional FED includes a cathode 22 formed on a lower substrate 20, an emitter 24 formed in a tip shape on the cathode 22, and an emitter 24 interposed therebetween. An insulating layer 26 and a gate electrode 28 sequentially stacked on the 22, an upper substrate 32 disposed to face the lower substrate 20 with a spacer 30 therebetween, An anode 34 formed on the upper substrate 32, the anode 34 and the phosphor 36 and the black matrix 38 applied on the upper substrate 32 are provided.

Looking at the process of generating visible light in the FED of the three-electrode structure shown in Figure 1, first, a high electric field between the cathode 22 and the gate electrode 28 by the voltage applied to the cathode 22 and the gate electrode 28 Is formed. This high field causes emitter 24 to release electrons into the vacuum. The emitted electrons are accelerated by the voltage applied between the cathode 22 and the anode 34 to impinge on the phosphor 36 formed on the upper substrate 32. At this time, the phosphor 36 is excited to emit visible light, thereby realizing an image of the FED. Meanwhile, in FIG. 1, the spacer 30 serves to provide a space at a predetermined interval between the upper plate 42 and the lower plate 40 so that the electrons emitted from the emitter 24 are sufficiently accelerated. In addition, by supporting the upper plate 42 and the lower plate 40 serves to prevent the panel from being damaged by the internal and external pressure difference. Each of the subcells 44 forming the pixel unit is distinguished from each other by the black matrix 38 formed on the upper plate 42. Each subcell 44 is coated with different phosphors, that is, phosphors of red (R), green (G), and blue (B), respectively, to adjust the color of the screen by mixing the visible light generated from each of the phosphors 36. Will be implemented.

The emitter 24 emitting the accelerated electrons from the FED is one of the important factors that determine the image quality of the FED. When the emitter 24 is unevenly formed in the panel manufacturing process or when the characteristics of the emitter 24 are deteriorated as time deteriorates during use, the electron emission efficiency of the emitter 24 is lowered. The amount of visible light generated varies by 44), resulting in deterioration of display quality or deterioration of luminance. As the type of emitter generally used in the related art, a tip shape that is formed to be relatively easy to emit electrons as shown in FIG. 1 is representative. A detailed view of the emitter structure in the form of a tip is shown in FIG. 2. However, in the tip-type emitter structure, the phenomenon of spreading of the electron beam emitted from the emitter 24 is generated, so that beam focusing is required, and the focusing electrode has to be separately formed. The tip-type emitter 24 is mainly manufactured in a spindt method, and the process for manufacturing the emitter is complicated and difficult. In addition, in the case of manufacturing in a large area, the shape of each tip may be non-uniform, so that the large screen is difficult. In addition to these problems, there is a fundamental problem that the tip-type emitter structure has a severe characteristic change due to deterioration of the tip during use (that is, a change in the radius of the tip end or melting). Recently, a planar emitter has been proposed for the purpose of solving the problems of the conventional tip-type emitter structure and lowering the unit cost in the manufacturing process.

3A to 3C are schematic views illustrating a bottom plate structure of a FED equipped with a conventional surface conduction planar emitter. 3A is a diagram illustrating a planar structure of an emitter and an electrode formed in one pixel cell constituting the FED. 3B and 3C are cross-sectional views taken along lines A-A 'and B-B', respectively, in FIG. 3A. The top plate structure in which the anode and the phosphor are formed is the same as that of the FED having the tip type emitter shown in FIG. 3A to 3C, a conventional FED having a planar emitter is provided with a cathode 52 and a gate electrode 54 separated from each other by a predetermined distance on a lower substrate 50, and a cathode 52 and a gate electrode. A planar emitter 56 formed by coating a thin layer in a planar shape between the 54 and an insulating layer 58 having a uniform thickness on the lower substrate 50 on which the cathode 52 and the gate electrode 54 are formed. The through hole 60 formed by partially etching the insulating layer 58 on the gate electrode 54 and the through hole formed on the insulating layer 58 in a direction crossing the cathode 52 and the gate electrode 54. The upper electrode 62 is connected to the gate electrode 54 via the 60. An enlarged view of the planar emitter 56 portion in FIG. 3A is shown in FIG. 4.

The principle of electron emission in the surface conduction planar emitter 56 will first be described. First, the local melting of the emitter material in the planar emitter 56 when a voltage is applied between the cathode 52 and the gate electrode 54. As a result, as shown in FIG. 4, a gap Gap of several tens of nm is formed in the center of the emitter 56. This is called an electro-forming process. After this process, electrons are tunneled from the cathode 52 to the gate electrode 54 by the electric field between the cathode 52 and the gate electrode 54 and tunneled toward the gate electrode 54. Some of the electrons lost energy by the tunneling are driven toward the upper plate 42 by the voltage applied to the anode 34 on the upper plate. At this time, visible light is generated by exciting the phosphor 36 while the accelerated electrons collide with the phosphor 36 formed on the upper plate 42.

Figures 5a to 5e is a diagram showing a step-by-step manufacturing process of the FED bottom plate having a conventional planar emitter. Referring to FIGS. 5A to 5E, a process of forming a lower plate on which a planar emitter is formed will be described. First, in the process of FIG. 5A, a conductive metal is entirely deposited on the lower substrate 50 and then patterned to form a cathode 52 and a gate electrode. Form 54. Al, Cr, Mo, Nb, and the like are used as materials for the cathode 52 and the gate electrode 54, and are formed to a thickness of about 1000 mW. Next, in the process of FIG. 5B, an insulating layer 58 is formed by depositing an insulating material on the lower substrate 50 on which the electrode is formed to a thickness of about 1 μm, and then patterning a predetermined region on the gate electrode 54 through patterning. A through hole 60 is formed in the light emitting portion, and a light emitting portion 64 is formed in a portion where an emitter is formed between the cathode 52 and the gate electrode 54. As the material of the insulating material, SiO ₂ , Al ₂ O ₃ , SiNx, or the like is used. In etching the insulating layer 58 of the through hole 60, the boundary part is formed obliquely to have a predetermined slope to overcome the step problem. In the process of FIG. 5C, the upper electrode 62 is formed on the insulating layer 58 to be connected to the gate electrode 54 through the through hole 60. As the material of the upper electrode 62, the same metal material as that of the cathode 52 or the gate electrode 54 is used, and the thickness of the upper electrode 62 is formed to a thickness of about 3000 kPa to overcome the step problem in the through hole 60. A photoresist mask pattern 66 is then formed in all regions except for the light emitting portion 64 region on the bottom plate as shown in FIG. 5D to form the emitter. Subsequently, the emitter material is entirely deposited on the lower plate on which the photoresist pattern 66 is formed. As the emitter material, an organometallic compound in which the light emitting device undergoes a forming process or a discontinuous conductive particle material which does not undergo a forming process is used. In the case of the organometallic compound, as the composite material in which conductive particles such as Fe are uniformly distributed in an insulating material such as SiO ₂ , the organometallic compound material is formed by depositing a thin film on a lower plate. In the case of using a discontinuous conductive particle material, conductive particles such as Au are formed by depositing on the lower plate so that the particles are discontinuously distributed in the emitter. The deposition thickness of the emitter layer is about 500 GPa or less. Then, when the photoresist pattern 66 layer is etched and exposed using acetone or the like, only the emitter 56 formed in the light emitting part 64 remains, and the rest is removed, thereby completing the lower plate structure as shown in FIG. 5E. Such an emitter manufacturing method is called a lift-off method.

In the FED having the planar emitter structure, as shown in FIG. 4, since a gap in nm is formed, driving is possible even when a low voltage of about 15 V or less is applied between the cathode 52 and the gate electrode 54. In addition, since the spreading of the emitted electron beam is less than that of the tip-type emitter structure, focusing is unnecessary. In addition, the manufacturing process is simple compared to the tip-type emitter structure has an advantage in large area. However, in the FED having the conventional planar emitter 56, the emitter 56 is unevenly formed for each pixel, resulting in uneven light emission characteristics of each pixel. This problem is caused when the emitter material is formed by depositing an emitter material for each pixel, and the particles of emitter 56 are formed to have a non-uniform thickness, or conductive particles which are closely related to electron emission are formed in the emitter 56 of each pixel. Occurs due to uneven distribution. The uniformity of emitter 56 greatly affects the uniformity of electron emission in each pixel and thus the uniformity of emission. Even in the process of forming the actual planar emitter material, it is difficult to uniformly distribute the conductive particles in the insulating material. In the FED having the conventional planar emitter 56, the uniformity of the light emission is lowered in some cells and the light is not emitted in some cells even when the same voltage is applied due to the nonuniformity of the emitter. There is a disadvantage that the luminance deviation occurs.

Accordingly, an object of the present invention is to provide a field emission display device having improved uniformity of light emission and a method of manufacturing the same.

1 is a longitudinal sectional view showing a basic structure of a field emission display device having a conventional tip type emitter.

FIG. 2 is an enlarged cross-sectional view of the tip type emitter shown in FIG. 1. FIG.

3A illustrates a planar structure of one pixel formed on a lower plate of a field emission display device equipped with a conventional surface conduction planar emitter.

3B and 3C are cross-sectional views taken along the lines A-A 'and B-B' shown in FIG. 3A, respectively.

4 is an enlarged view of the planar emitter part shown in FIG. 3A;

5A through 5E are steps of a manufacturing process of a lower plate of a field emission display device having a conventional planar emitter.

6A illustrates a planar structure of one pixel formed on a lower plate of the field emission display device according to the first embodiment of the present invention.

6B and 6C are cross-sectional views taken along the lines A-A 'and B-B' shown in FIG. 6A, respectively.

7A to 7F are steps illustrating a manufacturing process of a lower plate of the field emission display device according to the first embodiment of the present invention.

8A illustrates a planar structure of one pixel formed on a lower plate of the field emission display device according to the second embodiment of the present invention.

8B to 8D are cross-sectional views taken along lines A-A ', B-B', and C-C 'shown in FIG. 8A, respectively.

9A to 9F are steps illustrating a manufacturing process of a lower plate of a field emission display device according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

20,50,70,100: Lower substrate 22,52,72,102: Cathode

24: tip type emitter 26,58,78,108: insulating layer

28, 54, 74, 104: gate electrode 30: spacer

32: upper substrate 34: anode

36: phosphor 38: black matrix

40: lower plate 42: upper plate

44: subcell 56,76,106: planar emitter

60, 80, 110: Through hole 62, 84, 112: Upper electrode

64,86,118: light emitting portion 66,88,120: photoresist pattern

82: resistive layer 114: first resistive layer

116: second resistance layer

In order to achieve the above object, the field emission display device of the present invention may be connected in series to any one of a cathode and a gate electrode which apply a voltage to a planar emitter for each pixel in order to secure electron emission uniformity of each pixel. It has a resistor formed.

A method of manufacturing a field emission display device according to the present invention includes forming a resistor so that each pixel is connected in series to one of a cathode and a gate electrode in order to secure electron emission uniformity of each pixel.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6A to 9F.

6A to 6C illustrate a bottom plate structure of the FED according to the first embodiment of the present invention. 6A is a diagram illustrating a planar structure of an emitter and an electrode formed in one pixel constituting the FED. 6B and 6C are cross-sectional views taken along the AA ′ and BB ′ lines of FIG. 6A, respectively. The top plate structure in which the anode and the phosphor are formed is the same as that of the FED having the conventional tip type emitter shown in FIG. 6A to 6C, the lower plate of the FED according to the first exemplary embodiment of the present invention may include a cathode 72 and a gate electrode 74 separated from each other by a predetermined distance on the lower substrate 70 for each pixel. At least one or more planar emitters 76 formed at the boundary between the cathode 72 and the gate electrode 74 and the lower substrate 70 on which the cathode 72 and the gate electrode 74 are formed. An insulating layer 78 formed on the entire surface with a thickness, a through hole 80 formed by partially etching the insulating layer 78 on the gate electrode 74, and a resistance formed on the gate electrode 74 of the through hole 80. It is formed on the insulating layer 78 in a direction crossing the layer 82, the cathode 72 and the gate electrode 74, and is connected to the gate electrode 74 through the resistive layer 82 of the through hole 80. The upper electrode 84 is provided. In order to form the plurality of emitters 76 in one pixel, a plurality of emitter forming portions are formed at the boundary between the cathode 72 and the gate electrode 74. As the material of the planar emitter 76, an organic metal compound (SiO ₂ + Fe, etc.) material in which the light emitting device is formed or a discontinuous conductive particle (Au, etc.) thin film is not used. The difference between the FED according to the first embodiment of the present invention and the conventional FED shown in FIGS. 3A to 3C is that a plurality of planar emitters 76 are formed in one pixel, and an upper portion of the through hole 80 is formed. The resistive layer 82 is formed between the electrode 84 and the gate electrode 74. In the present invention, the resistive layer 82 is used as a means for ensuring uniformity of emission for each pixel. In addition to amorphous silicon (Amorphous-Silicon), which is a resistor material used in a conventional tip-type emitter, a material having a resistivity value of several 등 such as TaO _x N _y , CuO, AlN is used as the material of the resistive layer 82. do. When the resistive layer 82 is formed for each pixel, the thickness of the resistive layer 82 is adjusted to form a uniform resistance value for each pixel.

The light emitting mechanism of the FED according to the first embodiment of the present invention is similar to that of the FED having a conventional planar emitter. When the emitter material is subjected to the forming process, when a voltage is applied between the cathode 72 and the gate electrode 74, a plurality of planar emitters 76 may cause tens of nm units by local melting of the emitter material. A gap of is formed and undergoes an electro-forming process. After this process, electrons are tunneled from the cathode 72 toward the gate electrode 74 between the gaps in the center of the emitter 76 by the electric field between the cathode 72 and the gate electrode 74. . Some of the electrons lost energy due to tunneling are driven by the voltage applied to the anode on the upper plate and move toward the upper plate. At this time, the accelerated electrons collide with the phosphor formed on the upper plate to excite the phosphor to generate visible light. However, in the present invention, when a voltage is applied between the cathode 72 and the gate electrode 74, a kind of surplus voltage distribution effect is generated between the pixels by the resistance layer 82 uniformly formed for each pixel. If the emitter 76 is unevenly formed in each pixel or the distribution of conductive particles in the emitter 76 is uneven, the electron emission voltage between the pixels is non-uniform, so that the electron emission voltage is lower than that of other pixels. The surplus voltage remaining in the pixels emitting electrons is distributed to other pixels having a high electron emission voltage under the influence of the voltage distribution effect by the resistance layers 82. Accordingly, even though the emitter 76 is somewhat unevenly formed between the pixels, the emitters 76 of all the pixels may eventually perform uniform electron emission, thereby ensuring uniformity of emission for each pixel cell. You can do it. In addition, in the present invention, since a plurality of emitters 76 are formed for each pixel, not only the light emission uniformity can be further improved but also the effect of improving the brightness can be obtained.

The bottom plate forming method of the FED according to the first embodiment of the present invention is as shown in Figures 7a to 7f. First, in the process of FIG. 7A, the conductive metal layer is entirely deposited on the lower substrate 70 and then patterned to form the cathode 72 and the gate electrode 74. In the etching operation of the metal layer using the photoresist mask pattern, a plurality of emitter formation portions are patterned so as to provide a plurality of emitter formation portions at the boundary between the cathode 72 and the gate electrode 74 as shown in the figure. Al, Cr, Mo, Nb, and the like are used as materials for the cathode 72 and the gate electrode 74, and are formed to a thickness of about 1000 mW. Next, in the process of FIG. 7B, an insulating material is entirely deposited on the lower substrate 70 on which the electrode is formed to a thickness of about 1 μm to form the insulating layer 78. Through the patterning operation of the insulating layer 78, a through hole 80 is formed in a predetermined region on the gate electrode 74, and a plurality of emitters are formed at the boundary between the cathode 72 and the gate electrode 74. The light emitting parts 86 are formed. As the insulating material, SiO ₂ , Al ₂ O ₃ , SiNx, or the like is used. When etching the insulating layer 78 of the through hole 80, the boundary portion is formed obliquely to have a predetermined slope to overcome the step problem. Subsequently, in the process of FIG. 7C, the resistive material is patterned in the through hole 80 where the gate electrode 74 is exposed to form the resistive layer 82. In addition to the amorphous silicon, a material having a specific resistance value of about 1 to 5 GPa, such as TaO _x N _y , CuO, AlN, is used as the material of the resistive layer 82. In order to match the resistance value of each pixel, the resistance value is controlled by adjusting the thickness of the resistance layer 82 when the resistance layer 82 is formed. In the present invention, prior to forming the upper electrode 84 in the through hole 80, the resistive layer 82 having a predetermined thickness is formed to effectively prevent a step problem in the through hole 80 when the upper electrode 84 is formed. It becomes possible. After forming the resistive layer 82, in the process of FIG. 7D, the electrode material is patterned on the insulating layer 78 to be connected to the gate electrode 74 through the resistive layer 82 formed in the through hole 80. Electrode 84 is formed. As the material of the upper electrode 84, a metal material used for the cathode 72 or the gate electrode 74 is used. A photoresist mask pattern 88 is then formed in all regions on the bottom plate except for the light emitting portion 86 region as shown in FIG. 7E to form the planar emitter 76. Subsequently, the emitter material is entirely deposited on the lower plate on which the photoresist pattern 88 is formed. As the emitter material, a thin film material composed of organic metal compounds (such as SiO ₂ + Fe) or discontinuous conductive particles (Au) in which metal particles having a low work function are distributed in an insulating material is used as in the prior art. The deposition thickness of the emitter 76 layer is about 500 kPa or less. Then, as shown in FIG. 7F, the photoresist pattern 88 is exposed by a lift-off method, so that the emitter material is formed only on the light emitting portions 86. Complete the bottom plate. When the photoresist pattern 88 layer is etched and exposed using acetone or the like, only the planar emitter 76 formed in the light emitting part 86 remains, and the rest is removed, thereby completing a bottom plate structure as shown in FIG. 7F.

8A to 8D illustrate a bottom plate structure of the FED according to the second embodiment of the present invention. FIG. 8A illustrates a planar structure of an emitter and an electrode formed in one pixel constituting the FED. 8B to 8D are cross-sectional views taken along lines AA ′, BB ′, and CC ′ of FIG. 8A, respectively. The top plate structure in which the anode and the phosphor are formed is the same as that of the FED having the conventional tip type emitter shown in FIG. 8A to 8D, the lower plate of the FED according to the second exemplary embodiment of the present invention may include a cathode 102 and a gate electrode 104 formed on the lower substrate 100 by a predetermined interval for each pixel. At least one or more planar emitters 106 formed at the boundary between the cathode 102 and the gate electrode 104, and the lower substrate 100 on which the cathode 102 and the gate electrode 104 are formed. The insulating layer 108 formed on the entire surface with the thickness, the through-hole 110 formed by partially etching the insulating layer 108 on the gate electrode 104, and the direction crossing the cathode 102 and the gate electrode 104. The upper electrode 112 is formed on the insulating layer 108 and connected to the gate electrode 104 through the through hole 110, and a predetermined resistance value is applied to the gate electrode 104 line for each pixel. The first resistive layer 114 formed in the gate electrode line 104 and a plurality of planar And a second resistance layer 116 is formed in each negative electrode (102) line to give a predetermined resistance to the anode (102) line each connected to the emitter (106). In the case of the second embodiment of the present invention, unlike the first embodiment of the present invention, the upper electrode 112 in the through hole 110 has a first resistance layer 114 for securing the uniformity of light emission between the pixels. Instead of being formed between the gate electrode 104 and the gate electrode 104, the first resistor layer 114 is formed at a position where a gap is formed so that a part of the gate electrode 104 line is disconnected. The line portions of the two gate electrodes 104 which are disconnected from each other are connected via 114. In addition, in the second embodiment of the present invention, the second resistor layer 116 is also formed on the line of the cathode 102 connected to the plurality of planar emitters 106 formed in a plurality of pixels in each pixel, so that each emitter ( Electron emission uniformity and light emission uniformity between the two layers. Features of the electrode portion, the insulating layer, and the emitter material and thickness are the same as those of the first embodiment of the present invention. As the material of the first and second resistive layers 114 and 116, a material having a resistivity value of several orders of magnitude, such as amorphous silicon, TaO _x N _y , CuO, AlN, or the like is used.

Even in the case of the second embodiment of the present invention, when a voltage is applied between the cathode 102 and the gate electrode 104, a kind of surplus voltage distribution effect between the pixels by the first resistance layer 114 uniformly formed for each pixel. Occurs. Accordingly, when the emitter 106 is unevenly formed in each pixel, the uniformity of emission of each pixel cell is ensured due to the voltage distribution effect from the pixels having the low electron emission voltage to other pixels having the high electron emission voltage. You can do it. In addition, the second resistor layer 116 is uniformly formed in each of the lines of the cathode 102 supplying voltage to each of the plurality of planar emitters 106 formed in a single pixel, so that each emitter 106 may be formed within one pixel. The voltage distribution effect occurs between them. In other words, when electrons are emitted from an emitter with a low electron emission voltage even in one pixel, the surplus voltage is then distributed to another emitter where electrons are not emitted, and eventually all emitters in one pixel emit electrons uniformly. You can do it. Meanwhile, in the FED according to the second embodiment of the present invention, the resistance values of the first and second resistance layers 114 and 116 are adjusted by the width W and the length L when the resistance layer is formed.

The lower plate forming method of the FED according to the second embodiment of the present invention is as shown in Figs. 9a to 9f. Unlike the case of the first embodiment of the present invention, first, a resistor material is formed on the lower substrate 100 as shown in FIG. 9A. The first resistance layer 114 is formed in a predetermined region where the gate electrode 104 line is to be formed, and the second resistance layer 116 is formed in a predetermined region where the cathode 102 line is to be formed. As the resistor material, amorphous silicon TaO _x N _y , CuO, AlN or the like is used. When forming the first and second resistive layers 114 and 116, the resistance value is controlled by the formation width W and the length L. FIG. Next, the conductive metal layer is entirely deposited in the process of FIG. 9B, and then patterned to form the cathode 102 and the gate electrode 104. When the metal layer is patterned, the gate electrode 104 lines are connected to each other via the first resistive layer 114, and each cathode 102 line is appropriately patterned to be connected via the second resistive layer 116. In addition, the boundary portion between the cathode 102 and the gate electrode 104 is patterned such that a plurality of emitter forming portions are provided as in the first embodiment of the present invention. Al, Cr, Mo, Nb, or the like is used as the material of the cathode 102 and the gate electrode 104, and is formed to a thickness of about 1000 mW. Next, in the process of FIG. 9C, an insulating material 108 is entirely deposited on the lower substrate 100 on which the electrode is formed to a thickness of about 1 μm to form the insulating layer 108. Through-patterning of the insulating layer 108 forms a through hole 110 in a predetermined region on the gate electrode 104, and a plurality of emitters are formed at the boundary between the cathode 102 and the gate electrode 104. The light emitting units 118 are formed. As the insulating material, SiO ₂ , Al ₂ O ₃ , SiNx, or the like is used. In the process of FIG. 9D, the electrode material is patterned on the insulating layer 108 to form the upper electrode 112 to be connected to the gate electrode 104 through the through hole 110. A photoresist mask pattern 120 is then formed in all regions on the bottom plate except for the light emitting portion 118 as shown in FIG. 9E to form the planar emitter 106. Subsequently, the emitter material is entirely deposited on the lower plate on which the photoresist pattern 120 is formed. The deposition thickness of the emitter 106 layer is about 500 kPa or less. Next, the FED according to the second embodiment of the present invention in which the emitter material is formed only on the light emitting portions 118 by exposing the photoresist pattern 120 by a lift-off method as shown in FIG. 9F. You will complete the bottom of. When the photoresist pattern 120 layer is etched and exposed using acetone or the like, only the planar emitter 106 formed on the light emitting unit 118 remains and the rest is removed, thereby completing the lower plate structure as shown in FIG. 9F.

As described above, in the field emission display device and the manufacturing method thereof according to the present invention, a resistor having a uniform resistance value is formed in each of the pixels to apply a voltage to the planar emitter. Even if the emitter is unevenly formed for each pixel by the uniformly formed resistance, the surplus voltage is distributed and uniform electron emission is achieved in each pixel, thereby ensuring uniformity of emission between the pixels. do. In addition, by forming a plurality of planar emitters in one pixel, not only the luminance uniformity between the pixels can be further improved, but also the luminance improvement effect can be obtained. On the other hand, in the case where a plurality of planar emitters are formed in one pixel, the resistors are uniformly formed in the cathode lines connected to each emitter to improve the electron emission uniformity and emission uniformity among the emitters even within one pixel. do.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

A planar emitter formed between the cathode and the gate electrode to emit electrons by a voltage applied between the cathode and the gate electrode, and formed on the cathode and the gate electrode with an insulating layer interposed therebetween and insulated on the gate electrode. A field emission display device comprising pixels having an upper electrode connected to the gate electrode through a hole formed in a layer to apply a scan signal from the outside, In order to ensure the uniformity of electron emission of each pixel, each of the pixels having a resistor formed to be connected in series to any one of the cathode and the gate electrode for applying a voltage to the planar emitter Emission indicator. The method of claim 1, The material of the resistor is any one of amorphous silicon, TaO _x N _y , CuO and AlN having a specific resistance unit of several kilowatts. The method of claim 1, And the resistor is formed between the gate electrode and the upper electrode in the hole. The method of claim 3, wherein The field emission display device of claim 1, wherein the resistance formed in each of the pixels is controlled to have a uniform thickness. The method of claim 1, And the resistor is formed at a portion where a portion of the gate electrode line is disconnected to interconnect the disconnected two gate electrode line portions. The method of claim 5, And the resistances of the resistors formed in the pixels are adjusted in width and length to uniformly adjust resistance values. The method of claim 1, And a plurality of planar emitters formed in each of the pixels. The method of claim 7, wherein And further comprising second resistors connected in series to the cathode lines connected to the planar emitters to ensure electron emission uniformity of the planar emitters formed in a plurality of pixels. device. The method of claim 8, And the second resistor is formed at a portion where a portion of the cathode line is disconnected to interconnect the two disconnected cathode line portions. The method of claim 9, And the second resistors formed on the cathode lines are adjusted such that widths and lengths thereof are adjusted so that resistance values are uniform with each other. Forming a cathode and a gate electrode on the substrate for each pixel, forming a planar emitter for electron emission at a boundary between the cathode and the gate electrode, and an insulating layer on the substrate on which the cathode and the gate electrode are formed. Forming a hole by removing a portion of the insulating layer on the gate electrode, patterning an electrode material on the insulating layer, and applying a scan signal to be connected to the gate electrode through the hole. In the manufacturing method of the field emission display device comprising the step of forming an electrode, And forming a resistor such that each of the pixels is connected in series to one of the cathode and the gate electrode in order to secure electron emission uniformity of the pixels. The method of claim 11, The resistor is a method of manufacturing a field emission display device, characterized in that the resistivity is formed of any one of amorphous silicon, TaO _x N _y , CuO and AlN. The method of claim 11, Connecting the resistor to the gate electrode by forming the resistor in the hole prior to forming the upper electrode; And forming the upper electrode to be connected to the resistor through the hole. The method of claim 13, And forming a thickness of the resistor to adjust the thickness of the resistor to be uniform. The method of claim 11, Prior to forming the cathode and the gate electrode, forming the resistor on a predetermined region where the gate electrode line is to be formed; And discontinuously forming the gate electrode on the resistor so that two portions of the gate electrode disconnected from each other are connected in series through the resistor. The method of claim 15, And forming widths and lengths of the resistors so as to make the resistances of the resistors uniform for each pixel. The method of claim 11, And a plurality of emitters are formed for each of the pixels. The method of claim 17, And forming a second resistor to be connected in series to each of the cathode lines connected to the respective emitters to ensure electron emission uniformity between the emitters formed in the pixel. A method of manufacturing a field emission display device. The method of claim 18, Prior to forming the cathode and the gate electrode, forming the second resistors on a predetermined region where the cathode lines are to be formed; And discontinuously forming the cathode line on the second resistor such that two portions of the cathode line disconnected from each other are connected in series through the second resistor. . The method of claim 19, And forming widths and lengths of the second resistors connected to the cathode lines so that resistance values of the second resistors are uniform.