KR20010053649A - Method for isolating semiconductor devices - Google Patents

Abstract

PURPOSE: An isolation method of a semiconductor memory device is provided to simplify a process by forming an auto-planarized isolation film, by using a deposition rate difference of an oxide between on a nitride film and on a silicon substrate around a trench by filling the trench with the oxide formed an APCVD. CONSTITUTION: A buffer oxide(21) is formed on a silicon substrate(20) by a thermal oxidation method, and a mask layer(22) is formed by depositing a silicon nitride on the buffer oxide by a CVD(Chemical Vapor Deposition) method. And, an etch mask(22) confining an isolation region and an active region is formed by patterning the mask layer and the buffer oxide. Then, a trench is formed by etching a revealed isolation region using a RIE(Reactive Ion Etching) or a plasma etching method. A high temperature thermal oxide is grown on the surface of the silicon substrate revealed by the formation of the trench. And, the surface of the silicon substrate is revealed again by wet-etching the high temperature thermal oxide to cure a defective part of the substrate. An insulation film(240) is deposited on the etch mask enough thick to fill the revealed trench using an APCVD(Atmospheric Pressure Chemical Vapor Deposition) method. Then, the surface of the etch mask is revealed by performing a CMP(chemical mechanical polishing) to planarize the insulation film where an isolation film is to be formed.

Description

Device isolation method for semiconductor devices {Method for isolating semiconductor devices}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device, and in particular, to form a high temperature oxide film on the surface of a trench of a semiconductor substrate for device isolation, and then to remove the high temperature atmospheric pressure chemical vapor deposition (APCVD) using a high concentration of ozone. A method of forming an automatic planarized device isolation film for a semiconductor device to simplify the process by forming an automatic planarized device isolation film by burying the oxide film formed in the semiconductor layer and using a deposition rate difference between the nitride film of the oxide film and the silicon substrate in the trench region. will be.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

A method of device isolation while reducing the length of the buzz bee generated when the device is isolated by a general LOCOS method has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the stress buffer buffer oxide film is reduced, and the polysilicon buffer layer (PBLOCOS) and the sidewall of the buffer oxide film are interposed between the semiconductor substrate and the nitride film. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.

However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

Therefore, a BOX (buried oxide) type shallow trench isolation technology has been developed that can overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed on a semiconductor substrate and has a structure in which silicon oxide or polycrystalline silicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

However, since the trench type device isolation film forming method has no dependence on the deposition region of the insulating layer filling the trench, the step difference between the peripheral region due to the topography of the trench is severe. The first planarization of the uneven portion is carried out by photolithography, and then the second planarization is performed by chemical mechanical polishing for a relatively long time to complete the final device isolation film. Therefore, the process becomes complicated.

1A to 1E are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a buffer oxide film 11 is formed on a silicon substrate 10 that is a semiconductor substrate 10 by a thermal oxidation method, and chemical vapor deposition (hereinafter, referred to as chemical vapor deposition) is performed on the buffer oxide film 11. Silicon nitride is deposited by a CVD method to form a mask layer 12. In this case, the buffer oxide film 11 is formed to reduce thermal stress between the mask layer 12 made of a nitride film and the silicon substrate 10, and the mask layer 12 defines a trench formation region, which is an isolation region. It is formed to prepare an etching mask.

Then, the mask layer 12 and the buffer oxide film 11 are sequentially patterned to expose the trench forming regions of the semiconductor substrate 10 by a photolithography method to form an etching mask 12 that defines the device isolation region and the active region. Form.

Next, an exposed device isolation region of the semiconductor substrate 10 in a portion not protected by the etching mask 12 is etched to a predetermined depth to form a trench. The trench is formed by anisotropic etching using reactive ion etching (hereinafter referred to as RIE) or plasma etching. Thus, the step between the trench lower surface and the unetched silicon substrate surface becomes very large.

Referring to FIG. 1B, a thermal oxide film (not shown) is grown on a surface of the silicon substrate 10 exposed by trench formation at high temperature, and then wet-etched. This is to heal the silicon substrate 10 damaged by the reactive etching. The high temperature thermal oxide film 13 is grown on the inner surface of the trench of the silicon substrate 10 again exposed. At this time, since the profile in the trench lower edge A1 of the high temperature thermal oxide film 13 has a round shape, the leakage current due to the field concentration during device isolation is reduced.

Referring to FIG. 1C, an insulating film 14 is formed on the etch mask 12 to a thickness capable of sufficiently filling the trench in which the high temperature thermal oxide film 13 is formed. At this time, the insulating film 14 is formed by depositing an oxide film by chemical vapor deposition, and the insulating film 14 formed due to the high step due to the trench due to the deposition characteristics of the oxide film on the upper portion of the etching mask 12 and the upper trench formed of the remaining nitride film. Topography becomes largely nonuniform.

Referring to FIG. 1D, in order to first remove the protruding portion of the insulating film before performing chemical mechanical polishing for planarization, the protruding portion is removed by photolithography to leave the remaining insulating layer 140 on the substrate. At this time, the protruding portion of the insulating layer 140 is not completely removed and remains in a pillar shape P having a thin thickness.

Referring to FIG. 1E, the surface of the etching mask 120 is exposed by performing chemical mechanical polishing on the insulating film including the remaining protruding portion. At this time, the chemical mechanical polishing requires a long time for the planarization due to the residual protrusion, and also because a part of the etching mask made of the nitride film is polished and removed, the etching mask having a thickness c1 smaller than the etching mask thickness b1 in FIG. 120 remains.

In addition, the insulating film 141 remaining in the trench occupying a relatively wider area than the surrounding area may be polished by a predetermined thickness d1 than the insulating film remaining in other trenches by the dishing effect, and thus may be lower than the height of the substrate surface. As a result, the planarization with the surface of the etching mask 12 becomes more poor.

Therefore, the device isolation region of the semiconductor device is formed by forming the device isolation film 141 including the remaining insulating film 141.

However, since the device isolation method of the conventional semiconductor device described above has no surface dependence on the deposition site due to the deposition characteristics of the insulating film used as the device isolation film, the unevenness of the upper part after the growth of the insulating film is deepened, and the protrusions of the uneven parts are formed before chemical mechanical polishing. Since the first step is performed by photolithography and then chemical mechanical polishing is performed again for a long time, the process is complicated and the deposition thickness of the etching mask must be thicker than necessary. Since the surface height of the site is different, there is a further disadvantage in flattening.

Accordingly, an object of the present invention is to form a high temperature oxide film on the surface of the trench of the semiconductor substrate for device isolation and then to remove the oxide film and embed the trench into an oxide film formed by high temperature atmospheric pressure chemical vapor deposition (APCVD) using high concentration ozone. The present invention provides a method for forming an automatic planarized device isolation film of a semiconductor device to simplify the process by forming an automatic planarized device isolation film by using a deposition rate difference between a nitride film and a trench portion of a silicon substrate.

In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes a process of forming a trench by removing a predetermined portion of a semiconductor substrate using an etching mask having a predetermined thickness in which a device isolation region and an active region are defined; Forming a thermal oxide film on the surface of the semiconductor substrate forming the inner wall of the trench, and then removing the thermal oxide film, and filling the trench with an insulating material layer having a faster deposition rate than that of the etching mask on the semiconductor substrate. And forming a device isolation film made of an insulating material layer remaining only in the trench by exposing the surface of the etching mask by performing chemical mechanical polishing on the insulating material layer.

1A to 1E are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

2A to 2E are process cross-sectional views showing a device isolation method for a semiconductor device according to the present invention.

In general, when forming shallow trench isolation (STI) as a method of isolation between cells using trenches, silicon oxide is used as a trench filling material. Therefore, the isolation characteristics of the device depend on the physical critical dimension of the trench, and in order to facilitate the device formation process, the upper surface of the isolation layer and the silicon substrate, that is, the active and isolation regions The surface of the substrate having the flat surface without the step must be implemented.

Therefore, in the present invention, a trench type device isolation method is used, but the trench buried material is formed to have a different deposition rate on the surface of the nitride film and on the exposed silicon substrate surface of the trench to use the difference in deposition rate at each of these sites. In other words, the planarization is automatically performed, that is, to prevent the formation of uneven portions having a very large step, which is formed in the prior art, and then, by performing chemical mechanical polishing with a shorter process time than in the prior art, flattening the entire substrate. To achieve.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process cross-sectional views showing a device isolation method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a buffer oxide film 21 is formed on a silicon substrate 20 that is a semiconductor substrate 20 by a thermal oxidation method, and chemical vapor deposition (hereinafter, referred to as chemical vapor deposition) is performed on the buffer oxide film 21. Silicon nitride is deposited by a CVD method to form a mask layer 22. In this case, the buffer oxide film 21 is formed to reduce thermal stress between the mask layer 22 made of a nitride film and the silicon substrate 20, and the mask layer 22 defines a trench formation region, which is an isolation region. It is formed to produce an etching mask and the forming thickness thereof is thinner than the forming thickness in the prior art, so that the polishing time during chemical mechanical polishing is shorter than that in the prior art, thereby ensuring sufficient process margin.

Then, the mask layer 22 and the buffer oxide film 21 are sequentially patterned to expose the trench formation region, which is an isolation region of the semiconductor substrate 20, by a photolithography method, thereby defining an isolation region and an active region. To form (22).

Next, an exposed device isolation region of the semiconductor substrate 20 in a portion not protected by the etching mask 22 is etched to a predetermined depth to form a trench. The trench is formed by anisotropic etching using reactive ion etching (hereinafter referred to as RIE) or plasma etching. Therefore, although the step difference between the trench lower surface and the unetched silicon substrate surface is very large, an embodiment of the present invention uses a method of forming an insulating film so as to sufficiently overcome this step.

Referring to FIG. 2B, the high temperature thermal oxide film 23 is grown at a high temperature on the surface of the silicon substrate 20 exposed by the trench formation. This is to heal the portion of the silicon substrate 20 of the trench damaged by the reactive etching. At this time, since the profile at the lower corner A2 of the high temperature thermal oxide film 23 has a round shape, the leakage current due to the field concentration during device isolation is reduced.

Referring to FIG. 2C, the surface of the silicon substrate 20 forming the inner wall of the trench is exposed again by removing the high temperature thermal oxide film formed by the wet etching to heal the defect site of the substrate. This is because, as described above, the insulating film deposition for forming the device isolation film uses the deposition rate difference between the different deposition surfaces, that is, the silicon portion and the nitride film portion, in the embodiment of the present invention. At this time, the profile of the corner portion A3 of the lower portion of the trench also has a round shape.

Referring to FIG. 2D, an insulating film 24 is formed on the etch mask 22 to a thickness sufficient to fill a trench in which silicon of the silicon substrate 20 is re-exposed. At this time, the insulating film 24 is formed by depositing an oxide film by high temperature atmospheric chemical vapor deposition (APCVD) using a high concentration of ozone. At this time, the deposited insulating film 22 is different from the nitride film forming the etch mask 22 on the silicon surface of the substrate, so that its growth rate is fast in the silicon region and slow on the nitride film. Therefore, there is almost no step in the overall insulating film 24 because of the different deposition rates. As described above, in the embodiment of the present invention where the self-planarization is achieved to some extent, even if the thickness b2 of the nitride film 22 for forming the etch mask 22 is formed thinner than in the conventional art, the process margin in chemical mechanical polishing is reduced. We can secure enough. This is because the amount of the chemical mechanical polishing performed in the embodiment of the present invention is smaller than that of the conventional one, and the thickness of the nitride film lost or removed during polishing is also thin.

Referring to FIG. 2E, the surface of the etching mask 220 is exposed by performing chemical mechanical polishing for planarization on the insulating film to be an isolation layer. At this time, the chemical mechanical polishing requires a shorter time than the conventional planarization because the surface of the insulating film has achieved some self-planarization, and a part of the etching mask made of the nitride film is also polished to have a predetermined thickness (c2). Compared with the formation margin.

In addition, the device isolation film 240, which is an insulating film 240 remaining in a trench that occupies a relatively wider area than the surrounding area, is shorter in the dishing effect since the polishing time is shorter, and thus is the same as the insulating film remaining in other trenches. Only further polishing by the predetermined thickness d2 of the level further improves the overall planarization.

Therefore, the device isolation region 240 is formed by the remaining insulating layer 240 to form the device isolation region of the semiconductor device.

Therefore, the present invention does not require a process of additionally forming a high temperature thermal oxide film, and can achieve self leveling to some extent without a separate photolithography process by the deposition characteristics of the insulating film itself when the trench is buried. Since it is relatively small compared with the related art, the polishing time is shortened, and the dishing effect is improved, so that evenly planarization in the same trench is formed to form a uniform device isolation film, thereby increasing the reliability of the subsequent device formation process.

Claims (5)

Forming a trench by removing a predetermined portion of the semiconductor substrate using an etching mask having a predetermined thickness where the device isolation region and the active region are defined; Forming a thermal oxide film on a surface of the semiconductor substrate forming the inner wall of the trench, and then removing the thermal oxide film; Forming a trench on the etch mask to sufficiently fill the trench with an insulating material layer having a deposition rate higher than that at the etch mask in the semiconductor substrate; And chemically polishing the insulating material layer to expose a surface of the etching mask to form a device isolation film made of the insulating material layer remaining only in the trench. The method of claim 1, wherein the etching mask is formed of a nitride film, and the insulating material layer is formed by vapor deposition using atmospheric pressure chemical vapor deposition using a high concentration of ozone. The method of claim 1, wherein the trench is formed by removing a predetermined portion of the semiconductor substrate by a reactive ion etching method. The method of claim 1, wherein the etching mask is formed thin in consideration of a process time of chemical mechanical polishing. The method of claim 1, wherein the semiconductor substrate is a silicon substrate, and the thermal oxide layer is formed of silicon oxide, and the etching mask is formed by depositing and patterning silicon nitride.