KR19980065504A - Trench element isolation - Google Patents
Trench element isolation Download PDFInfo
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- KR19980065504A KR19980065504A KR1019970000527A KR19970000527A KR19980065504A KR 19980065504 A KR19980065504 A KR 19980065504A KR 1019970000527 A KR1019970000527 A KR 1019970000527A KR 19970000527 A KR19970000527 A KR 19970000527A KR 19980065504 A KR19980065504 A KR 19980065504A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Abstract
트렌지 소자분리방법이 개시되어 있다. 이 방법은 반도체기판 상에 식각저지막을 형성하는 단계와, 상기 식각저지막을 패터닝하여 상기 반도체기판의 소정영역을 노출시키는 식각저지막 패턴을 형성하는 단계와, 상기 노출된 반도체기판을 선택적으로 식각하여 트렌치 영역을 형성하는 단계와, 상기 트렌치 영역 측벽에 산화막 스페이서를 형성하는 단계와, 상기 결과물 전면에 상기 스페이서가 형성된 트렌치 영역을 채우면서 실리콘막 상에 증착되는 속도가 산화막 상에 증착되는 속도보다 빠른 특성을 갖는 절연막을 형성하는 단계와, 상기 식각저지막 패턴이 노출될 때까지 상기 절연막을 전면식각하여 상기 트렌치 영역 내에 소자분리막을 형성하는 단계를 포함하는 것을 특징으로 한다. 이에 따라, 트렌치 영역을 채우는 절연막 내부에 보이드가 형성되는 것을 방지할 수 있다.A method for separating transistor elements is disclosed. The method includes forming an etch stop layer on a semiconductor substrate, patterning the etch stop layer to form an etch stop layer pattern exposing a predetermined region of the semiconductor substrate, and selectively etching the exposed semiconductor substrate. Forming a trench region, forming an oxide spacer on the trench region sidewalls, filling a trench region in which the spacer is formed on the entire surface of the resultant, and a deposition rate on the silicon layer is faster than the deposition rate on the oxide layer; Forming an insulating film having a characteristic and forming an isolation layer in the trench region by etching the entire insulating film until the etch stop layer pattern is exposed. Accordingly, it is possible to prevent the formation of voids in the insulating film filling the trench region.
Description
본 발명은 반도체장치의 소자분리 방법에 관한 것으로, 특히 트렌치 소자분리방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor device, and more particularly to a trench device isolation method.
최근 반도체장치의 집적도가 증가함에 따라 소자분리 영역이 차지하는 면적을 감소시키기 위한 연구가 활발해지고 있다. 지금까지 소자분리 영역을 형성하는 방법으로 반도체기판의 소정영역을 선택적으로 열산화시키어 두꺼운 필드산화막을 형성하는 방법(Local oxidation of silicon; 이하 LOCOS라 한다)이 널리 사용되어 왔다. 그러나, 이러한 LOCOS 방법은 필드산화막의 가장자리에 버즈비크(bird's beak)가 발생하여 서로 이웃한 필드산화막 사이의 활성영역의 폭을 감소시킨다. 따라서, 고집적 반도체장치에 적합한 좁은 활성영역, 예컨대 0.5㎛ 이하의 좁은 활성영역을 형성하는 데에는 적합하지 않은 문제점이 있다. 또한, LOCOS 방법에 의하면 소자분리 영역의 폭에따라 필드산화막의 두께가 다르게 형성된다. 이에 따라, 필드산화막의 두께를 설정하는 데에 어려운 문제점이 있다.Recently, as the degree of integration of semiconductor devices increases, researches for reducing the area occupied by device isolation regions have been actively conducted. As a method of forming a device isolation region, a method of forming a thick field oxide film by selectively thermally oxidizing a predetermined region of a semiconductor substrate (hereinafter referred to as LOCOS) has been widely used. However, this LOCOS method generates a bird's beak at the edge of the field oxide film, thereby reducing the width of the active region between adjacent field oxide films. Therefore, there is a problem that it is not suitable to form a narrow active region suitable for a highly integrated semiconductor device, for example, a narrow active region of 0.5 mu m or less. In addition, according to the LOCOS method, the thickness of the field oxide film is formed differently according to the width of the device isolation region. Accordingly, there is a difficult problem in setting the thickness of the field oxide film.
상기한 LOCOS 방법의 문제점을 해결하기 위하여 최근에 반도체기판의 소정영역을 식각하여 트렌치 영역을 형성하고 상기 트렌치 영역을 절연막으로 채우는 트렌치 소자분리 방법이 제안된 바 있다.In order to solve the problem of the LOCOS method, a trench element isolation method has recently been proposed in which a predetermined region of a semiconductor substrate is etched to form a trench region, and the trench region is filled with an insulating layer.
도 1 및 도 2는 종래의 트렌치 소자분리 방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a conventional trench device isolation method.
도 1은 반도체기판의 소정영역을 식각하여 트렌치 영역을 형성하고 상기 트렌치 영역이 형성된 결과물 전면에 절연막(5)을 형성하는 단계를 설명하기 위한 단면도이다. 먼저, 반도체기판(1) 상에 식각 저지막, 예컨대 실리콘질화막을 형성한다. 이어서, 상기 식각 저지막을 패터닝하여 상기 반도체기판(1)의 소정영역을 노출시키는 식각 저지막 패턴(3)을 형성한다. 다음에, 상기 식각 저지막 패턴(3)을 식각 마스크로하여 상기 노출된 반도체기판(1)을 소정의 깊이로 식각함으로써, 트렌치 영역을 형성한다. 계속해서, 상기 트렌치 영역이 형성된 결과물 전면에 트렌치 영역을 채우는 절연막(5)을 형성한다. 여기서, 상기 절연막(5)은 사일레인(SiH4) 가스 및 산소 가스를 반응가스로 사용하는 CVD 산화막으로 형성한다. 이때, 도시된 바와 같이 트렌치 영역 내에 채워지는 절연막(5)의 내부에 보이드(V)가 형성된다.FIG. 1 is a cross-sectional view for explaining a step of forming a trench region by etching a predetermined region of a semiconductor substrate and forming an insulating film 5 on the entire surface of the resultant product in which the trench region is formed. First, an etch stop layer such as a silicon nitride layer is formed on the semiconductor substrate 1. Subsequently, the etch stop layer is patterned to form an etch stop layer pattern 3 exposing a predetermined region of the semiconductor substrate 1. Next, the exposed semiconductor substrate 1 is etched to a predetermined depth using the etch stop layer pattern 3 as an etch mask to form a trench region. Subsequently, an insulating film 5 filling the trench region is formed on the entire surface of the resultant product in which the trench region is formed. Here, the insulating film 5 is formed of a CVD oxide film using a silane (SiH 4 ) gas and an oxygen gas as a reaction gas. At this time, the void V is formed in the insulating film 5 filled in the trench region as shown.
도 2는 소자분리막(5a), 게이트 산화막(7), 및 게이트 전극(9)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 상기 식각 저지막 패턴(3)이 노출될 때까지 상기 절연막(5)을 전면식각하거나 화학기계적연마(CMP) 방법으로 연마하여 트렌치 영역 내에 소자분리막(5a)을 형성한다. 이때, 상기 보이드(V)가 노출되면서 소자분리막(5a)의 표면에 홈이 형성된다. 이어서, 상기 노출된 식각 저지막 패턴(5a)을 제거하고, 그 결과물을 열산화시키어 상기 소자분리막(5a) 사이의 반도체기판(1) 표면에 게이트 산화막(7)을 형성한다. 다음에, 상기 게이트 산화막(5a)이 형성된 결과물 전면에 도전막, 예컨대 도우핑된 폴리실리콘막을 형성하고, 이를 패터닝하여 상기 게이트 산화막(7)의 소정영역 및 소자분리막의 소정영역을 덮는 게이트 전극(9)을 형성한다. 이때, 상기 도전막이 식각되어 소자분리막이 노출되는 부분(도시하지 않음)의 홈 내에 스트링거(stringer)로 작용하는 도전막이 잔존한다. 이와 같이 소자분리막(5a)의 홈 내에 잔존하는 스트링거는 서로 이웃한 게이트 전극을 전기적으로 연결시켜주는 역할을 하여 반도체장치의 오동작을 유발시킨다. 이러한 스트링거를 제거하기 위해서는 게이트 전극(9)을 형성하기 위한 패터닝 공정시 도전막을 과도하게 식각하여야 한다. 그러나, 이와 같이 도전막을 과도하게 식각하게 되면, 게이트 산화막(3) 또한 과도하게 식각되어 그 아래의 반도체기판(1)에 식각 손상이 가해진다. 이와 아울러서, 게이트 전극의 선 폭 또한 비정상적으로 감소하여 트랜지스터의 특성을 저하시킨다.FIG. 2 is a cross-sectional view for explaining a step of forming the device isolation film 5a, the gate oxide film 7, and the gate electrode 9. FIG. In detail, the device isolation layer 5a is formed in the trench region by the entire surface etching or the chemical mechanical polishing (CMP) method until the etch stop layer pattern 3 is exposed. At this time, a groove is formed on the surface of the device isolation layer 5a while the void V is exposed. Subsequently, the exposed etch stop layer pattern 5a is removed, and the resultant is thermally oxidized to form a gate oxide layer 7 on the surface of the semiconductor substrate 1 between the device isolation layers 5a. Next, a conductive film, such as a doped polysilicon film, is formed on the entire surface of the resultant product on which the gate oxide film 5a is formed, and patterned to cover a predetermined region of the gate oxide film 7 and a predetermined region of the device isolation film. 9) form. At this time, the conductive film is etched so that a conductive film serving as a stringer remains in a groove (not shown) where the device isolation film is exposed. As such, the stringers remaining in the grooves of the device isolation layer 5a electrically connect adjacent gate electrodes to each other, causing malfunction of the semiconductor device. In order to remove the stringer, the conductive layer needs to be excessively etched during the patterning process for forming the gate electrode 9. However, when the conductive film is excessively etched in this manner, the gate oxide film 3 is also excessively etched, and etching damage is applied to the semiconductor substrate 1 beneath it. In addition, the line width of the gate electrode is also abnormally reduced to deteriorate the transistor characteristics.
상술한 바와 같이 종래의 트렌치 소자분리방법에 의하면, 트렌치 영역 내에 매립되는 절연막 내부에 보이드가 형성되어 트렌치 영역을 채우는 소자분리막 형성시 그 표면에 홈이 형성되고 이 홈 내에 게이트 전극을 형성하기 위한 도전막이 잔존하여 트랜지스터의 오동작을 유발시킨다. 이러한 문제점을 해결하기 위하여 게이트 전극을 패터닝하기 위한 식각공정시 도전막을 과도식각하게 되면, 반도체기판에 식각손상이 가해짐과 아울러 게이트 전극의 선폭이 감소되어 트랜지스터의 특성을 저하시키는 또 다른 문제점을 야기시킨다.As described above, according to the conventional trench device isolation method, a void is formed in the insulating film embedded in the trench region to form a groove in the surface of the device isolation film to fill the trench region, and a conductivity for forming a gate electrode in the groove is formed. The film remains, causing the transistor to malfunction. To solve this problem, if the conductive film is excessively etched during the etching process for patterning the gate electrode, etching damage is applied to the semiconductor substrate and the line width of the gate electrode is reduced, thereby causing another problem of degrading the characteristics of the transistor. Let's do it.
따라서, 본 발명이 이루고자 하는 기술적 과제는 트렌치 영역을 채우는 절연막 내부에 보이드가 형성되는 것을 방지할 수 있는 트렌치 소자분리방법을 제공하는 데 있다.Accordingly, an aspect of the present invention is to provide a trench isolation method capable of preventing voids from being formed in an insulating layer filling a trench region.
도 1 및 도 2는 종래의 트렌치 소자분리방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a conventional trench isolation method.
도 3 내지 도 5는 본 발명의 트랜치 소자분리방법을 설명하기 위한 단면도들이다.3 to 5 are cross-sectional views for explaining a trench device isolation method of the present invention.
상기 기술적 과제를 이루기 위하여 본 발명에 따른 트렌치 소자분리방법은 반도체기판 상에 식각저지막을 형성하는 단계와, 상기 식각저지막을 패터닝하여 상기 반도체기판의 소정영역을 노출시키는 식각저지막 패턴을 형성하는 단계와, 상기 노출된 반도체기판을 선택적으로 식각하여 트렌치 영역을 형성하는 단계와, 상기 트렌치 영역 측벽에 산화막 스페이서를 형성하는 단계와, 상기 결과물 전면에 상기 스페이서가 형성된 트렌치 영역을 채우면서 실리콘막 상에 증착되는 속도가 산화막 상에 증착되는 속도보다 빠른 특성을 갖는 절연막을 형성하는 단계와, 상기 식각저지막 패턴이 노출될 때까지 상기 절연막을 전면식각하여 상기 트렌치 영역 내에 소자분리막을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, a trench isolation method includes forming an etch stop layer on a semiconductor substrate, and patterning the etch stop layer to form an etch stop layer pattern that exposes a predetermined region of the semiconductor substrate. And selectively etching the exposed semiconductor substrate to form a trench region, forming an oxide spacer on sidewalls of the trench region, and filling a trench region in which the spacer is formed on the entire surface of the resultant. Forming an insulating film having a characteristic that a deposition rate is faster than a deposition rate on an oxide layer, and forming an isolation layer in the trench region by etching the entire surface of the insulating layer until the etch stop layer pattern is exposed; Characterized in that.
본 발명에 의하면, 트렌치 영역을 채우는 절연막 내부에 보이드가 형성되지 않으므로 소자분리막 표면에 홈이 형성되는 것을 방지할 수 있다.According to the present invention, since voids are not formed in the insulating film filling the trench region, it is possible to prevent the formation of grooves on the surface of the device isolation film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 반도체기판(11)의 소정영역에 트렌치 영역을 형성하고, 상기 트렌치 영역 측벽에 산화막으로 이루어진 스페이서(15)를 형성하는 단계를 설명하기 위한 단면도이다. 먼저, 반도체기판(11), 예컨대 실리콘기판 상에 식각저지막을 형성하고, 식각저지막을 통상의 사진/식각공정으로 패터닝하여 반도체기판(11)의 소정영역을 노출시키는 식각저지막 패턴(13)을 형성한다. 여기서, 상기 식각저지막은 실리콘기판에 대한 식각 선택비가 우수한 실리콘질화막으로 형성하는 것이 바람직하다. 이어서, 상기 식각저지막 패턴(13)을 식각마스크로 사용하여 상기 노출된 반도체기판(11)을 선택적으로 식각함으로써, 반도체기판(11)의 소정영역에 소정의 깊이를 갖는 트렌치 영역을 형성한다. 이때, 상기 노출된 반도체기판(11)을 선택적으로 식각하는 공정에 있어서, 상기 식각저지막 패턴(13)을 형성하기 위한 사진공정에 의하여 형성되는 포토레지스트 패턴(도시하지 않음)을 식각 마스크로 사용할 수도 있다. 다음에, 상기 트렌치 영역이 형성된 결과물 전면에 CVD 실리콘산화막을 형성하고, 이를 이방성 식각하여 트렌치 영역 측벽에 스페이서(15)를 형성한다.3 is a cross-sectional view for explaining a step of forming a trench region in a predetermined region of the semiconductor substrate 11 and forming a spacer 15 made of an oxide film on the sidewalls of the trench region. First, an etch stop layer pattern 13 is formed on the semiconductor substrate 11, for example, a silicon substrate, and the etch stop layer is patterned by a general photo / etch process to expose a predetermined region of the semiconductor substrate 11. Form. The etch stop layer may be formed of a silicon nitride film having an excellent etching selectivity with respect to the silicon substrate. Subsequently, the exposed semiconductor substrate 11 is selectively etched using the etch stop layer pattern 13 as an etching mask to form a trench region having a predetermined depth in a predetermined region of the semiconductor substrate 11. In this case, in the process of selectively etching the exposed semiconductor substrate 11, a photoresist pattern (not shown) formed by a photo process for forming the etch stop layer pattern 13 is used as an etching mask. It may be. Next, a CVD silicon oxide film is formed on the entire surface of the resultant trench region, and then anisotropically etched to form a spacer 15 on the sidewalls of the trench region.
도 4는 소자분리막을 형성하기 위한 절연막(17)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로, 상기 스페이서(15)가 형성된 결과물 전면에 실리콘막 상에 증착되는 속도가 실리콘산화막 상에 증착되는 속도에 비하여 빠른 특성을 갖는 절연막(17)을 형성한다. 이때, 상기 절연막(17)의 두께는 트렌치 영역이 충분히 채워질 수 있도록 두껍게 형성하여야 한다. 그리고, 상기 절연막(17)은 CVD 방법에 의한 언도우프트 TEOS(tetraethyl orthosilicate) 산화막으로 형성하는 것이 바람직하다. 이는, 언도우프트 TEOS 산화막이 실리콘막 상에 증착되는 속도가 실리콘산화막 상에 증착되는 속도에 비하여 약 두배정도 빠른 특성을 갖기 때문이다. 다시 말해서, 언도우프트 TEOS 산화막은 트렌치 영역의 바닥, 즉 실리콘기판 위에 증착되는 속도가 트렌치 영역의 측벽에 실리콘산화막으로 형성된 스페이서(15) 상에 증착되는 속도보다 2배 정도 빠르기 때문이다. 이와 같이 상기 절연막(17)으로 언도우프트 TEOS 산화막을 형성하면, 도시된 바와 같이 트렌치 영역 내부를 완전히 채우는 절연막(17)을 얻을 수 있다.4 is a cross-sectional view for explaining a step of forming the insulating film 17 for forming the device isolation film. Specifically, an insulating film 17 having a faster characteristic than the speed of being deposited on the silicon oxide film is formed on the entire surface of the resultant formed spacer 15 is formed. In this case, the thickness of the insulating layer 17 should be thick so that the trench region may be sufficiently filled. The insulating film 17 is preferably formed of an undoped tetraethyl orthosilicate (TEOS) oxide film by CVD. This is because the rate at which the undoped TEOS oxide film is deposited on the silicon film is about twice faster than the rate at which the undoped TEOS oxide film is deposited on the silicon oxide film. In other words, the undoped TEOS oxide film is about twice as fast as the deposition rate on the bottom of the trench region, that is, on the silicon substrate, than the deposition rate on the spacer 15 formed of the silicon oxide film on the sidewall of the trench region. By forming the undoped TEOS oxide film using the insulating film 17 as described above, an insulating film 17 that completely fills the inside of the trench region can be obtained as shown.
도 5는 소자분리막(17a), 게이트 산화막(19), 및 게이트 전극(21)을 형성하는 단계를 설명하기 위한 단면도이다. 상세히 설명하면, 상기 식각저지막 패턴(13)이 노출될 때까지 절연막(17)을 전면식각하여 트렌치 영역을 채우는 소자분리막(17a)을 형성한다. 여기서, 상기 절연막(17)을 전면식각하는 방법은 에치백 공정 또는 화학기계적 연마(CMP; chemical mechanical polishing) 공정으로 실시하는 것이 바람직하다. 이와 같이 소자분리막(17a)을 형성하면, 소자분리막(17a)의 내부 또는 그 표면에 보이드나 홈이 형성되는 것을 방지할 수 있다. 이어서, 상기 노출된 식각저지막 패턴(13)을 건식 식각 또는 습식 식각공정으로 제거하여 그 아래의 반도체기판(11), 즉 활성영역을 노출시킨다. 여기서, 상기 식각저지막 패턴(13)을 습식 식각공정으로 제거하는 경우에는 인산용액이 널리 사용된다. 다음에, 상기 결과물을 열산화시키어 상기 노출된 활성영역 표면에 게이트 산화막(19)을 형성하고, 그 결과물 전면에 도전막, 예컨대 도우핑된 폴리실리콘막을 형성한다. 계속해서, 상기 도전막을 패터닝하여 게이트 산화막(19)의 소정영역 및 소자분리막(17a)의 소정영역을 덮는 게이트 전극(21)을 형성한다.5 is a cross-sectional view for describing a step of forming the device isolation film 17a, the gate oxide film 19, and the gate electrode 21. In detail, the isolation layer 17a filling the trench region may be formed by etching the entire surface of the insulating layer 17 until the etch stop layer pattern 13 is exposed. Here, the method of etching the entire surface of the insulating film 17 is preferably performed by an etch back process or a chemical mechanical polishing (CMP) process. By forming the device isolation film 17a in this manner, it is possible to prevent the formation of voids or grooves in or on the surface of the device isolation film 17a. Subsequently, the exposed etch stop layer pattern 13 is removed by a dry etching process or a wet etching process to expose the semiconductor substrate 11, that is, the active region below it. In the case where the etch stop layer pattern 13 is removed by a wet etching process, a phosphoric acid solution is widely used. Next, the resultant is thermally oxidized to form a gate oxide film 19 on the exposed active region surface, and a conductive film such as a doped polysilicon film is formed on the entire surface of the resultant. Subsequently, the conductive film is patterned to form a gate electrode 21 covering a predetermined region of the gate oxide film 19 and a predetermined region of the device isolation film 17a.
본 발명은 상기 실시예에 한정되지 않고 당업자의 수준에서 그 변형 및 개량이 가능하다.The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.
상술한 바와 같이 본 발명의 실시예에 의하면, 소자분리막의 표면에 홈이 형성되는 것을 방지할 수 있으므로, 서로 이웃한 게이트 전극 사이에 도전막으로 이루어진 스트링거가 형성되지 않는다. 이에 따라, 게이트 전극을 구비하는 트랜지스터가 오동작하는 문제점을 제거할 수 있으므로, 반도체장치의 신뢰성 및 수율을 개선시킬 수 있다.As described above, according to the exemplary embodiment of the present invention, since the grooves can be prevented from being formed on the surface of the device isolation film, the stringer made of the conductive film is not formed between the adjacent gate electrodes. As a result, the malfunction of the transistor including the gate electrode can be eliminated, so that the reliability and yield of the semiconductor device can be improved.
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| KR20010053649A (en) * | 1999-12-01 | 2001-07-02 | 박종섭 | Method for isolating semiconductor devices |
| KR100541801B1 (en) * | 1998-12-23 | 2006-04-12 | 삼성전자주식회사 | Semiconductor device and manufacturing method |
| KR100773754B1 (en) * | 2006-09-19 | 2007-11-09 | 주식회사 아이피에스 | Method of depositing dielectric layer with increased gap-fill ability |
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| KR100541801B1 (en) * | 1998-12-23 | 2006-04-12 | 삼성전자주식회사 | Semiconductor device and manufacturing method |
| KR20010053649A (en) * | 1999-12-01 | 2001-07-02 | 박종섭 | Method for isolating semiconductor devices |
| KR100773754B1 (en) * | 2006-09-19 | 2007-11-09 | 주식회사 아이피에스 | Method of depositing dielectric layer with increased gap-fill ability |
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