KR20010046915A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR20010046915A KR20010046915A KR1019990050885A KR19990050885A KR20010046915A KR 20010046915 A KR20010046915 A KR 20010046915A KR 1019990050885 A KR1019990050885 A KR 1019990050885A KR 19990050885 A KR19990050885 A KR 19990050885A KR 20010046915 A KR20010046915 A KR 20010046915A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 description 13
- 238000001259 photo etching Methods 0.000 description 11
- 238000005259 measurement Methods 0.000 description 10
- 238000005498 polishing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000002002 slurry Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 포토/습식각 스텝을 스킵하여 단순화된 공정으로 스테퍼 얼라인 및 계측 안정성을 확보할 수 있도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device in which stepper alignment and measurement stability can be secured in a simplified process by skipping photo / wet etching steps.
도 1은 종래 기술의 반도체 소자의 구조 단면도이다.1 is a structural cross-sectional view of a semiconductor device of the prior art.
종래 기술의 반도체 소자의 제조 방법에서는 CMP(Chemical Mechnical Polishing)에 의한 PGI(Profiled Groove Isolation) 공정시에 PGI CMP ~ FG(First Gate) 포토 공정사이에 스테퍼 얼라인먼트(Stepper alignment) 안정성 및 오버레이(Overlay) 계측의 안정성을 확보하기 위하여 각 스테퍼 얼라인 키를 별도의 마스크를 사용하여 오프시키고 습식각을 통해 식각하는 방법을 사용하였다.In the manufacturing method of the semiconductor device of the prior art, stepper alignment stability and overlay between PGI CMP to FG (First Gate) photo process during PGI (Profiled Groove Isolation) process by CMP (Chemical Mechnical Polishing) In order to secure measurement stability, each stepper alignment key was turned off using a separate mask and etched through wet etching.
도 1은 습식각에 의한 얼라인 키 패턴의 확보 단면을 나타낸 것으로 이를 개략적으로 설명하면 다음과 같다.1 is a cross-sectional view illustrating a secured key pattern obtained by wet etching.
반도체 기판(1), 반도체 기판(1)의 그루브내에 매립되어 소자격리층으로 사용되는 HDP 산화막(2), 상기 반도체 기판(1)의 특정 부분(wide field)에 형성되는 얼라인 키 패턴(3)으로 구성된다.The semiconductor substrate 1, the HDP oxide film 2 embedded in the groove of the semiconductor substrate 1 and used as a device isolation layer, and the alignment key pattern 3 formed in a wide field of the semiconductor substrate 1. It is composed of
상기 HDP(High Density Plasma) 산화막(2)은 반도체 기판(1)의 소자 격리 영역에 그루브를 형성하고 전면에 고밀도 플라즈마 공정으로 산화막을 형성한후에 CMP 공정으로 평탄화하여 형성한다.The HDP (High Density Plasma) oxide film 2 is formed by forming a groove in the device isolation region of the semiconductor substrate 1 and forming an oxide film on the entire surface by a high-density plasma process and then planarizing it by a CMP process.
이와 같은 CMP 공정으로 얼라인 키 패턴(3)이 완전 평탄화되면 얼라인 키의 요철 상태 및 콘트래스트(contrast)가 감소하여 이후의 FG 포토 스텝에서 마스크 얼라인 및 오버레이 계측을 할 수 없다.When the alignment key pattern 3 is completely flattened by such a CMP process, the uneven state and contrast of the alignment key are reduced, so that mask alignment and overlay measurement cannot be performed in a subsequent FG photo step.
FG 포토 스텝에서 마스크 얼라인 및 오버레이 계측 가능성을 높이기 위해서는 별도의 포토/습식각을 통해 얼라인 키 패턴(3)의 요철을 확보한다.In order to increase the possibility of mask alignment and overlay measurement in the FG photo step, irregularities of the alignment key pattern 3 are secured through separate photo / wet etching.
그러나 이와 같은 종래 기술의 반도체 소자의 제조 방법은 다음과 같은 문제가 있다.However, such a conventional method of manufacturing a semiconductor device has the following problems.
PGI CMP 공정후에 얼라인 키 패턴의 요철을 확보하기 위하여 반드시 별도의 포토/습식각 공정을 수행하여야 하므로 포토 마스크수가 증가하게 되어 반도체 제조 원가 상승의 원인이된다.After the PGI CMP process, a separate photo / wet etching process must be performed in order to secure the unevenness of the alignment key pattern, thereby increasing the number of photo masks, which causes a rise in semiconductor manufacturing cost.
또한, 얼라인 키 패턴의 요철 확보를 위한 포토/습식각/PR 제거/세정 등의 추가되는 공정 스텝의 증가로 TAT 측면에서 불리하다.In addition, an increase in additional process steps such as photo / wet etching / PR removal / cleaning for securing irregularities of the alignment key pattern is disadvantageous in terms of TAT.
이와 같은 공정 스텝 추가는 웨이퍼의 오염을 초래할 수도 있다.Such process step addition may lead to contamination of the wafer.
본 발명은 이와 같은 종래 기술의 반도체 소자의 제조 방법의 문제를 해결하기 위하여 안출한 것으로, 포토/습식각 스텝을 스킵하여 단순화된 공정으로 스테퍼 얼라인 및 계측 안정성을 확보할 수 있도록한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art semiconductor device manufacturing method, the semiconductor device of the step to ensure the stepper alignment and measurement stability in a simplified process by skipping the photo / wet etching step It is an object to provide a manufacturing method.
도 1은 종래 기술의 반도체 소자의 구조 단면도1 is a structural cross-sectional view of a semiconductor device of the prior art
도 2는 본 발명에 따른 반도체 소자의 구조 단면도2 is a structural cross-sectional view of a semiconductor device according to the present invention.
도 3a내지 도 3f는 본 발명에 따른 포토/습식각 스킵후의 스테퍼 얼라인 및 오버레이 계측 안정성 비교 그래프3A to 3F are graphs comparing stepper alignment and overlay measurement stability after photo / wet etching skipping according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21. 반도체 기판 22. HDP 산화막21. Semiconductor substrate 22. HDP oxide film
23. 얼라인 키 패턴23. Align Key Pattern
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판의 소자 격리 영역에 트렌치 및 얼라인 키 패턴을 형성하는 단계;상기 트렌치 및 얼라인 키 패턴을 포함하는 전면에 트렌치가 매립되도록 산화막을 형성하는 단계;상기 산화막을 CMP의 타겟을 낮추고 공정 시간을 10 ~ 20sec 증가시켜 얼라인 키 패턴이 형성된 부분(wide field)에서 산화막의 디싱(Dishing) 현상이 유발되도록하여 얼라인 키의 요철 확보하는 것과 동시에 소자 격리층을 형성하는 단계;상기 얼라인 키 패턴을 이용하여 게이트 라인을 패터닝하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a trench and an alignment key pattern in an isolation region of a semiconductor substrate; a trench is embedded in a front surface of the trench and the alignment key pattern; Forming an oxide film so as to lower the target of the CMP and increase the process time by 10 to 20 sec to cause dishing of the oxide film in a wide field where an alignment key pattern is formed. Forming an isolation layer at the same time to secure the unevenness; and patterning the gate line using the alignment key pattern.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 제조 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 소자의 구조 단면도이고, 도 3a내지 도 3f는 본 발명에 따른 AA 포토/습식각 스킵후의 스테퍼 얼라인 및 오버레이 계측 안정성 비교 그래프이다.2 is a cross-sectional view of a semiconductor device according to the present invention, and FIGS. 3A to 3F are graphs comparing stepper alignment and overlay measurement stability after AA photo / wet etching skip according to the present invention.
본 발명은 얼라인 키 패턴의 요철을 확보하기 위한 포토/습식각 공정을 스킵하고도 스테퍼 얼라인 및 오버레이 계측의 안정성을 확보할 수 있도록한 것이다.The present invention is to ensure the stability of the stepper alignment and overlay measurement even if the photo / wet etching process to secure the irregularities of the alignment key pattern.
그 구성은 반도체 기판(21), 반도체 기판(21)의 그루브내에 매립되어 소자격리층으로 사용되는 HDP 산화막(22), 상기 반도체 기판(21)의 특정 부분(wide field)에 형성되는 얼라인 키 패턴(23)으로 구성된다.Its configuration is an alignment key formed in the semiconductor substrate 21, the HDP oxide film 22 embedded in the groove of the semiconductor substrate 21 and used as a device isolation layer, and in a specific field of the semiconductor substrate 21. It consists of a pattern 23.
여기서, 얼라인 키 패턴(23)의 요철이 오버 폴리싱에 의해 충분히 확보되는 것을 단면에서 알 수 있다.Here, it can be seen from the cross section that the unevenness of the alignment key pattern 23 is sufficiently secured by over polishing.
공정 진행은 다음과 같은 순서로 진행한다.The process proceeds in the following order.
먼저, 반도체 기판(21)의 소자 격리 영역에 2000 ~ 4000Å의 깊이와 0.1 ~ 0.3㎛의 스페이스를 갖는 트렌치를 형성하고 HDP로 갭 필(Gap-Fill)공정을 진행하여 상기 트렌치를 매립하는 HDP 산화막(22)을 4000 ~ 7000Å 두께로 형성한다.First, a trench having a depth of 2000 to 4000 microns and a space of 0.1 to 0.3 µm is formed in the device isolation region of the semiconductor substrate 21, and a gap fill process is performed using HDP to fill the trench. (22) is formed to a thickness of 4000 ~ 7000Å.
그리고 상기 HDP 산화막(22)을 CMP 공정으로 평탄화하여 소자격리층을 형성한다.The HDP oxide film 22 is planarized by a CMP process to form an isolation layer.
이때, CMP 공정의 타겟을 낮추고 공정 시간을 10 ~ 20sec 증가시켜 50 ~ 150Å정도 오버 폴리싱한다.At this time, the target of the CMP process is lowered and the process time is increased by 10 to 20 sec to overpolish about 50 to 150 ms.
상기 CMP 공정의 구체적인 공정 조건은 다음과 같다.Specific process conditions of the CMP process are as follows.
플래튼 스피드(platen speed)를 70 ~ 100rpm로 하고, 헤드 스피드(head speed)를 60 ~ 90rpm으로 한다.The platen speed is 70 to 100 rpm and the head speed is 60 to 90 rpm.
폴리싱 압력은 3.0 ~ 5.0psi, 슬러리 플로우 레이트(Slurry flow rate)를 100 ~ 200ml/min, 리모벌 레이트(Removal rate)를 2000 ~ 2800Å/min으로 한다.Polishing pressure is 3.0 ~ 5.0psi, slurry flow rate (Slurry flow rate) 100 ~ 200ml / min, Removal rate (2000) 2800Pa / min.
이와 같은 공정 조건으로 CMP 공정을 진행하여 10 ~ 20%의 오버 폴리싱을 하는 경우 얼라인 키 패턴(23)이 형성된 부분(wide field)에서 산화막의 디싱(Dishing) 현상이 유발되어 얼라인 키의 요철이 확보된다.In the case of performing the CMP process under such a process condition and performing 10 to 20% over polishing, dishing of the oxide film occurs in the wide field where the alignment key pattern 23 is formed, thereby causing irregularities in the alignment key. This is secured.
이와 같은 본 발명에 따른 반도체 소자의 제조 공정은 얼라인 키 패턴의 요철 확보를 위하여 별도의 포토/습식각 공정을 하지 않고 PGI CMP공정시에 오버 폴리싱으로 얼라인 패턴의 요철 및 얼라인 패턴의 콘트래스트를 확보한다.The manufacturing process of the semiconductor device according to the present invention is the concave and convex pattern of the alignment pattern by over-polishing in the PGI CMP process without performing a separate photo / wet etching process to secure the irregularity of the alignment key pattern Secure the trace.
도 3a는 기존의 포토/습식각을 적용한후의 스테퍼 얼라인시의 X 방향의 오정렬도(misregistration)를 나타낸 것이고, 도 3b는 Y 방향의 오정렬도를 나타낸 것이다.FIG. 3A illustrates misregistration in the X direction during stepper alignment after applying a conventional photo / wet angle, and FIG. 3B illustrates misalignment in the Y direction.
그리고 도 3c는 포토/습식각을 적용한후의 오버레이 계측 결과를 나낸 것이다.3C shows the overlay measurement result after applying photo / wet angle.
그리고 도 3d는 본 발명에 따라 포토/습식각을 스킵하고 오버 폴리싱후의 스테퍼 얼라인시의 X 방향의 오정렬도(misregistration)를 나타낸 것이고, 도 3e는 Y 방향의 오정렬도를 나타낸 것이다.3D illustrates misregistration in the X direction during stepper alignment after skipping photo / wet angle according to the present invention, and FIG. 3E illustrates misalignment in the Y direction.
그리고 도 3f는 포토/습식각을 적용한후의 오버레이 계측 결과를 나낸 것이다.3F shows the result of overlay measurement after applying photo / wet angle.
상기 도 3a내지 도 3f의 그래프를 비교하면 포토/습식각 공정을 스킵한 본 발명에 따른 오버 폴리싱에 의한 방법 역시 스테퍼 얼라인 안정성 및 오버레이 계측 안정성이 충분히 확보되는 것을 알 수 있다.Comparing the graphs of FIGS. 3A to 3F, it can be seen that the method by overpolishing according to the present invention, which skips the photo / wet etching process, also sufficiently secures stepper alignment stability and overlay metrology stability.
상대적으로 넓은 필드(wide field) 지역인 얼라인 키 패턴부의 산화 디싱 효과를 이용하므로 실제 양산에 적용하는 경우 셀부에서의 산화 디싱 문제 및 전기적 특성의 열화 문제는 없다.Since the oxidizing dishing effect of the alignment key pattern portion, which is a relatively wide field area, is used, there is no problem of oxidizing dishing and degradation of electrical characteristics in the cell portion when applied to actual mass production.
이와 같은 본 발명에 따른 반도체 소자의 제조 방법은 다음과 같은 효과가 있다.Such a method of manufacturing a semiconductor device according to the present invention has the following effects.
첫째, FG 포토 공정을 진행하기 전에 스테퍼 얼라인의 안정성 및 오버레이 안정성의 확보를 위하여 별도의 마스크 공정을 진행하지 않으므로 제조 원가의 감소 효과가 있다.First, since the separate mask process is not performed to secure the stability of the stepper alignment and the overlay stability before the FG photo process, the manufacturing cost is reduced.
둘째, 포토/습식각 공정을 스킵할 수 있으므로 양산 TAT를 단축하는 효과가 있다.Second, since the photo / wet etching process can be skipped, there is an effect of shortening the mass production TAT.
셋째, 공정 스텝수의 감소에 따라 웨이퍼 오염 감소 효과가 있다.Third, wafer contamination is reduced by reducing the number of process steps.
넷째, CMP 공정시에 RPM, 압력, 슬러리 유입율등의 조건을 동일하게 하고 공정 시간 및 타겟 위치만을 달리하여 얼라인 요철을 확보하므로 공정 리스크가 적다.Fourth, in the CMP process, the conditions such as RPM, pressure, slurry inflow rate are the same, and the alignment irregularities are secured only by changing the process time and the target position, thereby reducing the process risk.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101593744B (en) * | 2008-05-29 | 2011-07-06 | 中芯国际集成电路制造(北京)有限公司 | Alignment mark and manufacture method thereof |
| CN109346419A (en) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
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| KR0165353B1 (en) * | 1995-12-14 | 1999-02-01 | 김광호 | Forming alignment key pattern in semiconductor apparatus |
| KR100248155B1 (en) * | 1997-12-08 | 2000-03-15 | 김영환 | Method for forming align key of field region |
| KR20010003670A (en) * | 1999-06-24 | 2001-01-15 | 김영환 | Method for forming alignment key of semiconductor device |
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| CN101593744B (en) * | 2008-05-29 | 2011-07-06 | 中芯国际集成电路制造(北京)有限公司 | Alignment mark and manufacture method thereof |
| CN109346419A (en) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
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