KR20010004309A - Method of fabricating alignment key of wafer - Google Patents

Method of fabricating alignment key of wafer Download PDF

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Publication number
KR20010004309A
KR20010004309A KR1019990024933A KR19990024933A KR20010004309A KR 20010004309 A KR20010004309 A KR 20010004309A KR 1019990024933 A KR1019990024933 A KR 1019990024933A KR 19990024933 A KR19990024933 A KR 19990024933A KR 20010004309 A KR20010004309 A KR 20010004309A
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KR
South Korea
Prior art keywords
alignment key
polysilicon
wafer alignment
interlayer dielectric
wafer
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KR1019990024933A
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Korean (ko)
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정우영
문승찬
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김영환
현대전자산업 주식회사
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Priority to KR1019990024933A priority Critical patent/KR20010004309A/en
Publication of KR20010004309A publication Critical patent/KR20010004309A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

PURPOSE: A method for manufacturing a wafer alignment key is provided to prevent a depth of a wafer alignment key from becoming uneven because of polysilicon residue, by leaving an interlayer dielectric on the wafer alignment key in a landing plug contact mask, thereby completely removing the polysilicon residue in a chemical mechanical polishing(CMP) process of landing plug polysilicon. CONSTITUTION: A wafer alignment key(11) is formed in a predetermined region of a semiconductor substrate. The first polysilicon layer is deposited on the semiconductor substrate and patterned into a predetermined pattern while leaving the first polysilicon on the wafer alignment key. After an interlayer dielectric is formed on the first polysilicon layer, a planarization process is performed. The interlayer dielectric is patterned into a predetermined pattern while leaving the interlayer dielectric on the wafer alignment key. The second polysilicon layer is deposited on the interlayer dielectric and polished by a chemical mechanical polishing(CMP) method while the second polysilicon layer on the wafer alignment key is completely polished.

Description

웨이퍼 정렬키 형성방법{Method of fabricating alignment key of wafer}Method of fabricating alignment key of wafer

본 발명은 웨이퍼 정렬키(alignment key) 형성방법에 관한 것으로, 특히 웨이퍼 정렬키상에 잔존하는 폴리실리콘 잔유물을 제거하여 폴리실리콘 잔유물 두께의 균일도 불량에 의한 정렬신호 강도의 저하를 방지할 수 있는 웨이퍼 정렬키의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wafer alignment key, and more particularly, to remove a polysilicon residue remaining on a wafer alignment key so as to prevent a decrease in alignment signal strength due to poor uniformity of polysilicon residue thickness. A method of forming a key.

웨이퍼 정렬시 레이저를 광원으로 사용할 경우 정렬신호(alignment signal)의 강도는 웨이퍼 정렬키의 깊이에 따라 주기적으로 변화하므로 웨이퍼 정렬키 깊이의 균일도가 불량할 경우 정렬 실패 또는 정렬 정확도의 감소가 발생한다.When the laser is used as a light source for wafer alignment, the intensity of the alignment signal changes periodically depending on the depth of the wafer alignment key. Thus, when the uniformity of the wafer alignment key depth is poor, alignment failure or reduction in alignment accuracy occurs.

웨이퍼 정렬시의 정확도를 향상시키기 위해서 마스크 작업시 웨이퍼 정렬키 위치를 오픈시켜 웨이퍼 정렬키위에 증착되는 막을 모두 제거하는 방법이 있다. 이 방법을 도 1a 내지 1f를 참조하여 간단히 설명하면 다음과 같다.In order to improve the accuracy of the wafer alignment, there is a method of removing all the films deposited on the wafer alignment key by opening the wafer alignment key position during the mask operation. This method is briefly described with reference to FIGS. 1A to 1F as follows.

먼저, 도 1a에 나타낸 바와 같이 웨이퍼 정렬키(1)를 형성한 후, 도 1b에 나타낸 바와 같이 제1폴리실리콘층을 식각하게 되는데, 이때 웨이퍼 정렬키(1)상의 폴리실리콘은 모두 제거되게 된다. 이어서 도 1c에 나타낸 바와 같이 층간절연막(3)을 증착하고 플로우 및 CMP에 의해 평탄화한 후, 도 1d에 나타낸 바와 같이 웨이퍼 정렬키 상부의 층간절연막을 제거하고, 랜딩 플러그(landing plug)용 폴리실리콘(4)을 증착한다. 다음에 도 1e에 나타낸 바와 같이 상기 랜딩 플러그용 폴리실리콘(4)을 CMP에 의해 연마한 후, 도 1f에 나타낸 바와 같이 포토레지스트(5)를 도포하고 후속공정인 제2폴리실리콘 콘택 마스크공정을 진행한다.First, as shown in FIG. 1A, after forming the wafer alignment key 1, as shown in FIG. 1B, the first polysilicon layer is etched, wherein all of the polysilicon on the wafer alignment key 1 is removed. . Subsequently, as shown in FIG. 1C, the interlayer insulating film 3 is deposited and planarized by flow and CMP. Then, as shown in FIG. 1D, the interlayer insulating film on the wafer alignment key is removed, and the polysilicon for landing plug is removed. (4) is deposited. Next, as shown in FIG. 1E, the landing plug polysilicon 4 is polished by CMP, and then the photoresist 5 is applied as shown in FIG. 1F, and a second polysilicon contact mask process, which is a subsequent process, is performed. Proceed.

상기 방법에서는 웨이퍼 정렬키위에 증착되는 막을 모두 제거하는데, 랜딩 플러그용 폴리실리콘을 CMP에 의해 연마할때 웨이퍼 정렬키위의 폴리실리콘은 웨이퍼 정렬키의 낮은 단차로 인하여 완전히 제거되지 않고 도 1e에 나타낸 바와 같이 폴리실리콘 잔유물로 남아 웨이퍼 정렬키의 깊이를 변화시킨다. 이 폴리실리콘 잔유물은 그 두께가 균일하지 않아 웨이퍼 정렬키 깊이를 불균일하게 만들며 이로 인해 정렬 실패 또는 정렬시 정확도 감소의 문제를 유발한다.The method removes all the films deposited on the wafer alignment key. When polishing the polysilicon for the landing plug by CMP, the polysilicon on the wafer alignment key is not completely removed due to the low step of the wafer alignment key, as shown in FIG. As a result, it remains as polysilicon residue to change the depth of the wafer alignment key. The polysilicon residues are non-uniform in thickness, resulting in uneven wafer alignment key depths, leading to misalignment or reduced accuracy in alignment.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 웨이퍼 정렬키위에 증착되는 막을 제거하지 않고 남김으로써 웨이퍼 정렬키의 단차를 높여 랜딩 플러그용 폴리실리콘의 CMP후에 폴리실리콘 잔유물이 완전히 제거되도록 하여 정렬키의 깊이를 균일하게 하여 정렬시의 정확도를 향상시킬 수 있도록 하는 웨이퍼 정렬키 형성방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above-described problems, by increasing the step of the wafer alignment key by removing the film deposited on the wafer alignment key to remove the polysilicon residues after the CMP of the polysilicon for the landing plug to completely remove the alignment key It is an object of the present invention to provide a method for forming a wafer alignment key, which makes it possible to improve the accuracy in alignment by making the depth uniform.

상기 목적을 달성하기 위한 웨이퍼 정렬키 형성방법은 반도체기판상의 소정영역에 웨이퍼 정렬키를 형성하는 단계와, 반도체기판상에 제1폴리실리콘을 증착하고 이를 소정패턴으로 패터닝하는바, 상기 웨이퍼 정렬키 상부에 제1폴리실리콘을 제거하지 않고 남기는 단계, 상기 제1폴리실리콘층상에 층간절연막을 형성하고 평탄화시키는 단계, 상기 층간절연막을 소정패턴으로 패터닝하는바, 상기 웨이퍼 정렬키 상부에 층간절연막을 제거하지 않고 남기는 단계, 상기 층간절연막상에 제2폴리실리콘을 증착하고 이를 CMP에 의해 연마하는바, 상기 웨이퍼 정렬키 상부에서는 완전히 연마되어 제거되도록 하는 단계를 포함한다.In order to achieve the above object, a method of forming a wafer alignment key includes forming a wafer alignment key in a predetermined region on a semiconductor substrate, depositing a first polysilicon on the semiconductor substrate, and patterning the first polysilicon into a predetermined pattern. Leaving the first polysilicon on the first polysilicon layer without removing the first polysilicon layer; forming and planarizing the interlayer dielectric layer on the first polysilicon layer; patterning the interlayer dielectric layer in a predetermined pattern; removing the interlayer dielectric layer on the wafer alignment key And leaving the second polysilicon on the interlayer dielectric layer, and polishing the second polysilicon on the interlayer dielectric layer by CMP, thereby completely grinding and removing the upper portion of the wafer alignment key.

도 1a 내지 1f는 종래기술에 의한 웨이퍼 정렬키 형성방법을 나타낸 공정순서도,1A to 1F are process flowcharts showing a method for forming a wafer alignment key according to the prior art;

도 2a 내지 2f는 본 발명에 의한 웨이퍼 정렬키 형성방법을 나타낸 공정순서도.2A to 2F are process flowcharts showing a method for forming a wafer alignment key according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11.웨이퍼 정렬키 12.제1폴리실리콘11.Wafer Alignment Key 12.First Polysilicon

13.층간절연막 14.랜딩플러그용 폴리실리콘13.Interlayer insulation film 14.Polysilicone for landing plug

15.PE-TEOS 16.포토레지스트15.PE-TEOS 16.Photoresist

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 2f에 본 발명에 의한 웨이퍼 정렬키 형성방법을 공정순서에 따라 도시하였다.2A to 2F illustrate a method for forming a wafer alignment key according to the present invention according to the process sequence.

먼저, 도 2a에 나타낸 바와 같이 반도체기판상의 소정영역에 웨이퍼 정렬키(11)를 형성한 후, 도 2b에 나타낸 바와 같이 제1폴리실리콘(12)을 증착하고 이를 소정패턴으로 패터닝하는 공정시 마스크의 웨이퍼 정렬키에 해당되는 위치를 Cr처리하여 웨이퍼 정렬키의 상부에 제1폴리실리콘이 제거되지 않고 남아 있도록 한다.First, as shown in FIG. 2A, a wafer alignment key 11 is formed in a predetermined region on a semiconductor substrate. Then, as shown in FIG. 2B, a mask in a process of depositing and patterning the first polysilicon 12 into a predetermined pattern. Cr-treated the position corresponding to the wafer alignment key of the first polysilicon so that the top of the wafer alignment key is not removed.

이어서 도 2c에 나타낸 바와 같이 층간절연막(13)으로 BPSG등을 증착하고 플로우한 후, CMP공정을 진행하여 웨이퍼 정렬키상의 층간절연막(13)을 평탄화시킨다.Subsequently, as shown in FIG. 2C, BPSG or the like is deposited and flowed into the interlayer insulating film 13, and then the CMP process is performed to planarize the interlayer insulating film 13 on the wafer alignment key.

다음에 도 2d에 나타낸 바와 같이 상기 층간절연막(13)을 선택적으로 식각하여 소정영역에 랜딩 플러그 콘택(도시하지 않음)을 형성하는바, 랜딩 플러그 콘택형성을 위한 마스크공정시 마스크의 웨이퍼 정렬키에 해당되는 위치를 Cr처리하여 웨이퍼 정렬키 상부에 층간절연막(13)이 제거되지 않고 남아 있도록 한다. 이어서 층간절연막(13)상에 랜딩 플러그용 폴리실리콘(14)을 증착한다. 상기와 같이 하면 웨이퍼 정렬키상에 폴리실리콘(12)과 층간절연막(13)이 제거되지 않고 남아 있으므로 웨이퍼 정렬키의 단차가 높아진다.Next, as shown in FIG. 2D, the interlayer insulating layer 13 is selectively etched to form a landing plug contact (not shown) in a predetermined region, and the wafer alignment key of the mask is formed during a mask process for forming the landing plug contact. The corresponding position is Cr-treated so that the interlayer insulating film 13 remains on the wafer alignment key without being removed. Then, the landing plug polysilicon 14 is deposited on the interlayer insulating film 13. In this manner, since the polysilicon 12 and the interlayer insulating film 13 remain on the wafer alignment key without being removed, the level of the wafer alignment key is increased.

이어서 도 2e에 나타낸 바와 같이 상기 랜딩 플러그용 폴리실리콘(14)을 CMP 에 의해 연마하는데 상기와 같이 높아진 단차로 인하여 웨이퍼 정렬키상의 층간절연막(13)위에 증착된 랜딩 플러그용 폴리실리콘은 CMP에 의해 완전히 제거된다.Then, as shown in FIG. 2E, the landing plug polysilicon 14 is polished by CMP, and the landing plug polysilicon deposited on the interlayer insulating film 13 on the wafer alignment key is formed by CMP due to the increased step. Completely removed.

다음에 도 2f에 나타낸 바와 같이 기판상에 PE-TEOS(15)를 증착하고 그위에 포토레지스트(16)를 도포한 후, 제2폴리실리콘 콘택 마스크공정을 진행하게 되는데 웨이퍼 정렬키의 깊이에는 변화가 없으며 웨이퍼 정렬키위에는광학적으로 투명한 층간절연막(BPSG)(13)과 PE-TEOS(15)만이 남아 있으므로 웨이퍼 정렬시 정렬 실패나 정렬 정확도의 저하등의 문제를 발생하는 일없이 제2폴리실리콘 콘택 마스크공정을 진행할 수 있다.Next, as shown in FIG. 2F, the PE-TEOS 15 is deposited on the substrate and the photoresist 16 is applied thereon, and then a second polysilicon contact mask process is performed. Only the optically transparent interlayer insulating film (BPSG) 13 and the PE-TEOS 15 remain on the wafer alignment kiln, so that the second polysilicon contact can be avoided without causing problems such as misalignment or degradation of alignment accuracy during wafer alignment. The mask process can be performed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

종래에는 랜딩플러그 콘택 마스크공정시 웨이퍼 정렬키위의 층간절연막이 제거되어 웨이퍼 정렬키의 단차가 낮아져 랜딩플러그 폴리실리콘의 CMP후에 폴리실리콘 잔유물이 웨이퍼 정렬키위에 불균일하게 남게 되어 웨이퍼 정렬키의 깊이를 불균일하게 만들어 이로 인해 정렬 실패나 정렬 정확도 저하의 문제가 유발되었으나, 본 발명에서는 랜딩플러그 콘택 마스크에서 웨이퍼 정렬키위의 층간절연막을 제거하지 않고 남겨 둠으로써 랜딩플러그 폴리실리콘 CMP시 폴리실리콘 잔유물이 완전히 제거되도록 하여 폴리실리콘 잔유물로 인해 웨이퍼 정렬키 깊이가 불균일해지는 것을 방지하여 정렬의 정확도를 향상시킨다.Conventionally, during the landing plug contact mask process, the interlayer insulating film on the wafer alignment key is removed and the step of the wafer alignment key is lowered so that the polysilicon residue remains unevenly on the wafer alignment key after the CMP of the landing plug polysilicon, resulting in uneven depth of the wafer alignment key. This caused a problem of misalignment or deterioration of alignment accuracy. However, in the present invention, the polysilicon residues are completely removed during landing plug polysilicon CMP by leaving the interlayer insulating layer on the wafer alignment key in the landing plug contact mask without removing it. This prevents the polysilicon residues from becoming uneven in the wafer alignment key depth, thereby improving the accuracy of the alignment.

Claims (4)

반도체기판상의 소정영역에 웨이퍼 정렬키를 형성하는 단계와,Forming a wafer alignment key in a predetermined region on the semiconductor substrate; 반도체기판상에 제1폴리실리콘을 증착하고 이를 소정패턴으로 패터닝하는바, 상기 웨이퍼 정렬키 상부에 제1폴리실리콘을 제거하지 않고 남기는 단계,Depositing a first polysilicon on a semiconductor substrate and patterning the first polysilicon into a predetermined pattern, leaving the first polysilicon on the wafer alignment key without removing it; 상기 제1폴리실리콘층상에 층간절연막을 형성하고 평탄화시키는 단계,Forming and planarizing an interlayer insulating film on the first polysilicon layer, 상기 층간절연막을 소정패턴으로 패터닝하는바, 상기 웨이퍼 정렬키 상부에 층간절연막을 제거하지 않고 남기는 단계,Patterning the interlayer dielectric layer to a predetermined pattern, and leaving the interlayer dielectric layer on the wafer alignment key without removing the interlayer dielectric layer; 상기 층간절연막상에 제2폴리실리콘을 증착하고 이를 CMP에 의해 연마하는바, 상기 웨이퍼 정렬키 상부에서는 완전히 연마되어 제거되도록 하는 단계를 포함하는 웨이퍼 정렬키 형성방법.Depositing a second polysilicon on the interlayer dielectric layer and polishing the second polysilicon by CMP, wherein the second polysilicon is completely polished and removed on the wafer alignment key. 제1항에 있어서,The method of claim 1, 상기 웨이퍼 정렬키 상부에 제1폴리실리콘을 제거하지 않고 남기는 단계는 상기 제1폴리실리콘의 패터닝공정시 사용하는 마스크의 웨이퍼 정렬키에 해당되는 위치를 Cr처리하여 패터닝공정을 실시함으로써 진행하는 것을 특징으로 하는 웨이퍼 정렬키 형성방법.The step of leaving the first polysilicon without removing the first polysilicon on the wafer alignment key may be performed by performing a patterning process by Cr-processing a position corresponding to the wafer alignment key of the mask used in the patterning process of the first polysilicon. A wafer alignment key forming method. 제1항에 있어서,The method of claim 1, 상기 웨이퍼 정렬키 상부에 남아 있는 층간절연막은 광학적으로 투명한 물질로 형성하는 것을 특징으로 하는 웨이퍼 정렬키 형성방법.The interlayer dielectric layer remaining on the wafer alignment key is formed of an optically transparent material. 제3항에 있어서,The method of claim 3, 상기 층간절연막은 BPSG로 형성하는 것을 특징으로 하는 웨이퍼 정렬키 형성방법.And the interlayer dielectric layer is formed of BPSG.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627510B1 (en) * 2002-03-29 2003-09-30 Sharp Laboratories Of America, Inc. Method of making self-aligned shallow trench isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627510B1 (en) * 2002-03-29 2003-09-30 Sharp Laboratories Of America, Inc. Method of making self-aligned shallow trench isolation

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