KR100499555B1 - method for manufacturing of semiconductor device - Google Patents
method for manufacturing of semiconductor device Download PDFInfo
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- KR100499555B1 KR100499555B1 KR10-2000-0063370A KR20000063370A KR100499555B1 KR 100499555 B1 KR100499555 B1 KR 100499555B1 KR 20000063370 A KR20000063370 A KR 20000063370A KR 100499555 B1 KR100499555 B1 KR 100499555B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
Abstract
본 발명은 셀 영역의 오버 폴리싱에 의한 부식을 방지함과 동시에 글로벌 평탄화(global planarization)가 가능한 반도체 소자의 제조방법에 관한 것으로서, 셀 영역과 주변 영역으로 정의된 반도체 기판상에 게이트 절연막을 개재하여 도전층 및 캡 절연막을 차례로 형성하는 단계와, 상기 셀 영역의 캡 절연막 및 도전층을 제 1 스페이스를 갖도록 패터닝하는 단계와, 상기 주변 영역의 캡 절연막 및 도전층을 상기 제 1 스페이스보다 좁은 제 2 스페이스를 갖도록 패터닝하는 단계와, 상기 패터닝된 캡 절연막 및 도전층의 양측면에 절연막 측벽을 형성하는 단계와, 상기 반도체 기판의 전면에 ILD막을 형성하는 단계와, 상기 ILD막의 표면을 평탄화시키는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device capable of preventing global corrosion and overplanarization of a cell region, and including a gate insulating film on a semiconductor substrate defined as a cell region and a peripheral region. Forming a conductive layer and a cap insulating layer in sequence, patterning the cap insulating layer and the conductive layer in the cell region to have a first space, and forming a cap insulating layer and the conductive layer in the peripheral region narrower than the first space; Patterning to have a space, forming insulating film sidewalls on both sides of the patterned cap insulating film and the conductive layer, forming an ILD film on the entire surface of the semiconductor substrate, and planarizing the surface of the ILD film. It is characterized by forming.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 셀(cell) 영역의 부식(erosion)과 평탄화를 향상시키는데 적당한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the erosion and planarization of a cell region.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1b는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1B are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도 1a에 도시한 바와 같이, 셀(cell) 영역과 주변(periphery) 영역으로 정의된 반도체 기판(11)상에 게이트 절연막(도시되지 않음)을 개재하여 폴리 실리콘막(12), 텅스텐 실리사이드(WSix)막(13), 캡 절연막(14)을 차례로 형성한다.As shown in FIG. 1A, a polysilicon film 12 and tungsten silicide (WSix) are disposed on a semiconductor substrate 11 defined as a cell region and a peripheral region through a gate insulating film (not shown). Film 13 and cap insulating film 14 are formed in this order.
이어, 셀 영역의 캡 절연막(14), 텅스텐 실리사이드막(13), 폴리 실리콘막(12)을 일정한 스페이스를 갖도록 패터닝한다.Subsequently, the cap insulating film 14, the tungsten silicide film 13, and the polysilicon film 12 in the cell region are patterned to have a predetermined space.
그리고 상기 반도체 기판(11)의 전면에 절연막을 형성한 후, 에치백하여 상기 선택적으로 패텅닝된 캡 절연막(14), 텅스텐 실리사이드막(13), 폴리 실리콘막(12)의 양측면에 절연막 측벽(15)을 형성한다.After the insulating film is formed on the entire surface of the semiconductor substrate 11, the insulating film sidewalls are formed on both sides of the cap insulating film 14, the tungsten silicide film 13, and the polysilicon film 12 selectively etched back. 15).
도 1b에 도시한 바와 같이, 상기 절연막 측벽(15)을 포함한 반도체 기판(11)의 전면에 ILD막(16)을 증착한 후, 전면에 CMP 공정으로 ILD막(16)의 표면을 폴리싱하여 셀 영역과 주변 영역간에 평탄화한다.As shown in FIG. 1B, after the ILD film 16 is deposited on the entire surface of the semiconductor substrate 11 including the insulating film sidewall 15, the surface of the ILD film 16 is polished by a CMP process on the entire surface of the cell. Planarize between the area and the surrounding area.
즉, 상기 ILD막(16)을 증착하면, 셀 영역과 주변 영역간의 단차가 3000Å이상 발생하므로 셀 에치백(cell etch back) 공정에서 셀 영역의 ILD막(16)을 낮추도록 폴리싱(polishing)한다.That is, when the ILD film 16 is deposited, the step between the cell region and the peripheral region is generated to be 3000 Å or more, so that the ILD film 16 of the cell region is polished in the cell etch back process. .
한편, 타임 폴리싱(time polishing)으로 CMP 공정을 진행하는 경우 셀 영역이 주변 영역보다 ILD막(16)이 높은 구조에서는 공정의 특성상 셀 영역부터 폴리싱이 되기 시작하며, 특히 밀도 측면에서도 셀 영역이 주변 영역보다 월등히 높으므로 오버 폴리싱이 발생할 우려가 있다.On the other hand, when the CMP process is performed by time polishing, in the structure where the cell region is higher in the ILD film 16 than the peripheral region, polishing starts from the cell region due to the characteristics of the process. Since it is much higher than the area, there is a fear that overpolishing occurs.
그러나 상기와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 밀도(density) 측면에서 셀 영역이 주변 영역보다 높아 ILD막의 폴리싱시 셀 영역이 오버 폴리싱됨으로서 셀 영역이 부식될 우려가 있다.First, in terms of density, the cell region is higher than the peripheral region, so that the cell region may be corroded because the cell region is overpolished during polishing of the ILD film.
둘째, 잔막 모니터링(monitoring)을 위한 주변 영역의 TEG(Test Element Group)들은 100㎛＊100㎛정도의 큰 사이즈(large size) 패턴으로 단순히 잔막 측정 역할만 한다.Second, test element groups (TEGs) in the peripheral area for residual film monitoring simply act as a residual film measurement in a large size pattern of about 100 μm * 100 μm.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 셀 영역의 오버 폴리싱에 의한 부식을 방지함과 동시에 글로벌 평탄화(global planarization)가 가능한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing global corrosion due to overpolishing of a cell region and enabling global planarization.
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 셀 영역과 주변 영역으로 정의된 반도체 기판상에 게이트 절연막을 개재하여 도전층 및 캡 절연막을 차례로 형성하는 단계와, 상기 셀 영역의 캡 절연막 및 도전층을 제 1 스페이스를 갖도록 패터닝하는 단계와, 상기 주변 영역의 캡 절연막 및 도전층을 상기 제 1 스페이스보다 좁은 제 2 스페이스를 갖도록 패터닝하는 단계와, 상기 패터닝된 캡 절연막 및 도전층의 양측면에 절연막 측벽을 형성하는 단계와, 상기 반도체 기판의 전면에 ILD막을 형성하는 단계와, 상기 ILD막의 표면을 평탄화시키는 단계를 포함하여 형성함을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of sequentially forming a conductive layer and a cap insulating film through a gate insulating film on a semiconductor substrate defined by a cell region and a peripheral region, the cell region Patterning the cap insulating film and the conductive layer to have a first space, and patterning the cap insulating film and the conductive layer in the peripheral area to have a second space narrower than the first space, and the patterned cap insulating film and the conductive material. Forming an insulating film sidewall on both sides of the layer, forming an ILD film on the entire surface of the semiconductor substrate, and planarizing the surface of the ILD film.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 셀(cell) 영역과 주변(periphery) 영역으로 정의된 반도체 기판(21)상에 게이트 절연막(도시되지 않음)을 개재하여 폴리 실리콘막(22), 텅스텐 실리사이드막(23), 캡 절연막(24)을 차례로 형성한다.As shown in FIG. 2A, a polysilicon film 22 and a tungsten silicide film (not shown) are disposed on a semiconductor substrate 21 defined as a cell region and a peripheral region through a gate insulating film (not shown). 23) and the cap insulating film 24 are formed in order.
여기서 상기 폴리 실리콘막(22)은 1000~3000Å 두께로 형성하고, 상기 텅스텐 실리사이드막(23)은 1000~2000Å 두께로 형성하며, 상기 캡 절연막(24)은 APCVD 또는 LPCVD법을 이용하여 1000~3000Å 두께로 각각 형성한다.Here, the polysilicon film 22 is formed to a thickness of 1000 ~ 3000Å, the tungsten silicide film 23 is formed to a thickness of 1000 ~ 2000Å, the cap insulating film 24 is 1000 ~ 3000Å by the APCVD or LPCVD method Form each with a thickness.
이어, 포토 및 식각공정을 통해 셀 영역 및 주변 영역의 캡 절연막(24), 텅스텐 실리사이드막(23), 폴리 실리콘막(22)을 선택적으로 패터닝한다.Subsequently, the cap insulation layer 24, the tungsten silicide layer 23, and the polysilicon layer 22 in the cell region and the peripheral region are selectively patterned through photo and etching processes.
여기서 상기 주변 영역에서 캡 절연막(24), 텅스텐 실리사이드막(23), 폴리 실리콘막(22)은 셀 영역보다 좁은 스페이스(space)를 갖도록 패터닝된다.In the peripheral area, the cap insulating film 24, the tungsten silicide film 23, and the polysilicon film 22 are patterned to have a narrower space than the cell area.
즉, 패터닝된 셀 영역의 라인 폭은 0.18㎛이하, 스페이스는 0.18㎛이지만 주변 영역의 라인 폭은 0.18㎛ 일 때 스페이스는 0.12㎛이하이다. That is, when the line width of the patterned cell area is 0.18 μm or less and the space is 0.18 μm, the space is 0.12 μm or less when the line width of the peripheral area is 0.18 μm.
그리고 상기 반도체 기판(21)의 전면에 APCVD 또는 LPCVD법에 의해 절연막을 1000~3000Å 두께로 형성한 후, 에치백 공정을 실시하여 상기 패터닝된 캡 절연막(24), 텅스텐 실리사이드막(23), 폴리 실리콘막(22)의 양측면에 절연막 측벽(25)을 형성한다.After the insulating film is formed on the entire surface of the semiconductor substrate 21 by the APCVD or LPCVD method, the insulating film is formed to have a thickness of 1000 to 3000 GPa, followed by an etch back process to form the patterned cap insulating film 24, the tungsten silicide film 23, and the poly An insulating film sidewall 25 is formed on both sides of the silicon film 22.
이때 상기 주변 영역에 형성되는 절연막 측벽(25)은 패터닝된 캡 절연막(24), 텅스텐 실리사이드막(23), 폴리 실리콘막(22)의 스페이스가 좁아 스페이스 갭-필(gap-fill)이 되어 주변 영역이 셀 영역보다 단차가 1000 ~ 2000Å이상 높게 된다.At this time, the insulating film sidewall 25 formed in the peripheral region has a narrow space between the patterned cap insulating film 24, the tungsten silicide film 23, and the polysilicon film 22 to form a space gap-fill. The area becomes higher than the cell area by 1000 to 2000 ms.
도 2b에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 ILD막(예를 들면 BPSG)(26)을 CVD법으로 6000~10000Å 두께로 증착한 후, 전면에 CMP 공정으로 상기 ILD막(26)을 폴리싱하여 셀 영역과 주변 영역간에 평탄화를 실시한다.As shown in FIG. 2B, an ILD film (for example, BPSG) 26 is deposited on the entire surface of the semiconductor substrate 21 to a thickness of 6000 to 10000 mm by CVD, and then the ILD film ( 26) to planarize between the cell area and the peripheral area.
여기서 상기 CMP 공정의 조건은 폴리싱(polishing) 압력은 2~6psi, 속도는 30~120rpm, 슬러리 프로우(slurry flow)는 100~200ml/min이다.The conditions of the CMP process is a polishing pressure of 2 ~ 6psi, a speed of 30 ~ 120rpm, slurry flow (slurry flow) is 100 ~ 200ml / min.
한편, 상기 CMP 공정은 타임 폴리싱(time polishing)에 의해 캡 절연막(25)의 표면으로부터 1500~2500Å까지 상기 ILD막(26)을 폴리싱한다.On the other hand, in the CMP process, the ILD film 26 is polished from 1500 to 2500 kPa from the surface of the cap insulating film 25 by time polishing.
이어, 상기 평탄화가 완료된 반도체 기판(21)에 800~900℃의 온도와 10~30분 동안 어닐 공정을 실시한다.Subsequently, the annealing process is performed on the planarized semiconductor substrate 21 at a temperature of 800 to 900 ° C. for 10 to 30 minutes.
도 3은 본 발명에 의한 반도체 소자를 나타낸 레이아웃도이다.3 is a layout diagram showing a semiconductor device according to the present invention.
도 3에 도시한 바와 같이, 셀 블록(cell block)(20)을 둘러싸고 있는 주변 영역에 셀 영역의 게이트 패턴보다 스페이스가 좁은 더미 패턴(dummy pattern)(30)을 형성한다.As shown in FIG. 3, a dummy pattern 30 having a smaller space than the gate pattern of the cell region is formed in a peripheral region surrounding the cell block 20.
여기서 상기 더미 패턴(30)은 게이트 패턴과 동일한 물질이고, 상기 게이트 패턴 형성시 동일한 공정에서 형성된다.The dummy pattern 30 is made of the same material as the gate pattern, and is formed in the same process when forming the gate pattern.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조방법은 다음과 같은 효과가 있다.As described above, the method for manufacturing a semiconductor device according to the present invention has the following effects.
첫째, 주변 영역의 단차를 셀 영역보다 높게 함으로서 셀 영역이 오버 폴리싱하는 것을 방지할 수 있다.First, it is possible to prevent overpolishing of the cell region by making the step of the peripheral region higher than the cell region.
둘째, 셀 영역의 오버 폴리싱을 방지함으로서 부식 현상을 방지할 수 있다. Second, the corrosion phenomenon can be prevented by preventing overpolishing of the cell region.
도 1a 내지 도 1b는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1B are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2b는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도2A to 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3은 본 발명에 의한 반도체 소자를 나타낸 레이아웃도3 is a layout diagram showing a semiconductor device according to the present invention;
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 폴리 실리콘막21 semiconductor substrate 22 polysilicon film
23 : 텅스텐 실리사이드막 24 : 캡 절연막23 tungsten silicide film 24 cap insulating film
25 : 절연막 측벽 26 : ILD막25 insulating film sidewall 26 ILD film
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| KR20000028095A (en) * | 1998-10-30 | 2000-05-25 | 김영환 | Method for preparing semiconductor device |
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