KR20000015577A - Method for forming a contact pad of a semiconductor device - Google Patents
Method for forming a contact pad of a semiconductor device Download PDFInfo
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- KR20000015577A KR20000015577A KR1019980035603A KR19980035603A KR20000015577A KR 20000015577 A KR20000015577 A KR 20000015577A KR 1019980035603 A KR1019980035603 A KR 1019980035603A KR 19980035603 A KR19980035603 A KR 19980035603A KR 20000015577 A KR20000015577 A KR 20000015577A
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- forming
- contact pad
- contact
- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는 반도체 장치의 콘택 패드(contact pad) 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact pad of a semiconductor device.
반도체 장치가 고집적화 됨에 따라, 다층 배선 기술이 요구된다. 다층 배선 기술에 있어서, 포토리소그라피(photolithography) 공정 마진을 확보하고 배선의 길이를 최소화시키기 위해서 절연층 및 도전층의 평탄화가 요구된다. 이러한 평탄화는 심각한 토폴로지(topology)로 인해 배선이 끊어지거나 단락(short) 되는 것을 방지하게 된다.As semiconductor devices become highly integrated, multilayer wiring technology is required. In the multilayer wiring technology, planarization of the insulating layer and the conductive layer is required in order to secure a photolithography process margin and minimize the length of the wiring. This planarization prevents the wires from breaking or shorting due to severe topology.
상기 평탄화 방법으로는 여러 가지가 사용되어 왔으나, 건식 식각(dry etch)에서는 선택비(selectivity)의 한계로 인해 최근 CMP(chemical mechanical polishing) 기술로 대체되고 있는 실정이다.Various methods have been used as the planarization method, but in the case of dry etching, the chemical mechanical polishing (CMP) technique has recently been replaced due to the limitation of selectivity.
이러한 CMP 기술에 의한 평탄화 공정의 예로서, 콘택 패드 형성 공정이 있다.An example of the planarization process by such a CMP technique is a contact pad formation process.
도 1a 내지 도 1d는 종래의 반도체 장치의 콘택 패드 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.1A to 1D are flowcharts sequentially illustrating processes of a method of forming a contact pad of a conventional semiconductor device.
도 1a를 참조하면, 종래의 반도체 장치의 콘택 패드 형성 방법은 먼저, 반도체 기판(1) 상에 게이트 전극(2) 예를 들어, 반도체 메모리 장치의 워드 라인(wordline)이 형성된다. 상기 게이트 전극(2)을 포함하여 반도체 기판(1) 전면에 층간절연막(4)이 증착 된다. 상기 층간절연막(4)은 예를 들어, BPSG(borophospho silicate glass) 등과 같은 산화막이다.Referring to FIG. 1A, in the conventional method for forming a contact pad of a semiconductor device, a gate electrode 2, for example, a word line of a semiconductor memory device is formed on a semiconductor substrate 1. The interlayer insulating film 4 is deposited on the entire surface of the semiconductor substrate 1 including the gate electrode 2. The interlayer insulating film 4 is, for example, an oxide film such as borophospho silicate glass (BPSG).
도 1b에 있어서, 상기 층간절연막(4)의 상부 표면이 평탄화 되도록 산화막 CMP 공정이 수행된다. 다음, 콘택홀 형성 마스크를 사용하여 상기 층간절연막(4)이 식각 되어 콘택홀(6)이 형성된 후, 상기 콘택홀(6)이 완전히 채워질 때까지 도전막(8)이 증착 된다.(도 1c) 상기 도전막(8)은 여기서, 폴리실리콘막이다.In FIG. 1B, an oxide film CMP process is performed to planarize the upper surface of the interlayer insulating film 4. Next, after the interlayer insulating film 4 is etched using the contact hole forming mask to form the contact hole 6, the conductive film 8 is deposited until the contact hole 6 is completely filled (FIG. 1C). The conductive film 8 is a polysilicon film here.
마지막으로, 상기 층간절연막(4)의 상부 표면이 노출될 때까지 도전막(8)이 CMP 공정으로 평탄화 식각 되면 도 1d에 도시된 바와 같이, 콘택 패드(8a)가 완성된다.Finally, when the conductive film 8 is flattened by the CMP process until the upper surface of the interlayer insulating film 4 is exposed, the contact pad 8a is completed as shown in FIG. 1D.
상술한 바와 같은 CMP 공정은 균일도(uniformity) 확보의 어려움 및 큰 제조 원가의 부담으로 인해 최근, 에치 백 공정(etch back process)의 사용이 적극적으로 도입 및 검토 중에 있다. 그리고, 일부 CMP 공정은 상기 에치 백 공정으로 대체 적용 중에 있다.As described above, the CMP process has recently been actively introduced and reviewed due to the difficulty of securing uniformity and the burden of large manufacturing cost. In addition, some CMP processes are being replaced by the etch back process.
그러나, 상기 에치 백 공정으로 콘택 패드(8b)를 형성하는 경우, 도 2에서와 같이, 콘택홀(6) 내에 폴리 리세스(poly recess)가 약 850 Å 정도(참조 부호 't')로 크게 발생된다. 이러한 콘택 프로파일(contact profile)의 불량은 후속 공정인 비트 라인 콘택(bit line contact) 및 스토리지 전극 콘택(storage electrode contact) 형성시 콘택 낫 오픈(contact not open) 등의 문제점을 유발하게 된다.However, when the contact pad 8b is formed by the etch back process, as shown in FIG. 2, the poly recess in the contact hole 6 is large at about 850 kPa (reference numeral 't'). Is generated. The failure of such a contact profile causes problems such as bit line contact and contact not open when forming storage electrode contact, which are subsequent processes.
본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 평탄화 공정시 웨이퍼 내 균일도를 확보할 수 있고, 후속 공정에 영향이 적은 콘택 프로파일을 구현할 수 있는 반도체 장치의 콘택 패드 형성 방법을 제공함에 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, and provides a method for forming a contact pad of a semiconductor device capable of ensuring uniformity in a wafer during a planarization process and realizing a contact profile with less influence on subsequent processes. There is a purpose.
본 발명의 다른 목적은 CMP 보다 저렴한 단가로 CMP와 동일한 콘택 프로파일을 구현할 수 있고, 후속 공정에서의 공정 마진(process margin)을 확보할 수 있는 반도체 장치의 콘택 패드 형성 방법을 제공함에 있다.Another object of the present invention is to provide a method for forming a contact pad of a semiconductor device which can implement the same contact profile as CMP at a lower cost than CMP, and can secure a process margin in a subsequent process.
도 1a 내지 도 1d는 종래의 반도체 장치의 콘택 패드 형성 방법의 공정들을 순차적으로 보여주는 흐름도;1A to 1D are flowcharts sequentially showing processes of a method for forming a contact pad of a conventional semiconductor device;
도 2는 종래 에치 백 공정으로 형성된 반도체 장치의 콘택 패드 구조를 보여주는 단면도;2 is a cross-sectional view showing a contact pad structure of a semiconductor device formed by a conventional etch back process;
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 장치의 콘택 패드 형성 방법의 공정들을 순차적으로 보여주는 흐름도.3A to 3E are flowcharts sequentially showing processes of a method for forming a contact pad of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1, 100 : 반도체 기판 2, 102 : 게이트 전극1, 100: semiconductor substrate 2, 102: gate electrode
4, 104 : 층간절연막 6, 106 : 콘택홀4, 104: interlayer insulating film 6, 106: contact hole
8, 108 : 도전막 8a, 8b, 108a : 콘택 패드8, 108: conductive films 8a, 8b, 108a: contact pad
(구성)(Configuration)
상술한 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 콘택 패드 형성 방법은, 반도체 기판(100) 상에 형성된 도전 구조물(102)과, 상기 도전 구조물(102)을 포함하여 반도체 기판(100) 전면에 형성되어 있되, 반도체 기판(100)의 일부가 노출되도록 형성된 콘택홀(106)을 포함하는 층간절연막(104)을 갖는 반도체 장치의 콘택 패드 형성 방법에 있어서, 상기 콘택홀(106)이 완전히 채워질 때까지 층간절연막(104) 상에 도전막(108)을 형성하는 단계; 상기 층간절연막(104)의 상부 표면이 노출될 때까지 상기 도전막(108)에 대해 높은 식각 선택비를 갖는 조건으로 상기 도전막(108)을 에치 백 하는 단계; 및 상기 도전막(108) 및 층간절연막(104)의 일부를 1 : 1 식각 선택비를 갖는 조건으로 에치 백 하여 콘택 패드(108a)를 형성하는 단계를 포함한다.According to the present invention for achieving the above object, a method of forming a contact pad of a semiconductor device, the semiconductor substrate 100 including a conductive structure 102 formed on the semiconductor substrate 100, and the conductive structure 102 In the method for forming a contact pad of a semiconductor device having an interlayer insulating film 104 formed on a front surface thereof and including a contact hole 106 formed to expose a portion of the semiconductor substrate 100, the contact hole 106 is completely Forming a conductive film 108 on the interlayer insulating film 104 until filled; Etching back the conductive film (108) under conditions having a high etch selectivity with respect to the conductive film (108) until the upper surface of the interlayer insulating film (104) is exposed; And forming a contact pad 108a by etching back the portions of the conductive layer 108 and the interlayer insulating layer 104 under a condition having a 1: 1 etching selectivity.
이 방법의 바람직한 실시예에 있어서, 상기 도전막(108) 에치 백 공정은, 저스트 식각(just etch) 조건으로 수행된다.In a preferred embodiment of the method, the conductive film 108 etch back process is performed under just etch conditions.
(작용)(Action)
도 3d 및 도 3e를 참조하면, 본 발명의 실시예에 따른 신규한 반도체 장치의 콘택 패드 형성 방법은, 층간절연막의 상부 표면이 노출될 때까지 저스트 식각 조건으로 폴리실리콘막이 에치 백 된다. 폴리실리콘막 및 층간절연막의 일부가 1 : 1 의 식각 선택비를 갖는 조건으로 에치 백 되어 콘택 패드가 형성된다. 이와 같이, 2 단계 에치 백 공정으로 콘택 패드를 형성함으로써, 평탄화 식각 공정시 웨이퍼 내 균일도를 확보할 수 있고, 후속 공정에 영향이 적은 콘택 프로파일을 구현할 수 있다. 또한, CMP 보다 저렴한 단가로 CMP와 동일한 콘택 프로파일을 구현할 수 있고, 콘택 패드의 리세스를 최소화함으로써 후속 공정에서의 공정 마진을 확보할 수 있다.3D and 3E, in the method for forming a contact pad of a novel semiconductor device according to an embodiment of the present invention, the polysilicon layer is etched back under just etching conditions until the upper surface of the interlayer insulating layer is exposed. A portion of the polysilicon film and the interlayer insulating film are etched back under the condition of having an etching selectivity of 1: 1, thereby forming contact pads. As such, by forming the contact pad in the two-step etch back process, uniformity within the wafer may be secured during the planarization etching process, and a contact profile with less influence on subsequent processes may be realized. In addition, the same contact profile as CMP can be realized at a lower cost than CMP, and process margins in subsequent processes can be secured by minimizing recesses in the contact pads.
(실시예)(Example)
이하, 도 3을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 장치의 콘택 패드 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.3A through 3E are flowcharts sequentially illustrating processes of a method of forming a contact pad of a semiconductor device according to an embodiment of the present invention.
도 3a를 참조하면, 본 발명의 실시예에 따른 반도체 장치의 콘택 패드 형성 방법은 먼저, 반도체 기판(100) 상에 활성 영역과 비활성 영역을 정의하기 위해 STI(shallow trench isolation) 공정 등에 의해 소자격리막(도면에 미도시)이 형성된다.Referring to FIG. 3A, a method of forming a contact pad of a semiconductor device according to an exemplary embodiment of the present invention may first include a device isolation layer using a shallow trench isolation (STI) process to define an active region and an inactive region on a semiconductor substrate 100. (Not shown in the drawing) is formed.
상기 반도체 기판(100) 상에 게이트 전극(102) 예를 들어, 반도체 장치의 워드 라인이 형성된다. 상기 게이트 전극(102)은 다층의 도전막 패턴 및 이 도전막 패턴의 상부 및 양측벽을 덮도록 형성된 절연층을 포함한다. 이 절연층은 SAC(self align contact) 공정을 위해 후속 공정으로 증착 되는 층간절연막과 식각 선택비(etch selectivity)를 갖는 막질 예를 들어, 실리콘 질화막(SiN)으로 형성된다.A gate line 102, for example, a word line of a semiconductor device is formed on the semiconductor substrate 100. The gate electrode 102 includes a multilayer conductive film pattern and an insulating layer formed to cover upper and side walls of the conductive film pattern. The insulating layer is formed of an interlayer insulating film deposited in a subsequent process for a self align contact (SAC) process and a film having a etch selectivity, for example, silicon nitride (SiN).
상기 게이트 전극(102)을 포함하여 반도체 기판(100) 전면에 층간절연막(104)이 예를 들어, 약 9500Å의 두께로 증착 된다. 상기 층간절연막(104)은 예를 들어, BPSG 등의 산화막이다.An interlayer insulating film 104 is deposited on the entire surface of the semiconductor substrate 100 including the gate electrode 102, for example, to a thickness of about 9500 kV. The interlayer insulating film 104 is, for example, an oxide film such as BPSG.
도 3b를 참조하면, 상기 층간절연막(104)이 평탄한 상부 표면을 갖도록 CMP 공정으로 식각 된다. 즉, 상기 게이트 전극(102)이 형성된 고단차 영역과 게이트 전극(102)이 형성되지 않은 저단차 영역의 단차가 제거되도록 층간절연막(104)이 평탄화 식각 된다. 이때, 상기 층간절연막(104)은 약 6200Å의 두께로 남게 된다.Referring to FIG. 3B, the interlayer insulating film 104 is etched by a CMP process to have a flat upper surface. That is, the interlayer insulating film 104 is planarized and etched to remove the step difference between the high stepped region where the gate electrode 102 is formed and the low stepped region where the gate electrode 102 is not formed. At this time, the interlayer insulating film 104 is left to a thickness of about 6200Å.
다음, 도 3c에 있어서, 콘택홀 형성 마스크를 사용하여 활성 영역의 일부가 노출되도록 상기 층간절연막(104)이 식각 되어 콘택홀(106)이 형성된다. 상기 콘택홀(106)이 완전히 채워질 때까지 층간절연막(104) 상에 도전막(108)이 증착 된다. 상기 도전막(108)은 예를 들어, 폴리실리콘막이다.Next, in FIG. 3C, the interlayer insulating layer 104 is etched to expose a portion of the active region using a contact hole forming mask to form a contact hole 106. The conductive film 108 is deposited on the interlayer insulating film 104 until the contact hole 106 is completely filled. The conductive film 108 is, for example, a polysilicon film.
마지막으로, 상기 도전막(108)이 본 발명에 따른 2 단계 에치 백 공정으로 식각 되어 콘택 패드(108a)가 형성된다.Finally, the conductive film 108 is etched by a two-step etch back process according to the present invention to form a contact pad 108a.
구체적으로, 상기 층간절연막(104)의 상부 표면이 노출될 때까지 상기 도전막(108)에 대해 높은 식각 선택비를 갖는 조건으로 상기 도전막(108)이 저스트(just) 에치 백 된다.(도 3d) 다음, 층간절연막(104) 및 도전막(108)의 일부가 1 : 1 의 식각 선택비를 갖는 조건으로 에치 백 된다. 그러면, 도 3e에 도시된 바와 같이, 본 발명에 따른 리세스가 최소화된 콘택 패드(108a)가 형성된다. 즉, CMP 공정과 동일한 콘택 프로파일을 갖는 콘택 패드(108a)가 형성된다. 이때, 상기 층간절연막(104)은 최종적으로 약 5200Å의 두께로 남게 된다.Specifically, the conductive film 108 is just etched back under conditions having a high etching selectivity with respect to the conductive film 108 until the upper surface of the interlayer insulating film 104 is exposed. 3d) Next, a portion of the interlayer insulating film 104 and the conductive film 108 are etched back under conditions having an etching selectivity of 1: 1. Then, as shown in Fig. 3E, a contact pad 108a with a minimized recess according to the present invention is formed. That is, contact pads 108a having the same contact profile as the CMP process are formed. At this time, the interlayer insulating film 104 is finally left to a thickness of about 5200Å.
본 발명은 콘택 패드 형성 공정 뿐아니라, 콘택 플러그 형성 공정을 포함하여 절연층과 도전층을 평탄화 식각 하는 모든 공정에 적용 가능하다.The present invention can be applied to not only the contact pad forming process but also all the processes of planarizing etching the insulating layer and the conductive layer, including the contact plug forming process.
본 발명은 2 단계 에치 백 공정으로 콘택 패드를 형성함으로써, 평탄화 식각 공정시 웨이퍼 내 균일도를 확보할 수 있고, 후속 공정에 영향이 적은 콘택 프로파일을 구현할 수 있는 효과가 있다.According to the present invention, by forming a contact pad in a two-step etch back process, it is possible to secure uniformity in the wafer during the planarization etching process and to implement a contact profile with less influence on subsequent processes.
또한, CMP 보다 저렴한 단가로 CMP와 동일한 콘택 프로파일을 구현할 수 있고, 콘택 패드의 리세스를 최소화함으로써 후속 공정에서의 공정 마진을 확보할 수 있는 효과가 있다.In addition, it is possible to implement the same contact profile as CMP at a lower cost than CMP, and to minimize the recess of the contact pad, thereby securing a process margin in a subsequent process.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980035603A KR20000015577A (en) | 1998-08-31 | 1998-08-31 | Method for forming a contact pad of a semiconductor device |
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| KR1019980035603A KR20000015577A (en) | 1998-08-31 | 1998-08-31 | Method for forming a contact pad of a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030055799A (en) * | 2001-12-27 | 2003-07-04 | 주식회사 하이닉스반도체 | A method for forming copper layer of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030055799A (en) * | 2001-12-27 | 2003-07-04 | 주식회사 하이닉스반도체 | A method for forming copper layer of semiconductor device |
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