KR20010046748A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce time and cost by decreasing the number of processes, and to prevent problems occurring from an exposed conductive layer by protecting a bit line material layer with a nitride layer. CONSTITUTION: The first insulating layer(32) is formed on a semiconductor substrate(31) having a gate and an impurity diffusion region. A plug connected to the impurity diffusion region through the first insulating layer is formed. The second insulating layer(34) is formed on the plug. A bit line material layer and the third insulating layer(36) are sequentially formed on the second insulating layer. A bit line(35a) is formed by an etch process using a photomask while the surface of the plug is exposed. The fourth and fifth insulating layers(38,39) are sequentially formed on the entire surface including the exposed plug. The fifth insulating layer is etched by using a photomask. The fourth insulating layer is etched to form a node contact(41) exposing the plug. A storage node connected to the plug through the node contact is formed. A dielectric layer and a plate node are sequentially formed on the storage node.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device suitable for forming bit lines and node contacts for maximizing photo alignment margin.

At present, as the integration of devices progresses, the design rule is reduced, and thus the photo alignment margin is also reduced, making the process very difficult.

Therefore, if the gap margin between the bit line and the node contact cannot be secured, a short between the two conductors is caused, which greatly affects the reliability of the device.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in Fig. 1A, a first oxide film 12 is formed on a formed semiconductor substrate 11 on which a gate and an impurity diffusion region (not shown) are formed.

The first oxide film 12 is etched to expose the impurity diffusion region to form a hole, and a plug 13 is formed by filling a conductive material in the hole.

Thereafter, the second oxide layer 14 is formed on the entire surface including the plug 13, and the bit line material layer 15 is sequentially formed on the second oxide layer 14.

After applying the photoresist on the bit line material layer 15, a photoresist pattern 16 for defining the bit line is formed.

Thereafter, as shown in FIG. 1B, the width of the photoresist pattern 16 is reduced by using O ₂ gas. That is, in the current photolithography process, it is difficult to form the gap between the patterns to be 0.2 μm or less, but since the bit line size should be formed to be 0.1 μm or less in consideration of the alignment margin between nodes to be formed later, the photoresist pattern A process for reducing the size of (16a) is needed.

Subsequently, as shown in FIG. 1C, the bit line material 15 is patterned using the reduced photoresist pattern 16 as a mask to form the bit lines 15a.

After the nitride film 17 is deposited on the entire surface including the bit lines 15a and as illustrated in FIG. 1D, the third oxide film 18 is formed on the nitride film 17, and then the third oxide film is formed. The polysilicon layer 19 for hard mask is formed on (18).

Subsequently, as shown in FIG. 1E, after the photoresist is applied on the polymask layer 19 for hard mask, a photoresist pattern 20 for node contact is formed.

As shown in FIG. 1F, the polysilicon layer 19 is etched using the photoresist pattern 20 as a mask to form a polysilicon pattern 19a, and as shown in FIG. 1G. After the polysilicon layer is formed on the entire surface including the polysilicon pattern 19a, the polysilicon layer pattern 21 is formed on the side surface of the polysilicon layer pattern 19a.

Thereafter, as shown in FIG. 1H, the third oxide film 18, the nitride film 17, and the second oxide film 14 are selectively etched using the poly-side wall 21 as a mask so that the plug 13 is etched. Node contacts 22 are formed to be exposed.

Subsequently, although not shown in the drawing, when a conductive material is embedded in the node contact 22 to form a storage node, and a dielectric layer and a plate node are formed on the storage node, a semiconductor device manufacturing process according to the prior art is completed. .

However, the conventional method of manufacturing a semiconductor device as described above has the following problems.

First, a process of reducing the size of the photoresist should be added to control the line size when forming the bit line.

Second, since the polysilicon layer and the poly side wall for the hard mask are used, the number of processes increases accordingly and the required cost and processing time increase.

Third, there is a variation in the size generated in each process, and the size of the holes generated in the process progress such as poly etching for photo / hard mask and etching for poly side wall accumulates to eventually open node contact failure. Cause.

Fourth, if the bit line is exposed during the hole etching due to the mis-alignment between the bit line and the node contact, equipment contamination and the substrate should be discarded. Tungsten is currently used as a material for bit lines, and when tungsten is exposed during several etching processes, it causes contamination of equipment, thereby lowering the reliability of the process.

Fifth, if a misalignment occurs between the plug and the node contact, a defect in contact with the gate tunic occurs.

The present invention has been made to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device that can simplify the process, prevent equipment contamination, improve the reliability of the process progress to improve the yield. There is a purpose.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Explanation of symbols for main parts of the drawings

31 semiconductor substrate 33 plug

32,34,36,38,39: 1st, 2nd, 3rd, 4th, 5th insulation layer

35 bit line material layer 35 a bit line

37,40 photoresist pattern 41 node contact

The semiconductor device manufacturing method of the present invention for achieving the above object is to form a first insulating layer on a semiconductor substrate formed with a gate and an impurity diffusion region, and a plug connected to the impurity diffusion region through the first insulating layer. Forming a second insulating layer on the plug, sequentially forming a bit line material layer and a third insulating layer on the second insulating layer, and forming a bit line by an etching process using a photomask. And simultaneously exposing the surface of the plug, forming a fourth insulating layer and a fifth insulating layer on the entire surface including the exposed plug, and etching the fifth insulating layer using a photomask. Etching the insulating layer to form a node contact to which the plug is exposed; forming a storage node connected to the plug through the node contact; And forming a dielectric film and a plate node in sequence on the storage node.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

As shown in Fig. 2A, a first insulating layer 32 is formed on a semiconductor substrate 31 on which a gate and an impurity diffusion region (not shown) are formed.

After applying the photoresist on the first insulating layer 32, a photoresist pattern (not shown) for defining the cell plug is formed using an exposure and development process.

The first insulating layer 32 is selectively etched using the photoresist pattern as a mask to form a contact hole to expose the substrate.

Thereafter, a conductive material is embedded in the contact hole to form a plug 33.

A second insulating layer 34 is formed on the entire surface including the plug 33, and a bit line material layer 35 is sequentially formed on the second insulating layer 34.

After the third insulating layer 36 is formed on the bit line material layer 35, a photoresist pattern 37 is formed on the third insulating layer 36.

In this case, an oxide film is used as the material of the first and second insulating layers 32 and 34, and a nitride film is used as the material of the third insulating layer 36.

The photoresist pattern 37 is used as a mask pattern for defining primary node contacts.

That is, as shown in FIG. 2B, the third insulating layer 36, the bit line material layer 35, and the third insulating layer 36 are exposed until the surface of the plug 33 is exposed using the photoresist pattern 37 as a mask. The second insulating layer 34 is selectively etched to form a bit line 35a having a third insulating layer 36 formed thereon.

The third insulating layer 36, the bit line material layer 35, and the second insulating layer 34 are etched by the same etching equipment.

Thereafter, as shown in FIG. 2C, a fourth insulating layer 38 is formed on the entire surface including the exposed plug 33 surface, and a fifth insulating layer 39 is formed on the fourth insulating layer 38. After sequentially forming, the top surface of the fifth insulating layer 39 is planarized.

Here, the material of the fourth insulating layer 38 uses the same nitride film as the third insulating layer 36, and the material of the fifth insulating layer 39 has a large etching selectivity with respect to the fourth insulating layer 38. An oxide film is used.

Thereafter, a photoresist pattern 40 for defining secondary node contacts is formed on the fifth insulating layer 39.

As shown in FIG. 2D, the fifth insulating layer 39 is selectively etched with respect to the fourth insulating layer 38 by an etching process using the photoresist pattern 40 as a mask.

As illustrated in FIG. 2E, when the fourth insulating layer 38 is etched to expose the surface of the plug 33, a node contact 41 is formed.

Subsequently, although not shown in the drawings, a storage node electrically connected to the plug 33 through a node contact 41 and a dielectric layer and a plate node are formed on the storage node. The manufacturing process is complete.

As mentioned above, the manufacturing method of the semiconductor element of this invention has the following effects.

First, the number of processes is reduced compared to the conventional process, reducing time and cost.

Second, since the nitride film protects the bit line material layer, problems caused by exposure of the conductive film (metal contamination of the equipment and metal contamination of the wafer) are prevented.

Third, since the conductive film is not exposed even if the size of the photoresist pattern for forming the node contact hole is increased (protected by the nitride film) in the photo process, the photo process can be performed with a stable size, thereby securing a margin according to the photo process. It is possible to secure the stability of.

Fourth, even if the plug and the node contacts are misaligned, the node and the gate are not in contact with each other. Since the nitride film is thin during the nitride film etching, the gate is not exposed due to the small amount of etching.

Fifth, since a node contact is formed at a time by using a photomask, there is little variation in hole size, so that there is almost no possibility of a hole open failure.

Claims (3)

Forming a first insulating layer on the semiconductor substrate on which the gate and the impurity diffusion region are formed, and forming a plug connected to the impurity diffusion region through the first insulating layer; Forming a second insulating layer on the plug, and sequentially forming a bit line material layer and a third insulating layer on the second insulating layer; Forming a bit line by an etching process using a photomask and exposing the surface of the plug; Sequentially forming a fourth insulating layer and a fifth insulating layer on the entire surface including the exposed plug, Etching the fifth insulating layer using a photomask, and then etching the fourth insulating layer to form a node contact to which the plug is exposed; And forming a storage node connected to the plug through the node contact, and sequentially forming a dielectric layer and a plate node on the storage node. The method of claim 1, wherein the first, second, and fifth insulating layers use an oxide film, and the third, fourth insulating layers use a nitride film. The method of claim 1, further comprising forming a fifth insulating layer on the fourth insulating layer and flattening an upper surface of the fifth insulating layer.