KR20010046339A - A method for forming metal contact for improving contact resistance in semiconductor device - Google Patents
A method for forming metal contact for improving contact resistance in semiconductor device Download PDFInfo
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- KR20010046339A KR20010046339A KR1019990050062A KR19990050062A KR20010046339A KR 20010046339 A KR20010046339 A KR 20010046339A KR 1019990050062 A KR1019990050062 A KR 1019990050062A KR 19990050062 A KR19990050062 A KR 19990050062A KR 20010046339 A KR20010046339 A KR 20010046339A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 42
- 239000010937 tungsten Substances 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 75
- 230000008569 process Effects 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000006722 reduction reaction Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 2
- 239000010936 titanium Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005549 size reduction Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 하지층과 상부층을 전기적으로 연결시키기 위한 금속 콘택 형성 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal contact forming technology for electrically connecting an underlayer and an upper layer of a semiconductor device.
반도체 소자의 집적도가 증가함에 따라 배선의 선폭 및 콘택홀의 크기가 감소하고 있다. 따라서, 콘택홀의 크기에 대한 콘택홀의 깊이의 비(aspect ratio, 이하, 단차비라 함)는 계속하여 증가하고 있다. 이때, 고단차비의 콘택을 형성하기 위하여 실시하는 식각 공정에서 콘택홀의 입구 크기에 비해 콘택홀의 바닥(하지층과 접촉하는 부위, open area)의 크기가 작게 형성되는 것이 일반적이다. 콘택홀의 입구 크기와 바닥의 크기의 차이는 콘택홀의 깊이 및 단차비가 증가함에 따라 증가하게 된다.As the degree of integration of semiconductor devices increases, the line width of the wiring and the size of the contact holes decrease. Therefore, the ratio of the depth of the contact hole to the size of the contact hole (hereinafter, referred to as a step ratio) continues to increase. At this time, in the etching process performed to form the contact having a high step ratio, the size of the bottom of the contact hole (the area in contact with the underlying layer, the open area) is generally smaller than the inlet size of the contact hole. The difference between the size of the contact hole and the bottom of the contact hole increases as the depth and step ratio of the contact hole increase.
이러한 현상은 콘택의 접촉 저항 특성을 확보하는데 지대한 문제를 야기한다. 즉, 콘택에서의 접촉 저항은 접촉하는 면적에 반비례하는 특성이 있기 때문에 콘택 바닥의 크기 감소는 곧 접촉 저항의 증가를 의미하게 된다. 더욱이 반도체 소자의 집적도 증가에 따른 콘택 크기의 감소에 따라 약간의 콘택 크기 변화에 대해서도 접촉 저항은 크게 변화한다. 예를 들어, 콘택의 크기가 0.4㎛인 경우 0.02㎛의 콘택의 크기 감소는 5%에 해당하지만, 콘택의 크기가 0.2㎛인 경우 0.02㎛의 크기 감소는 10%의 크기 감소를 의미한다. 이를 콘택 면적으로 환산할 경우 각각 1.21배와 1.44배의 콘택 면적 감소를 의미하며, 이는 그 만큼의 접촉 저항의 증가를 의미하는 것이다.This phenomenon causes a great problem in securing the contact resistance characteristics of the contact. In other words, since the contact resistance in the contact is inversely proportional to the contact area, the decrease in the size of the contact bottom means an increase in the contact resistance. Furthermore, as the contact size decreases due to the increase in the degree of integration of the semiconductor device, the contact resistance changes significantly even with a slight change in the contact size. For example, if the size of the contact is 0.4 μm, the size reduction of the contact of 0.02 μm corresponds to 5%, but if the size of the contact is 0.2 μm, the size reduction of 0.02 μm means the size reduction of 10%. When converted into contact area, this means 1.21 times and 1.44 times reduction in contact area, respectively, which means that the contact resistance increases as much.
정리하면, 콘택홀의 형성 과정에서 일반적으로, 콘택 바닥의 크기는 감소한다. 이러한 현상은 반도체 소자의 집적도가 증가함에 따라 접촉 저항을 크게 증가시킬 수 있는 요인으로 작용하여 소자의 동작에 막대한 지장을 초래할 수 있다.In summary, in the process of forming the contact hole, the size of the contact bottom is generally reduced. This phenomenon acts as a factor that can greatly increase the contact resistance as the degree of integration of the semiconductor device increases, which may cause a significant disruption to the operation of the device.
한편, 식각 공정을 통하여 형성된 콘택홀에 금속 콘택 공정을 진행할 때 통상 티타늄(Ti)을 먼저 형성하고 있다. 이는 콘택 바닥에서 접하고 있는 실리콘(Si)과의 접촉 저항을 낮추기 위한 것으로, 이때 티타늄은 주로 스퍼터링 방식을 이용하여 형성하고 있으며, 최근에는 화학기상증착(CVD) 방식을 이용하려는 시도가 나타나고 있다.Meanwhile, when a metal contact process is performed in a contact hole formed through an etching process, titanium (Ti) is usually formed first. This is to reduce the contact resistance with the silicon (Si) in contact with the bottom of the contact, wherein the titanium is mainly formed by the sputtering method, and recently, attempts to use the chemical vapor deposition (CVD) method has been shown.
그런데, 콘택 바닥에서 티타늄과 실리콘이 접하는 면적은 식각 공정에서 형성된 면적과 크게 다르지 않다. 따라서, 이처럼 티타늄을 사용하는 통상의 콘택 공정에서는 감소된 콘택 바닥의 면적을 증가시키는 효과를 기대할 수 없다.However, the area where titanium and silicon contact at the contact bottom is not significantly different from the area formed in the etching process. Thus, in the conventional contact process using titanium, the effect of increasing the area of the reduced contact bottom cannot be expected.
본 발명은 콘택홀 바닥의 실리콘 접합(junction)과 접촉하는 금속의 면적을 넓혀 접촉 저항을 낮출 수 있는 반도체 소자의 금속 콘택 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal contact of a semiconductor device capable of lowering contact resistance by widening an area of a metal contacting a silicon junction of a contact hole bottom.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 금속 콘택 형성 공정도.1A to 1D are diagrams illustrating a metal contact forming process according to an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 다른 실시예에 따른 금속 콘택 공정도.2a to 2e are metal contact process diagrams according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 층간절연막10 silicon substrate 11 interlayer insulating film
12 : 텅스텐층 13 : 확산장벽층12: tungsten layer 13: diffusion barrier layer
14 : 배선 금속층14: wiring metal layer
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 금속 콘택 형성방법은, 소정의 하부층 공정을 통해 실리콘 기판 상에 형성된 층간절연막을 선택 식각하여 상기 실리콘 기판에 형성된 접합층을 노출시키는 콘택홀을 형성하는 제1 단계; 상기 접합층으로부터 제공된 실리콘(Si)과 WF6가스의 실리콘 환원 반응에 의해 상기 접합층 표면에 텅스텐층을 선택 증착하되, 상기 텅스텐층이 상기 층간절연막과 상기 접합층의 계면을 따라 일정 길이만큼 측면 성장되도록 하는 제2 단계; 및 금속층으로 상기 콘택홀을 매립하는 제3 단계를 포함하여 이루어진다.Technical Solution The method of forming a metal contact of a semiconductor device of the present invention for solving the above technical problem is a contact for exposing a bonding layer formed on a silicon substrate by selectively etching an interlayer insulating film formed on a silicon substrate through a predetermined lower layer process. Forming a hole; Selective deposition of a tungsten layer on the surface of the junction layer by silicon reduction reaction of silicon (Si) and WF 6 gas provided from the junction layer, the tungsten layer is a side length by a predetermined length along the interface between the interlayer insulating film and the junction layer A second step of allowing growth; And a third step of filling the contact hole with a metal layer.
또한, 본 발명은 소정의 하부층 공정을 통해 실리콘 기판 상에 형성된 층간절연막을 선택 식각하여 상기 실리콘 기판에 형성된 접합층을 노출시키는 콘택홀을 형성하는 제1 단계; 상기 접합층으로부터 제공된 실리콘(Si)과 WF6가스의 실리콘 환원 반응만으로 상기 접합층 표면에 제1 텅스텐층을 선택 증착하되, 상기 제1 텅스텐층이 상기 층간절연막과 상기 접합층의 계면을 따라 일정 길이만큼 측면 성장되도록 하는 제2 단계; 상기 WF6가스의 수소 환원 반응만으로 상기 제1 텅스텐층 상에 제2 텅스텐층을 선택 증착하는 제3 단계; 및 금속층으로 상기 콘택홀의 나머지 부분을 매립하는 제4 단계를 포함하여 이루어진다.The present invention also provides a first step of forming a contact hole exposing a bonding layer formed on the silicon substrate by selectively etching the interlayer insulating film formed on the silicon substrate through a predetermined lower layer process; Selectively depositing a first tungsten layer on the surface of the junction layer only by silicon reduction reaction of silicon (Si) and WF 6 gas provided from the junction layer, wherein the first tungsten layer is constant along the interface between the interlayer insulating layer and the junction layer. A second step of lateral growth by length; A third step of selectively depositing a second tungsten layer on the first tungsten layer only by hydrogen reduction reaction of the WF 6 gas; And a fourth step of filling the remaining portion of the contact hole with a metal layer.
즉, 본 발명은 텅스텐 선택 증착 메커니즘에서 실리콘 환원 반응만을 실시하는 경우, 텅스텐의 두께 성장은 일정 두께로 제한되고 층간절연막과 실리콘간의 계면으로 텅스텐이 측면 성장이 유도되는 원리를 이용하여 실질적인 금속 콘택 면적을 증가시켰으며, 이로써 콘택 저항을 저감할 수 있다.That is, in the present invention, when only the silicon reduction reaction is performed in the tungsten selective deposition mechanism, the thickness growth of tungsten is limited to a certain thickness, and a substantial metal contact area is utilized by using the principle that tungsten side growth is induced to the interface between the interlayer insulating film and silicon. This increases the contact resistance, thereby reducing the contact resistance.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 금속 콘택 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1D illustrate a metal contact formation process according to an embodiment of the present invention, which will be described with reference to the following.
본 실시예에 따른 공정은, 우선 도 1a에 도시된 바와 같이 소정의 하부층 공정을 통해 실리콘 기판(10) 상에 형성된 평탄화된 층간절연막(11)을 선택 식각하여 콘택홀을 형성하고, 통상적인 콘택 세정 공정을 진행한다.In the process according to the present embodiment, first, as shown in FIG. 1A, a contact hole is formed by selectively etching the planarized interlayer insulating film 11 formed on the silicon substrate 10 through a predetermined lower layer process, and forming a normal contact. Proceed with the cleaning process.
다음으로, 도 1b에 도시된 바와 같이 웨이퍼를 증착 챔버에 로딩하고 WF6(tungsten hexa fluoride) 가스를 1∼1000sccm 정도의 유량으로 유입시킨다. 이때, Ar, N2, He 등의 가스를 함께 사용할 수 있으나, H2또는 SiH4등과 같이 WF6을 환원 또는 분해할 수 있는 기체는 함께 유입시키지 않는다. 유입된 WF6가스는 실리콘산화물 또는 실리콘질화물과 같은 절연층과는 반응을 하지 않지만, 콘택 영역에 노출된 실리콘과는 반응을 한다. 즉, WF6이 Si에 의해 분해되어 텅스텐(W)층(12)이 성장하게 된다. 이때, 증착 온도는 200∼600℃이며, 예상되는 반응은 하기의 반응식 1과 같이 나타낼 수 있다.Next, as shown in FIG. 1B, the wafer is loaded into the deposition chamber, and tungsten hexa fluoride (WF 6 ) gas is introduced at a flow rate of about 1 to 1000 sccm. In this case, although gases such as Ar, N 2 and He may be used together, gases that may reduce or decompose WF 6 , such as H 2 or SiH 4 , may not be introduced together. The introduced WF 6 gas does not react with an insulating layer such as silicon oxide or silicon nitride, but with silicon exposed to the contact region. In other words, WF 6 is decomposed by Si to grow the tungsten (W) layer 12. At this time, the deposition temperature is 200 ~ 600 ℃, the expected reaction can be represented by the following reaction formula 1.
이러한 텅스텐의 선택적 증착(selective deposition)은 실리콘이 노출된 곳에서만 진행된다. 즉, 콘택홀의 바닥에서만 이러한 반응이 가능하다. 반응식 1을 잘 살펴보면 콘택홀 바닥의 실리콘이 소모되고 텅스텐층(12)이 증착됨을 알 수 있다. 이때, 소모되는 실리콘의 두께에 비하여 증착되는 텅스텐층(12)의 두께는 미세하게나마 작게 된다. 따라서, 원 내의 확대도에 도시된 바와 같이 층간절연막(11)과 하지의 실리콘 기판(10) 사이에 미세한 틈이 만들어지며, 이 틈을 따라 WF6계속 유입되어 노출된 실리콘을 만나면서 층간절연막(11)/실리콘 기판(10)의 계면을 따라 텅스텐층(12)이 측면으로 성장하게 된다. 이를 텅스텐의 잠식(encroachment, 확대도에서 'd'에 해당함)이라 하며, 텅스텐의 측면 성장은 금속층과 실리콘 기판(10)과의 접촉 면적의 증가를 의미한다. 미세하게 측면 성장한 텅스텐층(12)에 의해 접촉 면적은 크게 증가되며, 따라서 접촉 저항을 크게 낮출 수 있게 된다. 왜냐하면 접촉 저항은 접촉 면적에 반비례하기 때문이다. 예를 들어, 콘택 바닥의 크기가 0.1㎛인 경우 측벽으로 200Å 성장한 텅스텐은 1.2배의 접촉 면적 증가, 즉 44%의 접촉 저항을 감소할 수 있게 된다. 그러나, 과도한 텅스텐의 측면 성장은 인근하는 콘택과 단락(short)될 수 있으므로 그 정도를 적절히 조절하여야 한다. 본 발명에서는 측면 성장 길이를 50∼1000Å로 하는 것이 바람직하다. 한편, 실리콘을 소모하며 성장하는 텅스텐층(12)은 측면 방향으로 시간에 따라 그 길이가 계속 증가하는 반면에 수직 방향으로의 성장 두께가 제한되는 특성이 있다. 이는 실리콘을 소모하여 형성된 텅스텐층(12) 자체가 WF6과 Si의 반응을 방해하게 되어 일정 두께 이상 성장시킬 수 없기 때문이며, 그 두께는 약 100∼수백Å으로 얕은 접합(shallow junction)에 적용하게 알맞으며, 본 발명에서는 100∼500Å 정도가 바람직하다.This selective deposition of tungsten only occurs where silicon is exposed. That is, this reaction is possible only at the bottom of the contact hole. Looking closely at Scheme 1, the silicon at the bottom of the contact hole is consumed and the tungsten layer 12 is deposited. At this time, the thickness of the tungsten layer 12 deposited is slightly smaller than the thickness of the silicon consumed. Accordingly, as shown in the enlarged view of the circle, a minute gap is formed between the interlayer insulating film 11 and the underlying silicon substrate 10, and the interlayer insulating film 11 meets exposed silicon while WF 6 is continuously introduced along the gap. The tungsten layer 12 grows laterally along the interface of the C) / silicon substrate 10. This is called encroachment (corresponding to 'd' in the enlarged view), and the lateral growth of tungsten means an increase in the contact area between the metal layer and the silicon substrate 10. The finely laterally grown tungsten layer 12 greatly increases the contact area, thus greatly reducing the contact resistance. This is because the contact resistance is inversely proportional to the contact area. For example, when the contact bottom is 0.1 µm in size, tungsten grown 200 Å to the side wall can increase the contact area by 1.2 times, that is, reduce the contact resistance by 44%. However, excessive lateral growth of tungsten may be shorted with the neighboring contacts, so the extent should be controlled appropriately. In this invention, it is preferable to set side growth length to 50-1000 micrometers. On the other hand, the tungsten layer 12 that consumes silicon grows in length in the lateral direction with time, while the growth thickness in the vertical direction is limited. This is because the tungsten layer 12 formed by consuming silicon hinders the reaction between WF 6 and Si and cannot be grown beyond a certain thickness. The thickness of the tungsten layer 12 itself is about 100 to several hundred micrometers so that it can be applied to shallow junctions. In this invention, about 100-500 micrometers is preferable.
계속하여, 도 1c에 도시된 바와 같이 Ti/TiN, TiN 등의 확산장벽층(또는 접착층)(13)을 100∼1000Å 정도의 두께로 형성하고, 이어서 도 1d에 도시된 바와 같이 알루미늄, 구리, 텅스텐 - WF6을 환원시켜줄 H2및/또는 SiH4를 넣어 확산장벽층(13) 상부의 전면에 증착함 - 등의 배선 금속층(14)을 형성하여 금속 콘택 형성을 완료한다.Subsequently, as shown in FIG. 1C, a diffusion barrier layer (or adhesive layer) 13 such as Ti / TiN, TiN, or the like is formed to a thickness of about 100 to 1000 GPa, and as shown in FIG. 1D, aluminum, copper, The metal contact formation is completed by forming a wiring metal layer 14 such as tungsten, which deposits H 2 and / or SiH 4 to reduce WF 6 and is deposited on the entire surface of the diffusion barrier layer 13.
첨부된 도면 도 2a 내지 도 2e는 본 발명의 다른 실시예에 따른 금속 콘택 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2E illustrate a metal contact forming process according to another embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 금속 콘택 공정은, 우선 도 2a에 도시된 바와 같이 소정의 하부층 공정을 통해 실리콘 기판(20) 상에 형성된 평탄화된 층간절연막(21)을 선택 식각하여 콘택홀을 형성하고, 통상적인 콘택 세정 공정을 진행한다.In the metal contact process according to the present embodiment, first, as shown in FIG. 2A, the planarized interlayer insulating film 21 formed on the silicon substrate 20 is selectively etched through a predetermined lower layer process to form a contact hole. The phosphorus contact cleaning process is performed.
다음으로, 도 2b에 도시된 바와 같이 웨이퍼를 증착 챔버에 로딩하고 WF6(tungsten hexa fluoride) 가스를 유입시켜 콘택 영역의 실리콘 기판(20) 표면에 제1 텅스텐층(22a)을 성장시킨다. 여기까지는 상기 일 실시예의 도 2b에 도시된 바와 동일하며, H2, SiH4등과 같이 WF6을 환원 또는 분해할 수 있는 기체를 유입시키지 않는다.Next, as shown in FIG. 2B, the wafer is loaded into a deposition chamber and a tungsten hexa fluoride (WF 6 ) gas is introduced to grow the first tungsten layer 22a on the surface of the silicon substrate 20 in the contact region. Up to this point is the same as that shown in Figure 2b of the embodiment, do not introduce a gas capable of reducing or decomposing WF 6 , such as H 2 , SiH 4 .
이어서, 도 2c에 도시된 바와 같이 H2, SiH4등과 같이 WF6을 환원 또는 분해할 수 있는 기체를 WF6과 함께 유입시켜 제1 텅스텐층(22a)의 측면 성장을 제한하고 콘택의 수직 방향으로의 성장을 유도하여 제2 텅스텐층(22b)을 100∼10000Å 두께로 형성한다. 이때, 상기 도 1b의 확대도에 나타낸 바와 같은 미세한 틈이 메워지게 되며, 정도에 따라서는 단차비 감소에 도움을 줄 수 있다.Subsequently, as shown in FIG. 2C, a gas capable of reducing or decomposing WF 6 , such as H 2 , SiH 4, and the like, is introduced together with WF 6 to limit the lateral growth of the first tungsten layer 22a and the vertical direction of the contact. Growth is induced to form the second tungsten layer 22b to a thickness of 100 to 10000 mm 3. At this time, the minute gap as shown in the enlarged view of FIG. 1B is filled, and may help to reduce the step ratio depending on the degree.
계속하여, 도 2d에 도시된 바와 같이 확산장벽층(또는 접착층)(23)을 형성하고, 이어서 도 2e에 도시된 바와 같이 알루미늄, 구리, 텅스텐 - WF6을 환원시켜줄 H2및/또는 SiH4를 넣어 확산장벽층(23) 상부의 전면에 증착함 - 등의 배선 금속층(24)을 형성하여 금속 콘택 형성을 완료한다.Subsequently, as shown in FIG. 2D, a diffusion barrier layer (or adhesive layer) 23 is formed, followed by H 2 and / or SiH 4 to reduce aluminum, copper, tungsten—WF 6 as shown in FIG. 2E. To form a wiring metal layer 24, such as deposited on the entire surface of the diffusion barrier layer 23, to complete the metal contact formation.
상기의 일 실시예 및 다른 실시예에 따른 공정을 진행하게 되면, 콘택 영역의 실리콘 기판 표면 부분에서 선택적으로 측면 성장한 텅스텐층이 금속층과 실리콘의 콘택 면적을 증가시키는 결과를 초래하고, 이로써 금속 콘택의 콘택 저항을 줄일 수 있게 된다.When the process according to the above and other embodiments is performed, the tungsten layer selectively laterally grown on the surface portion of the silicon substrate of the contact region may increase the contact area of the metal layer and silicon, thereby increasing the contact area of the metal contact. The contact resistance can be reduced.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 상기 다른 실시예에서 제2 텅스텐층(22b)을 콘택홀 전체에 매립하여 콘택 플러그로 활용할 수도 있으나, 이 기술은 고단차비의 콘택홀에서 매립 특성에 한계를 드러내고 있어 자세히 설명하지는 않았다.For example, in another embodiment, the second tungsten layer 22b may be buried in the entire contact hole to be used as a contact plug. However, the technique has not been described in detail because it reveals a limitation in the buried property in the contact hole having a high step ratio.
접촉 저항의 확보는 반도체 소자의 집적도가 증가함에 따라 점차 매우 중요한 이슈(issue)로 떠오르고 있다. 본 발명에서 제안하는 공정 기술을 이용하는 경우, 콘택 크기의 증가 없이도 접촉 면적을 증가시켜 향후 차세대 초고집적 반도체소자에서도 접촉 저항을 안정적으로 확보할 수 있는 효과가 있으며, 이로써 소자의 신뢰성 향상, 동작속도 향상, 수율 향상 등의 효과를 얻을 수 있다.The securing of contact resistance is becoming a very important issue as the degree of integration of semiconductor devices increases. In the case of using the process technology proposed by the present invention, the contact area can be increased without increasing the contact size, so that the contact resistance can be stably secured in the next generation of ultra-high density semiconductor devices, thereby improving the reliability and operating speed of the device. The effect of yield improvement can be acquired.
Claims (10)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9758367B2 (en) | 2015-12-09 | 2017-09-12 | Analog Devices, Inc. | Metallizing MEMS devices |
| US10427931B2 (en) | 2016-06-28 | 2019-10-01 | Analog Devices, Inc. | Selective conductive coating for MEMS sensors |
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| JPS6473717A (en) * | 1987-09-16 | 1989-03-20 | Matsushita Electric Ind Co Ltd | Selective deposition of metal |
| JPH01160012A (en) * | 1987-12-17 | 1989-06-22 | Fujitsu Ltd | Vapor growth method |
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| JPS60130825A (en) * | 1983-12-19 | 1985-07-12 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61140133A (en) * | 1984-12-13 | 1986-06-27 | Toshiba Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9758367B2 (en) | 2015-12-09 | 2017-09-12 | Analog Devices, Inc. | Metallizing MEMS devices |
| US10427931B2 (en) | 2016-06-28 | 2019-10-01 | Analog Devices, Inc. | Selective conductive coating for MEMS sensors |
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