KR20010045968A - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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Publication number
KR20010045968A
KR20010045968A KR1019990049509A KR19990049509A KR20010045968A KR 20010045968 A KR20010045968 A KR 20010045968A KR 1019990049509 A KR1019990049509 A KR 1019990049509A KR 19990049509 A KR19990049509 A KR 19990049509A KR 20010045968 A KR20010045968 A KR 20010045968A
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sbt
thin film
capacitor
dielectric layer
semiconductor device
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KR1019990049509A
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Korean (ko)
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이석원
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박종섭
주식회사 하이닉스반도체
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Publication of KR20010045968A publication Critical patent/KR20010045968A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent reliability of the device from being degraded by a leakage current and dielectric loss, by forming a SrBi2Ta2O9(SBT) amorphous thin film between an SBT polycrystalline thin films and between the SBT polycrystalline thin film and an upper electrode. CONSTITUTION: A substrate(21) having a lower electrode(22) is prepared. A SrBi2Ta2O9(SBT) polycrystalline thin film(23a,23c) and an SBT amorphous thin film(23b,23d) are sequentially deposited on the lower electrode more than twice to form an SBT dielectric layer(23) of a multilayered structure. An upper electrode(24) is formed on the SBT dielectric layer.

Description

반도체 소자의 캐패시터 제조 방법 {Method of manufacturing a capacitor in a semiconductor device}Method of manufacturing a capacitor in a semiconductor device

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 강유전체 물질인 SrBi2Ta2O9(이하 SBT라 칭함)를 적용하는 SBT 캐패시터 제조에 있어, SBT 다결정질 박막 및 SBT 비정질 박막을 증착하는 공정을 반복하여 다층 구조의 SBT 유전체층을 형성하므로, 고온 열처리에 따른 Bi의 휘발을 보상하고 표면 거칠기를 완화시켜 누설 전류 감소 등 SBT 캐패시터의 전기적 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in the manufacture of an SBT capacitor applying SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT), a ferroelectric material, a process for depositing an SBT polycrystalline thin film and an SBT amorphous thin film Since the SBT dielectric layer having a multi-layer structure is repeatedly formed, the present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of compensating for volatilization of Bi due to high temperature heat treatment and relieving surface roughness to improve electrical characteristics of the SBT capacitor, such as a decrease in leakage current.

일반적으로, 반도체 소자가 고집적화 및 소형화되어감에 따라 캐패시터가 차지하는 면적 또한 줄어들고 있는 추세이다. 캐패시터의 면적이 줄어들고 있음에도 불구하고 소자의 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 정전 용량을 확보하기 위해 하부 전극을 3차원 구조로 형성하여 유효 표면적을 증대시키고 있으나, 이 방법 역시 한계에 도달하여 256M DRAM급 이상의 고집적 반도체 소자에는 적용할 수 없는 실정이다. 정전 용량을 확보하기 위한 다른 방법은 높은 유전율을 갖는 유전체를 사용하여 캐패시터를 제조하는 것이다.In general, as semiconductor devices are highly integrated and miniaturized, the area occupied by capacitors is also decreasing. Although the area of the capacitor is decreasing, the capacitance of the capacitor required for the operation of the device must be secured. In order to secure the capacitance, the lower electrode is formed in a three-dimensional structure to increase the effective surface area, but this method also reaches a limit and cannot be applied to a highly integrated semiconductor device of 256M DRAM or more. Another way to ensure capacitance is to manufacture a capacitor using a dielectric having a high dielectric constant.

최근, 높은 유전율을 갖는 SBT를 사용하여 SBT 캐패시터를 제조하는 방법이 연구되고 있다. 도 1에 도시된 바와 같이, SBT 캐패시터는 폴리실리콘 콘택 등과 같은 하부 구조가 형성된 기판(11) 상에 Pt, Ru, Ir 등과 같은 노블 메탈(noble metal)이나 RuO2, IrO2등과 같은 산화 금속물을 사용하여 하부 전극(12)을 형성하고, 하부 전극(12) 상에 SBT를 증착 및 열처리하여 SBT 유전체층(13)을 형성하고, Pt, Ir, Ru, RuO2, IrO2등과 같은 물질로 상부 전극(14)을 형성하여 제조된다.Recently, a method of manufacturing an SBT capacitor using an SBT having a high dielectric constant has been studied. As shown in FIG. 1, the SBT capacitor is a noble metal such as Pt, Ru, Ir, or a metal oxide such as RuO 2 , IrO 2 , or the like on a substrate 11 having a substructure such as a polysilicon contact. To form the lower electrode 12, deposit and heat-treat the SBT on the lower electrode 12 to form the SBT dielectric layer 13, the upper with a material such as Pt, Ir, Ru, RuO 2 , IrO 2 It is manufactured by forming the electrode 14.

상기한 종래의 SBT 캐패시터 제조 기술은 SBT 유전체층(13)을 형성할 때 고온 증착 이나 열처리 등을 통해 SBT 강유전체 박막의 결정화 공정을 포함하고 있다. 이는 다결정질 결정 구조하에서 SBT 유전체층(13)은 높은 유전 상수와 잔류 분극 등 강유전체로서의 성질을 제대로 나타낼 수 있기 때문이다. 그러나, 다결정질 박막은 결정립 계면이 누설전류의 전도 경로로 이용되기 때문에, 이러한 결정 구조의 SBT 유전체층(13)은 누설 전류 및 유전 손실의 증가를 가져오므로 SBT 캐패시터 소자의 전기적 특성을 열화 시킨다. 이러한 누설 전류를 줄이기 위하여 다양한 전극의 사용, 불순물 첨가 등 여러 방법이 시도 되고 있으나, 아직 만족할 만한 결과를 얻지 못하고 있다. 또한, SBT 유전체층(13) 형성을 위한 고온 열처리 공정시 SBT 유전체층(13)의 표면에서 Bi 성분의 휘발로 인하여 박막 특성을 열화 시키는 문제점도 있다.The conventional SBT capacitor manufacturing technique includes a crystallization process of the SBT ferroelectric thin film through high temperature deposition or heat treatment when forming the SBT dielectric layer 13. This is because, under the polycrystalline crystal structure, the SBT dielectric layer 13 can properly exhibit ferroelectric properties such as high dielectric constant and residual polarization. However, the polycrystalline thin film deteriorates the electrical characteristics of the SBT capacitor element because the SBT dielectric layer 13 having such a crystal structure causes an increase in leakage current and dielectric loss because the grain interface is used as a conductive path for leakage current. In order to reduce the leakage current, various methods such as the use of various electrodes and the addition of impurities have been attempted, but have not yet obtained satisfactory results. In addition, during the high temperature heat treatment process for forming the SBT dielectric layer 13, there is a problem in that the thin film characteristics are deteriorated due to the volatilization of Bi components on the surface of the SBT dielectric layer 13.

따라서, 본 발명은 SBT 캐패시터 제조에 있어, SBT 다결정질 박막 및 SBT 비정질 박막을 증착하는 공정을 반복하여 다층 구조의 SBT 유전체층을 형성하므로, 고온 열처리에 따른 Bi의 휘발을 보상하고 표면 거칠기를 완화시켜 누설 전류 감소 등 SBT 캐패시터의 전기적 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는 데 그 목적이 있다.Therefore, in the present invention, in the manufacture of the SBT capacitor, the process of depositing the SBT polycrystalline thin film and the SBT amorphous thin film is repeated to form a multi-layered SBT dielectric layer, thereby compensating for volatilization of Bi due to high temperature heat treatment and reducing surface roughness. An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of improving the electrical characteristics of the SBT capacitor, such as a reduction in leakage current.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 하부 전극이 형성된 기판이 제공되는 단계; 상기 하부 전극 상에 SBT 다결정질 박막 및 SBT 비정질 박막을 순차적으로 적어도 2회 이상 반복 증착하여 다층 구조의 SBT 유전체층을 형성하는 단계; 및 상기 SBT 유전체층상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device. Sequentially depositing an SBT polycrystalline thin film and an SBT amorphous thin film on the lower electrode at least twice in succession to form a multi-layered SBT dielectric layer; And forming an upper electrode on the SBT dielectric layer.

도 1은 종래 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a capacitor manufacturing method of a conventional semiconductor device.

도 2는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.2 is a cross-sectional view of a device for explaining a capacitor manufacturing method of a semiconductor device according to the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

11, 21: 기판 12, 22: 하부 전극11, 21: substrate 12, 22: lower electrode

13, 23: SBT 유전체층 23a, 23c: SBT 다결정질 박막13, 23: SBT dielectric layer 23a, 23c: SBT polycrystalline thin film

23b, 23d: SBT 비정질 박막 14, 24: 상부 전극23b, 23d: SBT amorphous thin film 14, 24: upper electrode

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도이다.2 is a cross-sectional view of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.

본 발명의 SBT 캐패시터는, 도 2에 도시된 바와 같이 폴리실리콘 콘택 등과 같은 하부 구조가 형성된 기판(21) 상에 Pt, Ru, Ir 등과 같은 노블 메탈(noble metal)이나 RuO2, IrO2등과 같은 산화 금속물을 사용하여 하부 전극(22)을 형성하고, 하부 전극(22) 상에 제 1 SBT 다결정질 박막(23a), 제 1 SBT 비정질 박막(23b), 제 2 SBT 다결정질 박막(23c) 및 제 2 SBT 비정질 박막(23d)을 순차적으로 증착하여 다층 구조의 SBT 유전체층(23)을 형성하고, Pt, Ir, Ru, RuO2, IrO2등과 같은 물질로 상부 전극(24)을 형성하여 제조된다.As shown in FIG. 2, the SBT capacitor of the present invention has a noble metal such as Pt, Ru, Ir, etc., or a noble metal such as RuO 2 , IrO 2, etc. formed on a substrate 21 having a substructure such as a polysilicon contact. The lower electrode 22 is formed using a metal oxide, and the first SBT polycrystalline thin film 23a, the first SBT amorphous thin film 23b, and the second SBT polycrystalline thin film 23c are formed on the lower electrode 22. And sequentially depositing the second SBT amorphous thin film 23d to form an SBT dielectric layer 23 having a multilayer structure, and forming the upper electrode 24 made of a material such as Pt, Ir, Ru, RuO 2 , IrO 2, and the like. do.

상기에서, 제 1 및 제 2 SBT 다결정질 박막(23a 및 23c)은 화학적 기상 증착법이나 물리적 기상 증착법으로 증착한 후, 결정화를 위한 급속 고온 열처리를 실시하여 형성한다. 이들 SBT 다결정질 박막(23a 및 23c)은 각 층별로 50 내지 200nm 의 두께로 형성되며, SBT 다결정질 박막(23a 및 23c) 내의 조성은 조성식 SrXBiYTa2O9에서 "X"가 0.6 내지 1.0이고, "Y"가 1.0 내지 1.5의 비율로 한다. 제 1 및 제 2 SBT 비정질 박막(23b 및 23d) 각각은 상온 내지 300℃의 온도에서 얇게 예를 들어 10 내지 30nm의 두께로 증착하여 형성한다. SBT 다결정질 박막(23a 및 23c)과 SBT 비정질 박막(23b 및 23d)은 Nb등 첨가 물질을 첨가하여 형성할 수 있다.In the above, the first and second SBT polycrystalline thin films 23a and 23c are formed by chemical vapor deposition or physical vapor deposition, followed by rapid high temperature heat treatment for crystallization. These SBT polycrystalline thin films 23a and 23c are formed to have a thickness of 50 to 200 nm for each layer, and the composition in the SBT polycrystalline thin films 23a and 23c has a "X" of 0.6 in the composition formula Sr X Bi Y Ta 2 O 9 . To 1.0, and "Y" is set at a ratio of 1.0 to 1.5. Each of the first and second SBT amorphous thin films 23b and 23d is formed by thinly depositing at a temperature of, for example, 10 to 30 nm at a temperature of from room temperature to 300 ° C. The SBT polycrystalline thin films 23a and 23c and the SBT amorphous thin films 23b and 23d can be formed by adding an additive material such as Nb.

상기한 본 발명의 실시예는 기존의 SBT 유전체층이 갖고 있는 문제점을 해결하고 원하는 물성의 SBT 유전체층을 얻기 위해, SBT 다결정질 박막을 제작한 후 SBT 비정질 박막을 얇은 두께로 제작하는 공정을 적어도 2회 이상 반복한다. 비정질 구조의 박막은 다결정질 구조의 박막에 비해 유전 상수도 작고, 강유전체로서의 특성을 나타내지 못하지만, 박막 내부에 물질 전달 경로가 형성되지 않기 때문에 누설 전류나 유전 손실이 매우 작다. 누설 전류는 전극을 통해서 소자 외부로 빠져나가는 것이므로 SBT 다결정질 박막 사이 및 다결정질 박막과 상부 전극 사이에 비정질 박막을 형성시키면 누설 전류의 이동 경로를 막을 수 있다. 이러한 효과를 가져오기 위해서는 비정질 박막의 두께가 그다지 두꺼울 필요가 없으므로, 유전 상수의 감소 등 강유전 특성에 열화를 가져오는 영향은 미미하다. 또한, 비정질 박막은 다결정질 박막에 비해 표면 거칠기를 완화시키는 특징을 가지므로, 웨이퍼 위치에 따른 특성 차이를 완화시키는 동시에 표면에서의 Bi 성분 휘발을 억제시킨다.In the above-described embodiment of the present invention, in order to solve the problems of the existing SBT dielectric layer and obtain an SBT dielectric layer having desired physical properties, the SBT amorphous thin film may be fabricated at least two times after the SBT polycrystalline thin film is manufactured. Repeat over. The thin film of the amorphous structure has a smaller dielectric constant than the thin film of the polycrystalline structure and does not exhibit characteristics as a ferroelectric, but the leakage current and the dielectric loss are very small because no mass transfer path is formed in the thin film. Since the leakage current flows out of the device through the electrode, an amorphous thin film is formed between the SBT polycrystalline thin film and between the polycrystalline thin film and the upper electrode to prevent the leakage current from moving. In order to obtain such an effect, the thickness of the amorphous thin film does not need to be very thick, and thus, the effect of deteriorating ferroelectric properties such as a decrease in dielectric constant is minimal. In addition, the amorphous thin film has a feature of relieving surface roughness in comparison with the polycrystalline thin film, thereby alleviating the difference in characteristics depending on the wafer position and suppressing the volatilization of Bi components on the surface.

상술한 바와 같이, 본 발명은 SBT 다결정질 박막 사이 및 SBT 다결정질 박막과 상부 전극 사이에 SBT 비정질 박막을 형성하므로 누설 전류와 유전 손실로 인한 소자의 신뢰도 저하를 방지할 수 있고, 고온 열처리시 발생하는 Bi 휘발 및 표면 거칠기 증가에 따른 소자 특성 열화를 감소시킬 수 있으며, 강유전체 본래의 특성을 유지하면서 신뢰도를 높이므로써 기억 소자의 전기적 물성 향상 및 안정화를 이룰 수 있다.As described above, the present invention forms an SBT amorphous thin film between the SBT polycrystalline thin film and between the SBT polycrystalline thin film and the upper electrode, thereby preventing the device from deteriorating reliability due to leakage current and dielectric loss, and occurring during high temperature heat treatment. The deterioration of the device characteristics due to the increase of Bi volatilization and surface roughness can be reduced, and the electrical properties of the memory device can be improved and stabilized by increasing the reliability while maintaining the original characteristics of the ferroelectric material.

Claims (5)

하부 전극이 형성된 기판이 제공되는 단계;Providing a substrate having a lower electrode formed thereon; 상기 하부 전극 상에 SBT 다결정질 박막 및 SBT 비정질 박막을 순차적으로 적어도 2회 이상 반복 증착하여 다층 구조의 SBT 유전체층을 형성하는 단계; 및Sequentially depositing an SBT polycrystalline thin film and an SBT amorphous thin film on the lower electrode at least twice in succession to form a multi-layered SBT dielectric layer; And 상기 SBT 유전체층상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming an upper electrode on the SBT dielectric layer. 제 1 항에 있어서,The method of claim 1, 상기 SBT 다결정질 박막은 화학적 기상 증착법이나 물리적 기상 증착법으로 50 내지 200nm 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The SBT polycrystalline thin film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by 50 to 200nm thickness by chemical vapor deposition or physical vapor deposition. 제 1 항에 있어서,The method of claim 1, 상기 SBT 비정질 박막은 상온 내지 300℃의 온도에서 10 내지 30nm 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The SBT amorphous thin film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 10 to 30nm at a temperature of room temperature to 300 ℃. 제 1 항에 있어서,The method of claim 1, 상기 SBT 다결정질 박막 내의 조성은 조성식 SrxBiyTa2O9에서 "X"가 0.6 내지 1.0이고, "Y"가 1.0 내지 1.5의 비율인 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The composition of the SBT polycrystalline thin film has a ratio of "X" of 0.6 to 1.0 and "Y" of 1.0 to 1.5 in the compositional formula Sr x Bi y Ta 2 O 9 . 제 1 항에 있어서,The method of claim 1, 상기 SBT 결정질 박막 및 상기 SBT 비정질 박막은 Nb와 같은 첨가 물질을 첨가하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The SBT crystalline thin film and the SBT amorphous thin film are formed by adding an additive material such as Nb.
KR1019990049509A 1999-11-09 1999-11-09 Method of manufacturing a capacitor in a semiconductor device KR20010045968A (en)

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KR100390845B1 (en) * 2001-06-30 2003-07-12 주식회사 하이닉스반도체 Ferroelectric capacitor in semiconductor device and forming method thereof
KR20050010650A (en) * 2003-07-22 2005-01-28 주식회사 하이닉스반도체 Method of manufacturing ferroelectric capacitor
KR20050062862A (en) * 2003-12-19 2005-06-28 주식회사 하이닉스반도체 Ferroelectric capacitor in semiconductor device and fabricating method thereof

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KR20000042388A (en) * 1998-12-24 2000-07-15 김영환 Ferroelectric capacitor of semiconductor device and fabrication method thereof

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JPH0822957A (en) * 1994-06-15 1996-01-23 Ramtron Internatl Corp Manufacture of ferroelectric bismuth layer oxide
KR19990005439A (en) * 1997-06-30 1999-01-25 김영환 Ferroelectric capacitor of semiconductor device and manufacturing method thereof
KR19990013720A (en) * 1997-07-09 1999-02-25 이데이노부유끼 Ferroelectric Capacitor, Manufacturing Method Thereof and Memory Cell Using the Capacitor
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390845B1 (en) * 2001-06-30 2003-07-12 주식회사 하이닉스반도체 Ferroelectric capacitor in semiconductor device and forming method thereof
KR20050010650A (en) * 2003-07-22 2005-01-28 주식회사 하이닉스반도체 Method of manufacturing ferroelectric capacitor
KR20050062862A (en) * 2003-12-19 2005-06-28 주식회사 하이닉스반도체 Ferroelectric capacitor in semiconductor device and fabricating method thereof

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