KR20010045487A - Stacked package - Google Patents

Stacked package Download PDF

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Publication number
KR20010045487A
KR20010045487A KR1019990048794A KR19990048794A KR20010045487A KR 20010045487 A KR20010045487 A KR 20010045487A KR 1019990048794 A KR1019990048794 A KR 1019990048794A KR 19990048794 A KR19990048794 A KR 19990048794A KR 20010045487 A KR20010045487 A KR 20010045487A
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KR
South Korea
Prior art keywords
package
stacked
substrate
stacked package
chip
Prior art date
Application number
KR1019990048794A
Other languages
Korean (ko)
Inventor
김명기
Original Assignee
박종섭
주식회사 하이닉스반도체
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Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1019990048794A priority Critical patent/KR20010045487A/en
Publication of KR20010045487A publication Critical patent/KR20010045487A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A stacked package is provided to simply modify a design for a signal interconnection between an upper module package and a lower module package when the design for the signal interconnection is changed, by installing a substrate between the upper and lower module packages. CONSTITUTION: An upper module package(30) is stacked on a lower module package(20) to increase memory capacity of a stacked package. The upper module package and the lower module package are interconnected while a substrate(40) for transferring an electrical signal is included in the stacked package.

Description

적층형 패키지{STACKED PACKAGE}Stacked Packages {STACKED PACKAGE}

본 발명은 적층형 패키지에 관한 것으로, 특히 적층되는 단품 패키지들의 외부단자가 되는 아웃 리드들의 설계변경이 용이해지도록 하는데 적합한 적층형 패키지에 관한 것이다.The present invention relates to a stacked package, and more particularly, to a stacked package suitable for facilitating a design change of out leads that are external terminals of stacked unit packages.

티 에스 오 피(TSOP)형태의 하부 패키지의 상부에 비 엘 피(BLP) 형태의 상부 단품 패키지를 적층하여 메모리 용량을 증대시킨 종래 적층형 패키지의 일예가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.An example of a conventional stacked package, in which a memory capacity is increased by stacking a BLP-type upper unit package on top of a TSOP-type lower package, is briefly described. Is as follows.

도 1에 도시된 바와 같이, 종래의 적층형 패키지는 패들(1)의 상면에 칩(2)이 부착되어 있고, 그 칩(2)과 리드프레임(3)의 인너리드(3a)가 금속와이어(4)로 연결되어 있으며, 칩(2), 금속와이어(4)의 일정부분을 감싸도록 형성된 몰딩된 봉지제(5)의 외측으로 돌출된 아웃리드(3b)로 구성되는 티 에스 오 피 형태의 하부 패키지(6)가 하측에 설치되어 있다.As shown in FIG. 1, in a conventional stacked package, a chip 2 is attached to an upper surface of a paddle 1, and the inner lead 3a of the chip 2 and the lead frame 3 is formed of a metal wire ( 4) is connected to the chip 2, formed of a TOSPI consisting of an outlead (3b) protruding to the outside of the molded encapsulant 5 formed to surround a portion of the metal wire (4) The lower package 6 is provided below.

그리고, 그 하부 패키지(6)의 상측에는 칩(7)의 하면 양측으로 리드(8)가 배치되어 있고, 그 리드(8)들이 금속와이어(9)로 연결되어 있으며, 그 리드(8)의 하단부가 노출됨 아울러 칩(7), 금속와이어(9)를 감싸도록 몰딩되는 봉지제(10)가 몰딩되어 있고, 그 리드(8)의 노출된 부분이 하부 패키지(6)의 아웃리드(3b)와 솔더(11)로 접합된 상부 패키지(12)가 설치되어 있다.Leads 8 are arranged on both sides of the lower surface of the chip 7 on the upper side of the lower package 6, and the leads 8 are connected by metal wires 9. The lower end portion is exposed, and an encapsulant 10 molded to enclose the chip 7 and the metal wire 9 is molded, and the exposed portion of the lid 8 is formed by the outlead 3b of the lower package 6. And the upper package 12 joined with the solder 11 is provided.

상기와 같이 구성되어 있는 적층형 패키지는 티 에스 오 피 형태의 하부 패키지(6)의 상측에 비 엘 피 형태의 상부 패키지(12)를 얼라인 하고, 하부 패키지(6)의 아웃리드(3b)와 상부 패키지(12)의 리드(8) 노출부를 솔더(11)로 솔더링 접합하여 적층형 패키지(13)를 구성한다.The stack-type package configured as described above aligns the upper package 12 of the BLP shape on the upper side of the lower package 6 of the TS package, and the outread 3b of the lower package 6 and An exposed portion of the lead 8 of the upper package 12 is soldered and bonded to the solder 11 to form the stacked package 13.

그러나, 그와 같이 적층되는 단품 패키지들 중 어느 한 패키지의 리드수가 증가되거나, 패키지들간의 신호연결구성을 변경하는 등의 설계변경이 이루어지는 경우에 상부 패키지(12)와 하부 패키지(6)의 전체를 다시 설계하여야 하는 문제점이 있었다.However, in the case where a design change such as an increase in the number of leads of one of the individual packages stacked as such or a signal connection configuration between the packages is made, the entirety of the upper package 12 and the lower package 6 is made. There was a problem that needs to be redesigned.

상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 신호연결구성을 용이하게 변경할 수 있도록 하는데 적합한 적층형 패키지를 제공함에 있다.Disclosure of Invention In view of the above problems, an object of the present invention is to provide a stacked package suitable for easily changing a signal connection configuration.

도 1은 종래 적층형 패키지의 구성을 보인 종단면도.1 is a longitudinal sectional view showing a configuration of a conventional stacked package.

도 2는 본 발명 적층형 패키지의 구성을 보인 정면도.Figure 2 is a front view showing the configuration of the present invention laminated package.

도 3은 본 발명 적층형 패키지를 부분적으로 보인 확대단면도.Figure 3 is an enlarged cross-sectional view partially showing the present invention laminated package.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20 : 하부 단품 패키지 30 : 상부 단품 패키지20: lower single piece package 30: upper single piece package

40 : 서브스트레이트 41 : 기판40: substrate 41: substrate

42,42' : 상,하부 컨텍터 43 : 회로선42,42 ': Upper and lower contactors 43: Circuit lines

상기와 같은 본 발명의 목적을 달성하기 위하여 하부 단품 패키지의 상측에 상부 단품 패키지를 적층하여 메모리 용량을 증대시킨 적층형 패키지에 있어서, 상기 상부 단품 패키지와 하부 단품 패키지를 연결함과 아울러 전기적인 신호를 전달하기 위한 서브스트레이트를 구비하여서 구성되는 것을 특징으로 하는 적층형 패키지가 제공된다.In order to achieve the object of the present invention as described above, in a stacked package in which an upper single package is stacked on an upper side of a lower single package to increase memory capacity, the upper single package and the lower single package are connected together with an electrical signal. A stacked package is provided that is configured with a substrate for delivery.

이하, 상기와 같이 구성되는 본 발명 적층형 패키지를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the embodiment of the accompanying drawings, the laminate package is configured as described above as follows.

도 2는 본 발명 적층형 패키지의 구성을 보인 정면도이고, 도 3은 본 발명 적층형 패키지를 부분적으로 보인 확대단면도로서, 도시된 바와 같이 본 발명 적층형 패키지는 하부 단품 패키지(20)의 상측에 상부 단품 패키지(30)가 설치되어 있고, 그 상부 단품 패키지(30)와 하부 단품 패키지(20)의 사이에 서브스트레이트(40)가 설치되어 있다.Figure 2 is a front view showing the configuration of the laminated package of the present invention, Figure 3 is an enlarged cross-sectional view showing a part of the laminated package of the present invention, as shown, the laminated package of the present invention is an upper single package on the upper side of the lower single package 20 30 is provided, and the substrate 40 is provided between the upper single package 30 and the lower single package 20.

상기 하부 단품 패키지(20)는 리드프레임(21)의 패들(21a) 상면에 칩(22)이 설치되어 있고, 그 칩(22)의 양측에는 인너리드(21b)들이 설치되어 있으며, 그 인너리드(21b)들과 상기 칩(22)는 금속와이어(23)로 연결되어 있고, 그 칩(22), 금속와이어(23), 인너리드(21b)의 일정부분을 감싸도록 봉지제(24)로 몰딩되어 있으며, 그 봉지제(24)의 외측으로는 아웃리드(21c)들이 돌출형성되어 있다.The lower unit package 20 is provided with a chip 22 on an upper surface of the paddle 21a of the lead frame 21, and inner leads 21b are provided on both sides of the chip 22, and the inner lead 21b and the chip 22 are connected to the metal wire 23, and the encapsulant 24 surrounds a portion of the chip 22, the metal wire 23, and the inner lead 21b. It is molded, and outleads 21c protrude from the outer side of the sealing agent 24. As shown in FIG.

상기 상부 단품 패키지(30)는 반도체 칩(31)의 하면 양측에 리드(32)들이 나열설치되어 있고, 그 리드(32)들은 칩(31)과 금속와이어(33)로 연결되어 있으며, 리드(32)의 하면을 노출시킴과 아울러 칩(31), 금속와이어(33), 리드(32)의 일정부분을 감싸도록 봉지제(34)로 몰딩되어 있다.The upper unit package 30 has leads 32 arranged on both sides of the lower surface of the semiconductor chip 31, and the leads 32 are connected to the chip 31 by a metal wire 33. The lower surface of the 32 is exposed and molded with an encapsulant 34 to cover a portion of the chip 31, the metal wire 33, and the lead 32.

상기 서브스트레이트(40)는 베이스 기판(41)의 상,하면 양단부에 "ㄴ"자형의 상,하부 컨텍터(42)(42')가 나열설치되어 있어서, 상부 컨텍터(42)는 상부 단품 패키지(30)의 리드(32) 노출부에 솔더(43)로 접속되어 있고, 하부 컨텍터(42')는 하부 단품 패키지(20)의 아웃리드(21c)에 솔더(44)로 접속되어 있으며, 그 컨텍터(42)(42')들은 기판(41)의 내부에 내설된 회로선(43)들에 의하여 전기적으로 연결되어 있다.The substrate 40 is provided with upper and lower contactors 42 and 42 'having a "b" shape on both upper and lower ends of the base substrate 41, and the upper contactor 42 is an upper unit. The lead 32 is exposed to the exposed portion of the package 30 by solder 43, and the lower contactor 42 'is connected by solder 44 to the outlead 21c of the lower unit package 20. The contactors 42 and 42 'are electrically connected to each other by circuit lines 43 inherent in the substrate 41.

상기와 같이 구성되어 있는 본 발명 적층형 패키지는 하부 단품 패키지(20)의 상측에 서브스트레이트(40)를 위치시키고, 하부 단품 패키지(20)의 아웃리드(21c)와 서브스트레이트(40)의 하부 컨텍터(42')를 솔더(44)로 접합한 다음, 그와 같이 설치된 서브스트레이트(40)의 상측에 상부 단품 패키지(30)를 위치시킨 상태에서 상부 단품 패키지(30)의 리드(32) 노출부와 서브스트레이트(40)의 상부 컨텍터(42)를 솔더(43)로 접합하는 순서로 진행하여 패키지의 적층작업을 완료하게 된다.In the stack package of the present invention having the above structure, the substrate 40 is positioned above the lower unit package 20, and the lower contact of the outread 21c and the substrate 40 of the lower unit package 20 is provided. The solder 42 'is bonded with the solder 44, and then the lead 32 of the upper unit package 30 is exposed with the upper unit package 30 positioned above the substrate 40 thus installed. The stacking operation of the package is completed by the process of joining the upper and the upper contactors 42 of the substrate 40 with the solder 43.

상기와 같은 적층형 패키지(50)의 신호연결을 설계변경하는 경우에는 상,하부 단품 패키지(30)(20)를 그대로 사용하는 상태에서 서브스트레이트(40)의 회로선(43)들을 변경하여 간단히 적층형 패키지(50)의 신호연결을 설계변경하게 된다.In the case of design change of the signal connection of the stacked package 50 as described above, the circuit lines 43 of the substrate 40 are simply changed by using the upper and lower unit packages 30 and 20 as they are. The signal connection of the package 50 is changed.

이상에서 상세히 설명한 바와 같이, 본 발명 적층형 패키지는 상부 단품 패키지와 하부 단품 패키지의 사이에 서브스트레이트를 설치하여, 상,하부 단품 패키지를 고정함과 아울러 신호전달의 경로가 되도록 함으로서, 상부 단품 패키지와 하부 단품 패키지의 신호연결 상의 설계변경이 발생되는 경우에 서브스트레이트의 회로선을 연결을 변경하는 것에 의하여 간단히 설계변경할 수 있다.As described in detail above, in the present invention, the stacked package includes a substrate installed between the upper single package and the lower single package to fix the upper and lower single packages and to provide a path for signal transmission. In the event of a design change on the signal connection of the lower unit package, the design can be easily changed by changing the connection of the circuit lines of the substrate.

Claims (2)

하부 단품 패키지의 상측에 상부 단품 패키지를 적층하여 메모리 용량을 증대시킨 적층형 패키지에 있어서, 상기 상부 단품 패키지와 하부 단품 패키지를 연결함과 아울러 전기적인 신호를 전달하기 위한 서브스트레이트를 구비하여서 구성되는 것을 특징으로 하는 적층형 패키지.A stacked package in which an upper single package is stacked on an upper side of a lower single package to increase memory capacity, wherein the stacked package includes a substrate for connecting an upper single package and a lower single package and transmitting an electrical signal. Stacked package characterized by. 제 1항에 있어서, 상기 서브스트레이트는 베이스 기판의 상,하면에는 "ㄴ"자형의 상,하부 컨텍터가 설치되어 있고, 그 상,하부 컨텍터들은 기판에 내설된 회로선에 의하여 전기적인 연결이 이루어진 것을 특징으로 하는 적층형 패키지.According to claim 1, wherein the substrate is provided with upper and lower contactors of the "b" shaped upper and lower surfaces of the base substrate, the upper and lower contacts are electrically connected by a circuit line built into the substrate Stacked package, characterized in that made.
KR1019990048794A 1999-11-05 1999-11-05 Stacked package KR20010045487A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020048315A (en) * 2002-03-16 2002-06-22 김영선 Semiconductor module package for image sensor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020048315A (en) * 2002-03-16 2002-06-22 김영선 Semiconductor module package for image sensor system

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