KR20010038586A - Apparatus for digital timing recovery - Google Patents

Abstract

PURPOSE: A digital timing restoring device capable of generating a reference clock by operating an output of a phase accumulator using a sine function is provided. CONSTITUTION: A comparator(400) compares reference timing phase information from a head end with a value from an n-bit counter(430), and a loop filter(410) smooths a phase difference from the comparator(400). A phase accumulator(440) accumulates a value from the loop filter(410). A sine function value generator(445) takes a sine function at the accumulated value, and a digital-to-analog converter(446) converts a sine function value into an analog sine waveform. A low pass filter(450) filters the analog sine function value, and the first limiter(460) judges whether an output of the low pass filter is less than a predetermined value to output a square wave. The n-bit counter(430) divides a pulse from the first limiter and generates timing phase information of a subscriber device to output the timing phase information to the comparator(400).

Description

Apparatus for digital timing recovery

The present invention relates to a digital timing recovery apparatus, and more particularly, to a digital timing recovery apparatus with low timing phase jitter in a communication network system.

In general, a communication network system uses a method of synchronizing a reference clock between a central device and a subscriber device for accurate time synchronization when the head end and the subscriber device need synchronization.

In a conventional synchronization device, a digital phase locked loop (DPLL) is used. When the reference clock is restored using the DPLL, a clock having a very large timing phase jitter is generated.

1 is a block diagram of a conventional timing recovery apparatus. The timing recovery apparatus of FIG. 1 includes a comparator 100, a loop filter 110, a phase accumulator 120, and an n-bit counter 130.

The comparator 100 compares the reference timing phase information transmitted from the central apparatus with the value divided by the n-bit counter 130 and outputs the phase difference. The loop filter 110 flattens the phase difference output from the comparator 100. The phase accumulator 120 accumulates the value output from the loop filter 110, and when the accumulated value overflows, the phase accumulator 120 outputs a pulse during the period of the operating frequency of the phase accumulator 120. This pulse becomes the reference clock signal recovered at the subscriber device. The n-bit counter 130 divides the pulse generated by the phase accumulator 120 to generate timing phase information of the subscriber device and outputs the timing phase information to the comparator 100.

The loop filter 110 includes a first multiplier 111, a second multiplier 112, a first adder 113, a limiter 114, a first delay unit 115, and a second adder 116. do.

The first and second multipliers 111 and 112 multiply the output values of the comparator 100 by predetermined constants α _p and α _i , respectively. The first adder 113 adds the output of the second multiplier 112 and the output of the first delay unit 115, and the limiter 114 outputs a pulse when the output of the first adder 113 is equal to or greater than a predetermined value. To the second adder 116. The first delay unit 115 delays the output of the limiter 113 and outputs the delayed output to the first adder 113. The second adder 116 adds the output of the first multiplier 111 and the output of the limiter 114 to output the flattened phase difference.

The phase accumulator 120 includes a third adder 121, a second delay unit 123, and a clock generator 124.

The third adder 121 adds the value output from the loop filter 110 and the output value of the second delay unit 123. When the overflow occurs in the added value, a pulse is output, and the second delay unit 123 delays the pulse output from the third adder 121 by the clock period generated by the clock generator 124.

2 illustrates overflow waveforms of the clock generated by the clock generator 124 and the output of the phase accumulator 120. The dotted line in the output waveform of phase accumulator 120 represents phase jitter. 3 illustrates an output waveform viewed from a clock generated by the clock generator 124 and an oscilloscope. Dotted lines represent timing phase jitter.

As shown, the timing phase jitter occurs for a time corresponding to the width of the clock before and after one clock of the output pulse.

Using this prior art to generate a clock with a very small timing phase jitter, the clock frequency of the DPLL must use a clock of a frequency less than the timing phase jitter. For example, a DPLL operating frequency clock of at least 200 MHz is required to generate a reference clock with timing phase jitter of ± 5 nsec or less.

In more detail, in the above-described timing restoration apparatus, since the reference clock is generated when an overflow occurs at the output of the phase accumulator 120, timing phase jitter is generated as much as an operating frequency for operating the phase accumulator 120. do. Therefore, it is not suitable for use as a reference frequency of a DPLL circuit that uses the recovered reference clock frequency to generate another frequency synchronized with this signal.

In addition, in order to reduce the timing phase jitter, the operating frequency of the phase accumulator 120 needs to be high, resulting in a complicated circuit and an additional oscillator for generating a high frequency.

An object of the present invention is to provide a digital timing recovery apparatus for generating a reference clock by calculating the output of the phase accumulator with a sine function.

1 is a block diagram of a conventional timing recovery apparatus.

FIG. 2 illustrates an overflow waveform of a clock and a phase accumulator output generated by the clock generator of FIG. 1.

FIG. 3 illustrates the clock generated by the clock generator of FIG. 1 and an output waveform viewed in an oscilloscope.

4 is a block diagram of a digital timing recovery apparatus according to the present invention.

FIG. 5 is a diagram illustrating a clock generated by the clock generator of FIG. 4, output waveforms of the LPF and the first limiter.

FIG. 6 is a waveform view of the waveform of FIG. 5 as an oscilloscope. FIG.

The present invention for achieving the technical problem in the digital timing recovery apparatus for generating a reference clock in the subscriber device from the reference timing phase information transmitted from the central unit, and divides the generated reference clock to output the phase information of the subscriber device; A comparator for obtaining a phase difference between reference timing phase information transmitted from the central apparatus and phase information of the subscriber apparatus; A loop filter to flatten the phase difference; A phase accumulator for accumulating the phase difference output from the loop filter according to a predetermined frequency; A sine function generator that takes a sine function value at the output of the phase accumulator; A limiter for determining an output value of the sine function value generator and outputting a reference clock according to the result; And a divider for dividing the output of the limiter and outputting the phase information of the subscriber device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a digital timing recovery apparatus according to the present invention. The apparatus according to FIG. 4 includes a comparator 400, a loop filter 410, an n-bit counter 430, a phase accumulator 440, a sine function generator 445, a digital-to-analog converter (DAC) 446, And a low pass filter (LPF) 450 and a first limiter 460.

The comparator 400 compares the reference timing phase information transmitted from the central apparatus with the value divided by the n-bit counter 430 and outputs the phase difference. The loop filter 410 flattens the phase difference output from the comparator 400. The phase accumulator 440 accumulates the values output from the loop filter 410, and the sine function generator 445 takes a sine function on the accumulated values and outputs the sine function, and the DAC 446 outputs the sine function analog sine wave. Output as a waveform. That is, the overflow of the accumulated value is not used, and the sine function is output to the accumulated result.

The LPF 450 filters and smoothes the output analog sine function value. The first limiter 460 determines whether the output of the LPF 450 is larger or smaller than a predetermined value and outputs a square wave clock. The n-bit counter 430 divides the pulse generated by the first limiter 460 to generate timing phase information of the subscriber device and outputs the timing phase information to the comparator 400.

The loop filter 410 includes first and second multipliers 411 and 412, a first adder 413, a second limiter 414, a first delay unit 415, and a second adder 416.

The first and second multipliers 411 and 412 multiply the phase difference output from the comparator 400 by the constants α _p and α _i . The first adder 413 adds the output of the second multiplier 412 to the output of the first delay 415. The second limiter 414 limits the output level of the first adder 413. The first delay unit 415 delays the output of the second limiter 414 and outputs the delayed output to the first adder 413. The second adder 416 adds the output of the second limiter 414 and the output of the first multiplier 411 to output the flattened phase difference from the current phase difference and the past phase difference.

Phase accumulator 440 includes a third adder 441, a second delayer 443, and a clock generator 444.

The third adder 441 adds the phase difference output from the loop filter 410 to the output of the second delay unit 443. The second delay unit 443 delays the output of the third adder 441 by the period of the clock generated by the clock generator 444 and outputs the result to the third adder 441. The clock generator 444 generates a clock according to the operating frequency of the phase accumulator 440. The sine function value generator 445 takes a sine function value with respect to the value output from the third adder 441. At this time, the sine function value generator 445 is preferably a memory for storing a look-up table for outputting sine function values for the values that can be output from the third adder 441. The DAC 446 converts the digital sine function value output from the sine function generator 445 into an analog waveform.

5 illustrates the clock generated by the clock generator 444 and the output waveforms of the LPF 450 and the first limiter 460.

FIG. 6 shows the waveform of the waveform of FIG. 5 as an oscilloscope, wherein the waveform shown is the timing phase information of the subscriber device. The dotted line shows the timing phase jitter, and it can be seen that the timing phase jitter is relatively smaller than the conventional case.

According to the present invention, the operating frequency of the DPLL can be relatively low by generating a sine function value for the result of phase accumulation and generating a reference clock. The operating frequency of the phase accumulator can be as low as three to four times the reference clock and timing phase jitter can be several nsec or less. In particular, by taking a sine function on the phase accumulation result, the reference clock can be restored even when the operating frequency of the phase accumulator is not an integer multiple of the reference clock.

Claims (4)

A digital timing recovery apparatus for generating a reference clock in a subscriber device from reference timing phase information transmitted from a central device, and dividing the generated reference clock to output the phase information of the subscriber device. A comparator for obtaining a phase difference between the reference timing phase information transmitted from the central apparatus and the phase information of the subscriber apparatus; A loop filter to flatten the phase difference; A phase accumulator for accumulating the phase difference output from the loop filter according to a predetermined frequency; A sine function generator that takes a sine function value at the output of the phase accumulator; A limiter for determining an output value of the sine function value generator and outputting a reference clock according to the result; And And a divider which divides an output of the limiter and outputs the phase information of the subscriber device. The sine function generator of claim 1, wherein And a memory configured to store a look-up table having a sine function value corresponding to the output value of the phase accumulator. The generator of claim 2, wherein the sine function generator And a digital-analog converter for converting the digital value output from the memory into an analog value. 4. The generator of claim 3, wherein the sine function generator And a low pass filter for flattening the output of said digital-to-analog converter.