KR20010037576A - method of manufacturing in SRAM cell - Google Patents
method of manufacturing in SRAM cell Download PDFInfo
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- KR20010037576A KR20010037576A KR1019990045161A KR19990045161A KR20010037576A KR 20010037576 A KR20010037576 A KR 20010037576A KR 1019990045161 A KR1019990045161 A KR 1019990045161A KR 19990045161 A KR19990045161 A KR 19990045161A KR 20010037576 A KR20010037576 A KR 20010037576A
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- insulating layer
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- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체 메모리 소자에 관한 것으로, 특히 공정을 단순화 시키고, 콘택 사이즈에 따라 하부 막질의 식각 비율를 개선시키는데 적당한 에스램 셀의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of manufacturing an SRAM cell suitable for simplifying a process and improving an etching rate of a lower film quality according to contact size.
일반적으로 SRAM 셀은 4개의 트랜지스터(예를 들면, 2개의 액세스 트랜지스터들 및 2개의 드라이브 트랜지스터들)와 2개의 폴리 실리콘 부하저항으로 구성되거나 또는 6개의 트랜지스터들로 구성된다. →특히, 4M급 이상의 고집적 셀은 일반적으로 4개의 NMOS 트랜지스터들과 2개의 PMOS 트랜지스터들로 이루어지는 CMOS 형태로 구성되어 있다.In general, an SRAM cell consists of four transistors (eg, two access transistors and two drive transistors) and two polysilicon load resistors or six transistors. In particular, 4M or higher integrated cells are generally configured in the form of CMOS, which consists of four NMOS transistors and two PMOS transistors.
이하, 첨부된 도면을 참조하여 종래의 에스램 셀의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional SRAM cell will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 에스램 셀의 제조방법을 나타낸 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional SRAM cell.
먼저, 도 1a에 도시한 바와 같이 반도체 기판(1)에 전도층을 증착하고 포토공정을 이용하여 게이트 라인(2)을 형성한 후, 에치백 공정을 이용하여상기 게이트 라인(2) 측면에 절연막 측벽(3)을 형성한다.First, as illustrated in FIG. 1A, a conductive layer is deposited on the semiconductor substrate 1, and a gate line 2 is formed by using a photo process, and then an insulating film is formed on the side of the gate line 2 using an etch back process. The side wall 3 is formed.
그리고 상기 게이트 라인(2)을 포함한 전면에 제 1 절연막(4)을 형성하고, 평탄화 공정을 이용하여 상기 제 1 절연막(4)상에 제 1 층간 절연막(5), 제 2 절연막(6) 및 제 2 층간 절연막(7)을 차례로 형성한다.A first insulating film 4 is formed on the entire surface including the gate line 2, and the first interlayer insulating film 5, the second insulating film 6, and the first insulating film 4 are formed on the first insulating film 4 using a planarization process. The second interlayer insulating film 7 is formed in sequence.
여기서, 상기 제 1 절연막(4)은 SRAM 등과 같은 디바이스(device)에서 불순물의 확산(diffiusion)을 방지하고 식각 공정 진행시 식각 저지층(stopping layer) 으로 사용하기 위해 SiON, SiN 등을 사용한다.Here, the first insulating layer 4 uses SiON, SiN, or the like to prevent diffusion of impurities in a device such as an SRAM and to use it as an etch stop layer during the etching process.
그리고 상기 제 2 절연막(6)은 디바이스 구조상 식각 공정 진행시 후속 단계에서 식각 저지층으로 사용하기 위해 SiON, SiN 등을 사용하고, 상기 제 1, 제 2 층간 절연막(5)(7)은 산화막을 사용한다.The second insulating film 6 uses SiON, SiN, or the like for use as an etch stop layer in a subsequent step during the etching process due to the device structure, and the first and second interlayer insulating films 5 and 7 are formed of an oxide film. use.
이어, 상기 제 2 층간 절연막(7)상에 포토레지스트를 증착한 후, 노광 및 현상공정을 이용하여 일정간격을 갖는 포토레지스트 패턴(PR)을 형성한다.Subsequently, after the photoresist is deposited on the second interlayer insulating layer 7, a photoresist pattern PR having a predetermined interval is formed using an exposure and development process.
도 1b에 도시한 바와 같이 상기 포토레지스트 패턴(PR)을 마스크로 이용하여 상기 제 2 층간 절연막(7) 및 제 2 절연막(6)을 선택적으로 제거한다.As shown in FIG. 1B, the second interlayer insulating film 7 and the second insulating film 6 are selectively removed using the photoresist pattern PR as a mask.
도 1c에 도시한 바와 같이 상기 포토레지스트 패턴(PR)을 마스크로 이용하여 상기 제 1 층간 절연막(5)을 선택적으로 제거한다.As illustrated in FIG. 1C, the first interlayer insulating layer 5 is selectively removed using the photoresist pattern PR as a mask.
도 1d에 도시한 바와 같이 상기 포토레지스트 패턴(PR)을 마스크로 이용하여 상기 제 1 절연막(4)을 선택적으로 제거하여 콘택홀()을 형성한다.As illustrated in FIG. 1D, the first insulating layer 4 is selectively removed using the photoresist pattern PR as a mask to form a contact hole.
따라서 식각 공정시 기판에 형성된 절연막 SiON, SiN에서 층간 절연막으로 사용된 산화막과의 선택비를 이용하여 식각 저지를 시킨 후, 다시 절연막으로 사용된 SiON, SiN를 식각한다.Therefore, after the etching process is performed using the selectivity of the insulating film SiON, SiN formed on the substrate to the oxide film used as the interlayer insulating film, the SiON and SiN used as the insulating film are etched again.
그러나 상기와 같은 종래의 에스램 셀의 제조방법에 있어서는 식각 저지로 사용될 절연막을 기판에 형성하고 층간 절연막 사이에 절연막을 형성하므로 멀티 식각(multi-step etch)공정이 실시되어 공정이 복잡하다.However, in the conventional manufacturing method of the SRAM cell as described above, since the insulating film to be used as an etch stop is formed on the substrate and the insulating film is formed between the interlayer insulating films, a multi-step etch process is performed and the process is complicated.
그리고 250nm 이상의 사이즈가 큰 콘택 형성시 식각 저지층으로 사용된 SiON, SiN의 식각 비율이 증가하여 식각공정을 적용시키지 못하는 문제점이 있었다.In addition, the etching rate of SiON and SiN used as an etch stop layer increases when forming a contact having a large size of 250 nm or more.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 사이즈가 큰 콘택 형성시 개구부의 탑 부위보다 하부를 감소시켜 콘택 사이즈에 따른 하부막질의 식각 비율을 개선 시키고, 공정의 단순화에 적당하도록 한 에스램 셀 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems to reduce the lower portion than the top portion of the opening when forming a large contact to improve the etching rate of the lower film quality according to the contact size, and to make it suitable for the simplification of the process It is an object of the present invention to provide a method for manufacturing a ram cell.
도 1a 내지 도 1d는 종래의 에스램 셀의 제조방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional SRAM cell.
도 2a 내지 도 2d는 본 발명의 에스램 셀의 제조방법을 나타낸 공정 단면도2A to 2D are cross-sectional views illustrating a method of manufacturing the SRAM cell of the present invention.
＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
21 : 반도체 기판 22 : 게이트 라인21 semiconductor substrate 22 gate line
23 : 절연막 측벽 24 : 제 1 절연막23 insulating film side wall 24 first insulating film
25 : 제 1 층간 절연막 26 : 제 2 절연막25: first interlayer insulating film 26: second insulating film
27 : 제 2 층간 절연막 28 : 콘택홀27: second interlayer insulating film 28: contact hole
상기와 같은 목적을 달성하기 위한 본 발명에 의한 에스램 셀 제조방법에 있어서, 반도체 기판에 게이트 라인과 상기 게이트 라인 측면에 절연막 측벽를 형성하는 단계와, 상기 게이트 라인를 포함한 전면에 식각 저지층을 형성하는 단계와, 상기 식각 저지층을 포함한 전면에 적어도 둘 이상의 절연막층을 순차적으로 형성하는 단계와, 상기 다수의 절연막층들중 최하부에 위치된 절연막을 제외한 절연막층들이 경사지도록 제 1 식각공정을 실시하는 단계와, 상기 다수의 절연막층의 최하부에 위치된 절연막층과 식각 저지층을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing an SRAM cell according to the present invention for achieving the above object, forming an insulating film sidewall on the side of the gate line and the gate line on the semiconductor substrate, and forming an etch stop layer on the entire surface including the gate line And sequentially forming at least two insulating layers on the entire surface including the etch stop layer, and performing a first etching process to incline the insulating layers except for the insulating layer positioned at the bottom of the plurality of insulating layers. And forming a contact hole by selectively removing the insulating layer and the etch stop layer positioned at the lowermost portions of the plurality of insulating layers.
이하, 첨부된 도면을 참조하여 본 발명의 에스램 셀의 제조방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing the SRAM cell of the present invention with reference to the accompanying drawings in more detail.
도 2a 내지 도 2d는 본 발명의 에스램 셀의 제조방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing the SRAM cell of the present invention.
먼저, 도 2a에 도시한 바와 같이 반도체 기판(21)에 액티브 영역과 필드영역을 정의한 후, 액티브 영역상에 전도층을 증착하고 패터닝하여 게이트 라인(22)을 형성하고 에치백 공정을 이용하여 상기 게이트 라인(22) 측면에 절연막 측벽(23)을 형성한다.First, as shown in FIG. 2A, an active region and a field region are defined in the semiconductor substrate 21, and then a conductive layer is deposited and patterned on the active region to form the gate line 22, and then, using the etch back process. An insulating film sidewall 23 is formed on the side of the gate line 22.
그리고 상기 게이트 라인(22)을 포함한 전면에 제 1 절연막(24)을 형성한 후, 상기 제 1 절연막(24)상에 평탄화 공정을 이용하여 제 1 층간 절연막(25)을 형성한다.After the first insulating film 24 is formed on the entire surface including the gate line 22, the first interlayer insulating film 25 is formed on the first insulating film 24 using a planarization process.
이어, 상기 제 1 층간 절연막(25)상에 제 2 절연막(26)과 제 2 층간 절연막(27)을 차례로 형성한 후, 상기 제 2 층간 절연막(27)상에 포토레지스트를 증착하고 노광 및 현상공정을 이용하여 일정간격을 갖는 포토레지스트 패턴(PR)을 형성한다.Subsequently, a second insulating film 26 and a second interlayer insulating film 27 are sequentially formed on the first interlayer insulating film 25, and then a photoresist is deposited on the second interlayer insulating film 27, followed by exposure and development. By using the process to form a photoresist pattern (PR) having a predetermined interval.
이때, 상기 제 1, 제 2 절연막(24)(26)은 식각 저지층으로 이용되고, SiON, SiN를 사용한다.In this case, the first and second insulating layers 24 and 26 are used as an etch stop layer, and SiON and SiN are used.
그리고 상기 제 1, 제 2 층간 절연막(25)(27)은 ILD(inter layer dielectric : 산화막)을 사용한다.The first and second interlayer insulating films 25 and 27 use an interlayer dielectric (ILD).
이어서, 도 2b에 도시한 바와 같이 상기 제 2 절연막(26)와 제 2 층간 절연막(27)와의 선택비가 낮은 조건을 통해 상기 포토레지스트 패턴(PR)을 마스크로 이용하여 상기 제 2 절연막(26), 제 2 층간 절연막(27)을 경사지도록 선택적으로 식각 제거한다.Subsequently, as shown in FIG. 2B, the second insulating layer 26 is formed by using the photoresist pattern PR as a mask under a condition where the selectivity between the second insulating layer 26 and the second interlayer insulating layer 27 is low. The second interlayer insulating layer 27 is selectively etched away so as to be inclined.
여기서, 콘택 사이즈가 250nm 이상으로 큰 경우 콘택 내부가 경사지도록 선택적으로 식각 제거하여 콘택 사이즈가 개구부의 탑 부위보다 하부 사이즈를 감소시킬 수 있다.In this case, when the contact size is larger than 250 nm, the contact size may be selectively etched away so that the inside of the contact is inclined so that the contact size may be lower than the top portion of the opening.
이때, 갖고자 하는 콘택 하부 사이즈에 도달하고자 일정 단차 동안 식각하고, 식각조건은 CHF₃, CO, O₂ 가스를 사용하며, O₂량은 0∼8sccm를 사용한다.At this time, to reach the contact lower size to be etched for a certain step, the etching conditions are used CHF₃, CO, O₂ gas, the amount of O₂ 0 ~ 8sccm is used.
그리고 O₂량을 2sccm 이하로 가져갈 때는 86° 이하로 프로파일(profile)을 콘트롤 할 수 있고, O₂량이 2sccm 이상인 경우 수직(vertical) 프로파일을 확보할 수 있다.And when the amount of O2 is less than 2sccm, the profile can be controlled to 86 ° or less, and when the amount of O2 is more than 2sccm, the vertical profile can be secured.
이어, 도 2c에 도시한 바와 같이 상기 포토레지스트 패턴(PR) 및 상기 제 2 절연막(26), 제 2 층간 절연막(27)을 마스크로 이용하여 상기 제 1 층간 절연막(25)을 선택적으로 식각 제거한다.Next, as illustrated in FIG. 2C, the first interlayer insulating layer 25 is selectively etched away using the photoresist pattern PR, the second insulating layer 26, and the second interlayer insulating layer 27 as a mask. do.
이때, 상기 제 1 절연막(24)과 상기 제 1 층간 절연막(25)와의 고선택비를 이용하며, 식각조건은 C4F8, Ar, O₂ 가스를 사용한다.In this case, a high selectivity ratio between the first insulating film 24 and the first interlayer insulating film 25 is used, and etching conditions include C 4 F 8 , Ar, and O 2 gases.
이와 같은 방법은 보드리스 콘택(borderless contact) 구조나 평범한 콘택(normal contact) 구조에서 식각량의 증가시 기판층의 소비를 최소화 시킬 수 있다.This method can minimize the consumption of the substrate layer when the etching amount is increased in the boardless contact structure or the normal contact structure.
이어서, 도 2d에 도시한 바와 같이 상기 포토레지스트 패턴(PR)과 상기 제 2 층간 절연막(25)을 마스크로 이용하여 상기 제 1 절연막(24)을 선택적으로 제거하여 콘택홀(28)을 형성한다.Subsequently, as illustrated in FIG. 2D, the first insulating layer 24 is selectively removed using the photoresist pattern PR and the second interlayer insulating layer 25 as a mask to form a contact hole 28. .
이상에서 설명한 바와 같이 본 발명의 에스램 셀의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of manufacturing the SRAM cell of the present invention has the following effects.
첫째, 기판상에 식각 저지층이 없을 경우 2번의 식각공정 만으로도 적용가능 하므로 공정을 단순화 시킬 수 있다.First, if there is no etch stop layer on the substrate can be applied only by two etching process can simplify the process.
둘째, 콘택 사이즈가 커질수록 식각 저지층의 선택비가 증가되는 프로세스(process)시 저 선택비 및 고 선택비를 이용하여 사이즈가 작은 패턴을 형성할 수 있어 식각 저지층으로 사용되는 SiON, SiN의 식각 비율를 개선 시킬 수 있다.Second, in the process of increasing the selectivity of the etch stop layer as the contact size increases, etching patterns of SiON and SiN used as the etch stop layer can be formed by using a low selectivity and a high selectivity. The ratio can be improved.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045161A KR20010037576A (en) | 1999-10-18 | 1999-10-18 | method of manufacturing in SRAM cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045161A KR20010037576A (en) | 1999-10-18 | 1999-10-18 | method of manufacturing in SRAM cell |
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| KR20010037576A true KR20010037576A (en) | 2001-05-15 |
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| KR1019990045161A KR20010037576A (en) | 1999-10-18 | 1999-10-18 | method of manufacturing in SRAM cell |
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| KR (1) | KR20010037576A (en) |
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1999
- 1999-10-18 KR KR1019990045161A patent/KR20010037576A/en not_active Application Discontinuation
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