KR20010025653A - Termination structure for chip and fabricating method therefor - Google Patents
Termination structure for chip and fabricating method therefor Download PDFInfo
- Publication number
- KR20010025653A KR20010025653A KR1020010002125A KR20010002125A KR20010025653A KR 20010025653 A KR20010025653 A KR 20010025653A KR 1020010002125 A KR1020010002125 A KR 1020010002125A KR 20010002125 A KR20010002125 A KR 20010002125A KR 20010025653 A KR20010025653 A KR 20010025653A
- Authority
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- South Korea
- Prior art keywords
- chip
- external terminal
- chip component
- terminal electrode
- electrode
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 10
- 229910052718 tin Inorganic materials 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229910052709 silver Inorganic materials 0.000 claims abstract description 12
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 11
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 10
- 238000000465 moulding Methods 0.000 claims abstract description 5
- 239000002002 slurry Substances 0.000 claims abstract description 4
- 239000002003 electrode paste Substances 0.000 claims abstract 3
- 238000007747 plating Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 abstract description 9
- 238000002386 leaching Methods 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000000740 bleeding effect Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- WMWLMWRWZQELOS-UHFFFAOYSA-N bismuth(iii) oxide Chemical compound O=[Bi]O[Bi]=O WMWLMWRWZQELOS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910002637 Pr6O11 Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000005456 alcohol based solvent Substances 0.000 description 1
- 238000000498 ball milling Methods 0.000 description 1
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(II) oxide Inorganic materials [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- VASIZKWUTCETSD-UHFFFAOYSA-N manganese(II) oxide Inorganic materials [Mn]=O VASIZKWUTCETSD-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
- H01C1/1406—Terminals or electrodes formed on resistive elements having positive temperature coefficient
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
- H01C1/1413—Terminals or electrodes formed on resistive elements having negative temperature coefficient
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
- H01C17/281—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thick film techniques
- H01C17/283—Precursor compositions therefor, e.g. pastes, inks, glass frits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
본원 발명은 칩부품을 PCB(Printed Circuit Board) 등에 부착한 후 납땜(Soldering)시 발생되는 외부단자전극(Termination)의 식은(Leaching) 현상을 방지하고 완벽한 납땜성(Solderability)을 부여하기 위하여 칩부품의 외부단자전극을 특수하게 설계하여 우수한 납땜성을 갖는 외부단자전극 및 이를 제조하는 방법에 관한 것이다.The present invention is to attach the chip component to the PCB (Printed Circuit Board), etc. and then to prevent the phenomenon of the terminal terminal (Leaching) generated when soldering (Soldering) and to give the perfect solderability (Solderability) By specially designing the external terminal electrode of the present invention relates to an external terminal electrode having excellent solderability and a method of manufacturing the same.
일반적으로 표면 실장형 칩부품 들은 칩의 양 끝단에 양쪽 외부단자전극이 형성되어 있고 칩부품의 외부단자전극과 PCB 기판을 땜납(Solder Cream)을 이용하여 납땜한다. 칩부품의 외부단자전극은 주로 도전체 단자전극물질을 도포하여 형성한다. 외부단자전극으로 은(Ag)을 사용하는 경우 도1과 같이 내부전극(11)이 형성된 적층체(12)를 제조한 후 은 페이스트(Paste)를 이용하여 은 외부단자전극(13)을 형성한다. 이때 외부단자전극이 형성된 칩부품을 기판에 납땜하기 위해서는 식은 현상을 방지하기 위해 순수한 은으로만 외부단자전극을 형성한 경우 반드시 니켈(Ni)층(14)을 도금한 후 니켈층 위에 주석(Sn)이나 주석/납(Sn/Pb)층(15)을 도금한다. 이는 땜납 성분이 Sn/Pb이므로 외부단자전극에 Sn이나 Sn/Pb층을 도금하여야 땜납 성분과 서로 융착되어 납땜성이 향상되며, Sn이나 Sn/Pb층과 Ag층 사이에 Ni층을 도금하지 않으면 납땜시에 외부단자전극 물질인 Ag가 같이 용융되어 PCB 기판쪽으로 이동하여 단자전극이 없어지는 식은 현상이 발생하기 때문이다. 즉, Ni층은 바깥쪽의 Sn이나 Sn/Pb층이 땜납과 같이 용융되어 칩부품이 PCB 기판과 완벽한 납땜을 이룰 때 안쪽의 Ag 금속이 같이 용융되어 녹아나가는 것을 방지하는 역할을 한다. 이러한 Ni 및 Sn이나 Sn/Pb층이 도금된 외부단자전극은 칩부품의 납땜 특성을 향상시킴으로 인해 대부분의 칩부품 업체들이 선호하는 구조이며 또한 대부분의 세트 업체에서도 도1과 같이 도금된 칩을 요구하고 있다. 칩부품의 도금은 일반적으로 전해도금법을 이용하는데 이는 외부단자전극이 도전성이기 때문에 외부단자전극만이 선택적으로 도금되기 때문이다. 즉, 전기를 통하는 부분만 도금이 되는 전해도금의 원리를 이용한 것이다. 그러나 칩배리스터와 같이 저항이 낮은 물질인 경우 Ni층 및 Sn 또는 Sn/Pb층을 칩부품의 외부단자전극에 도금시 일반적으로 세라믹 소체로 이루어진 칩부품 본체 부분의 낮은 저항으로 인해 외부단자전극뿐만 아니라 세라믹 소체도 부분적으로 도금이 되는 문제점이 있다. 도금 번짐 현상은 특히 Ni층의 도금시에 심하게 발생하며, 상대적으로 Sn층이나 Sn/Pb층의 도금시에는 도금 번짐 현상이 경미하나 Ni층의 도금시에 이미 번져버린 Ni 도금 번짐층 위에 Sn이나 Sn/Pb층이 쉽게 도금된다. 칩부품의 경우 도금층 형성시 외부단자전극뿐만 아니라 외부단자전극 사이의 세라믹 소체의 표면에 도금층이 형성되면 전기적 불량품이 발생한다. 이러한 외부단자전극 도금시 발생하는 도금 번짐 현상을 해결하기 위하여 부품업체 특히 칩 배리스터 업체에서 다양한 방법으로 도금을 시도하고 있으나 수율이 떨어지는 등 많은 문제점을 야기시키고 있다.In general, surface-mount chip components have both external terminal electrodes formed at both ends of the chip, and solder the external terminal electrodes of the chip component and the PCB board using solder cream. The external terminal electrode of the chip component is mainly formed by applying a conductor terminal electrode material. In the case of using silver (Ag) as the external terminal electrode, as shown in FIG. 1, after the laminate 12 having the internal electrode 11 is formed, the silver external terminal electrode 13 is formed by using a silver paste. . In this case, in order to solder the chip component having the external terminal electrode formed on the substrate, in order to prevent the cooling phenomenon, when the external terminal electrode is formed of pure silver only, the nickel (14) layer must be plated, and then the tin (Sn) layer is formed on the nickel layer. ) Or tin / lead (Sn / Pb) layer 15 is plated. Since the solder component is Sn / Pb, the Sn or Sn / Pb layer should be plated on the external terminal electrode to be fused with the solder component to improve solderability, and if the Ni layer is not plated between the Sn or Sn / Pb layer and the Ag layer, This is because, when soldering, Ag, which is an external terminal electrode material, melts together and moves toward the PCB substrate, thereby eliminating the terminal electrode. That is, the Ni layer serves to prevent the inner Sn metal from melting and melting when the outer Sn or Sn / Pb layer is melted like solder and the chip component is completely soldered to the PCB substrate. The external terminal electrode plated with Ni, Sn, or Sn / Pb layer is preferred by most chip parts makers because of improved soldering characteristics of chip parts. Also, most set companies require a plated chip as shown in FIG. Doing. The plating of chip components is generally performed by electroplating, since only the external terminal electrodes are selectively plated since the external terminal electrodes are conductive. That is, it uses the principle of electroplating in which only the part through electricity is plated. However, in the case of a low resistance material such as a chip varistor, when the Ni layer and the Sn or Sn / Pb layer are plated on the external terminal electrode of the chip component, the external terminal electrode is not only formed due to the low resistance of the main part of the chip component which is generally made of ceramic element. Ceramic bodies also have a problem of being partially plated. Plating bleeding phenomenon occurs especially when plating Ni layer, and relatively plating bleeding phenomenon when Sn layer or Sn / Pb layer is plated, but Sn The Sn / Pb layer is easily plated. In the case of a chip component, when a plating layer is formed on the surface of a ceramic element between an external terminal electrode as well as an external terminal electrode, an electrical defect occurs. In order to solve the plating bleeding phenomenon occurring during the external terminal electrode plating, component manufacturers, in particular, chip varistor manufacturers are attempting plating by various methods, but it causes many problems such as poor yield.
또한 다른 종래 기술은 도2와 같이 칩부품의 외부단자전극(23)으로 Ag 금속에 소량의 팔라듐(Pd)이나 백금(Pt)을 섞은 물질을 사용한다. Ag에 소량의 Pd나 Pt를 첨가한 물질로 외부단자전극을 형성하는 경우 Ni이나 Sn등의 별도의 도금 공정이 없이도 칩부품의 PCB 기판에의 실장이 가능하다. 이는 Ag 금속에 소량의 Pd나 Pt금속을 첨가하면 납땜시 Ag 금속이 땜납과 반응하나 Pd나 Pt 금속이 Ag의 식은(Leaching)현상을 막아주기 때문이다. 그러나 이러한 외부단자전극은 납땜 성능이 떨어진다. Pd나 Pt를 첨가한 Ag 금속으로 외부단자전극을 제조한 칩부품(31)을 PCB 기판(33)과 납땜하는 경우 납땜성이 떨어지므로 도3과 같이 랜드(34) 위의 땜납(35)이 외부단자전극(32)과 완전히 융착되지 않아 PCB 기판과 제대로 납땜이 되지 않는 문제점이 있다.In addition, another conventional technique uses a material in which a small amount of palladium (Pd) or platinum (Pt) is mixed with Ag metal as the external terminal electrode 23 of the chip component as shown in FIG. When the external terminal electrode is made of a material in which a small amount of Pd or Pt is added to Ag, the chip component can be mounted on the PCB substrate without a separate plating process such as Ni or Sn. This is because if a small amount of Pd or Pt metal is added to the Ag metal, the Ag metal reacts with the solder during soldering, but the Pd or Pt metal prevents Aging from leaking. However, these external terminal electrodes have poor soldering performance. When soldering the chip component 31 fabricated from the Pd or Pt-added Ag terminal electrode with the PCB substrate 33, the solderability is poor, so that the solder 35 on the land 34 as shown in FIG. Since the external terminal electrode 32 is not completely fused, there is a problem in that the PCB is not properly soldered.
상술한 바와 같은 종래의 문제점들을 해결하기 위한 본 발명의 목적은 외부단자전극물질 및 구조를 조정하여 외부단자전극 금속(Ag)의 식은 현상이 없으면서도 우수한 납땜성을 갖는 칩부품의 외부단자전극을 제조하는 데 있다.An object of the present invention for solving the conventional problems as described above is to adjust the external terminal electrode material and structure to provide an external terminal electrode of the chip component having excellent solderability without cooling the external terminal electrode metal (Ag). To manufacture.
본 발명의 다른 목적은 외부단자전극물질 및 구조를 조정하여 외부단자전극의 도금시에 발생하는 도금 번짐 현상을 제거하는 데 본 발명의 목적이 있다.Another object of the present invention is to adjust the external terminal electrode material and structure to eliminate the plating bleeding phenomenon occurring during the plating of the external terminal electrode.
도 1 종래의 도금 칩부품의 외부단자전극 모식도1 is a schematic diagram of an external terminal electrode of a conventional plating chip component
도 2 종래의 비도금 칩부품의 외부단자전극 모식도2 is a schematic diagram of an external terminal electrode of a conventional non-plated chip component.
도 3 납땜성이 부족한 칩부품의 납땜 모식도3 is a schematic diagram of soldering of a chip component having poor solderability.
도 4 본 발명에 의한 칩부품의 외부단자전극 모식도4 is a schematic diagram of an external terminal electrode of a chip component according to the present invention.
상술한 바와 같은 목적을 해결하기 위한 본 발명에 따른 칩부품의 외부단자전극은 외부단자전극 물질로 Ag/Pd, Ag/Pt 혹은 Ag/Pd/Pt계 페이스트(Paste)를 사용하여 단자전극을 형성하고 그 위에 Sn 혹은 Sn/Pb층을 도금하여 2중층으로 내부 전극과 연결되는 외부단자전극을 형성하여 제조한다.In order to solve the above object, the external terminal electrode of the chip component according to the present invention forms a terminal electrode using Ag / Pd, Ag / Pt or Ag / Pd / Pt-based paste as an external terminal electrode material. Then, the Sn or Sn / Pb layer is plated thereon to prepare an external terminal electrode connected to the internal electrode in a double layer.
본 발명에 따른 외부단자전극의 제조에 관하여 적층형 칩배리스터 부품을 예로 하기에서 보다 상세하게 살펴본다.With respect to the manufacture of the external terminal electrode according to the present invention will be described in more detail as an example of a stacked chip varistor component.
공업용으로 시판하고 있는 적층형 칩 배리스터 소자의 원료 분말을 이용하거나 ZnO 분말에 Bi2O3, Pr6O11, CoO, MnO 등의 첨가제를 넣은 원하는 조성에 물 또는 알코올 등을 용매로 24시간 볼밀(Ball Mill)하여 원료분말을 준비한다. 성형 시트를 준비하기 위해 상기 준비된 배리스터용 분말에 첨가제로 PVB계 바인더(Binder)를 원료 분말 대비 약 8wt% 정도 칙량한 후 톨루엔/알코올(Toluene/Alcohol)계 솔벤트(Solvent)에 용해시켜 투입한 후 소형 볼 밀(Ball mill)로 약 24시간 동안 밀링(Milling) 및 혼합하여 슬러리(Slurry)를 제조하고, 이러한 슬러리를 닥터 블레이드(Doctor blade)등의 방법으로 원하는 두께의 성형 시트(41, Green sheet)로 제조한다.Raw powder by using a raw material powder of a commercially available stacked chip varistor device commercially or by ball milling water or alcohol with a solvent in a desired composition in which an additive such as Bi2O3, Pr6O11, CoO, MnO is added to ZnO powder Prepare. In order to prepare a molding sheet, PVB-based binder (Vinder) is added to the prepared varistor powder as an additive about 8wt% of the raw material powder, dissolved in toluene / alcohol-based solvent, and then added. A slurry is prepared by milling and mixing for about 24 hours in a small ball mill, and forming the slurry into a desired thickness of a sheet by using a doctor blade or the like. To manufacture).
제조된 시트 위에 내부전극 패턴의 스크린을 이용하여 스크린 프린팅(Screen printing) 방법으로 내부전극(42)을 인쇄한다. 이때 내부전극은 Ag, Pt, 혹은 Pd 페이스트를 이용하여 인쇄한다.The internal electrode 42 is printed by a screen printing method using a screen of the internal electrode pattern on the manufactured sheet. At this time, the internal electrode is printed using Ag, Pt, or Pd paste.
상기와 같이 내부전극이 인쇄된 시트를 원하는 수만큼 적층한 후 적층물(43) 내의 각종 바인더 성분을 모두 제거하기 위하여 400℃에서 6시간 정도 가열하여 베이크 아웃(Bake-out)시킨 후 온도를 상승시켜 배리스터 조성의 소성온도에서 적층물을 소성한다.After stacking the sheets printed with the internal electrodes as desired as described above, in order to remove all the binder components in the laminate 43, the substrate was heated at 400 ° C. for about 6 hours to bake out and then the temperature was increased. The laminate is fired at the firing temperature of the varistor composition.
소성된 적층물(43)의 외부에 적층물의 내부전극과 연결되는 외부단자전극(44, Termination)을 형성하여 배리스터 소자를 제조한다. 즉, 양쪽 측면의 제1 외부단자전극(45)은 칩 배리스터 적층물의 양쪽 끝단을 Ag/Pd, Ap/Pt 혹은 Ag/Pd/Pt계 페이스트가 도포된 베드(Bed) 위에 디핑(Dipping)하여 아령 모양으로 형성한 후, 적당한 온도에서 소성한다. 형성된 제1 외부단자전극 위에 전해도금방법을 이용하여 도 2와 같이 Sn 혹은 Sn/Pb층(46)을 외부단자전극에만 선택적으로 도금하여 표면 실장형 칩 배리스터를 제조한다.A varistor device is manufactured by forming an external terminal electrode 44 connected to the internal electrodes of the laminate on the outside of the fired laminate 43. That is, the first external terminal electrodes 45 on both sides of the dumbbells are formed by dipping both ends of the chip varistor stack onto a bed coated with Ag / Pd, Ap / Pt, or Ag / Pd / Pt-based paste. After forming into a shape, it is baked at an appropriate temperature. A surface-mounted chip varistor is manufactured by selectively plating a Sn or Sn / Pb layer 46 only on the external terminal electrode using the electroplating method on the formed first external terminal electrode.
상기한 바와 같이 외부단자전극을 제조하는 기술은 상기의 예시된 소자 외에 여러 가지 칩부품의 외부단자전극으로 제조할 수 있다. 특히 저항이 낮은 물질의 칩부품의 경우 도금 번짐성을 방지하면서도 우수한 납땜성을 가지는 외부단자전극을 제조할 수 있다.As described above, the technique of manufacturing the external terminal electrode may be manufactured by external terminal electrodes of various chip components in addition to the above-described device. In particular, in the case of a chip component having a low resistance material, an external terminal electrode having excellent solderability while preventing plating bleeding may be manufactured.
상술한 바와 같은 본 발명에 따른 외부단자전극의 구조로 제조된 단자전극은 Ni층이 없이도 Ag금속의 식은 현상을 방지하며 우수한 납땜성을 얻을 수 있는 효과가 있으며, 또한 도금시 발생하는 도금 번짐 현상을 제거하는 효과가 있다.The terminal electrode manufactured by the structure of the external terminal electrode according to the present invention as described above has the effect of preventing the cooling of Ag metal and obtaining excellent solderability even without a Ni layer, and also the plating bleeding phenomenon generated during plating. Has the effect of removing.
본 발명에 따라 제조된 칩부품의 외부단자전극은 단순한 이중층 구조로 별도의 공정 추가 없이 단순한 공정에 의해 원하는 전기적 특성을 구현하는 경박 단소화된 소형의 칩 부품 소자를 제조할 수 있으며, 단순한 공정에 의한 외부단자전극의 제조로 제조 원가를 저감하는 효과가 있다.The external terminal electrode of the chip component manufactured according to the present invention has a simple double layer structure and can manufacture a thin and small and small chip component device that realizes desired electrical characteristics by a simple process without adding a separate process. The manufacturing cost of the external terminal electrode can be reduced.
또한 본 발명에 따라 칩부품의 외부단자전극을 제조함으로 PCB 기판에의 실장 효율을 향상시키며, 칩부품의 표면에 도금 번짐 현상을 방지함으로 칩부품의 전기적 특성을 안정적으로 얻을 수 있는 효과가 있다.In addition, according to the present invention, the external terminal electrode of the chip component is manufactured, thereby improving the mounting efficiency on the PCB substrate, and preventing the plating bleeding phenomenon on the surface of the chip component, thereby stably obtaining the electrical characteristics of the chip component.
Claims (7)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002125A KR20010025653A (en) | 2001-01-15 | 2001-01-15 | Termination structure for chip and fabricating method therefor |
| PCT/KR2002/000061 WO2002056654A1 (en) | 2001-01-15 | 2002-01-15 | Terminal for chip and fabricating method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002125A KR20010025653A (en) | 2001-01-15 | 2001-01-15 | Termination structure for chip and fabricating method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400606B1 (en) * | 2001-09-08 | 2003-10-08 | 정재필 | Double pre-coated substrate using lead free solder plated with low-melting-pointed alloy and manufacturing method thereof |
| KR20040045769A (en) * | 2002-11-25 | 2004-06-02 | 삼성전기주식회사 | Low Temperature Co-fired Ceramic Multi-laminated board enhancing a force of soldering |
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| JPH0575238A (en) * | 1991-03-06 | 1993-03-26 | Nau Chem:Yugen | Circuit board and its manufacture |
| JPH08293654A (en) * | 1995-04-21 | 1996-11-05 | World Metal:Kk | Formation of metal film on ceramic base material and metal-coated ceramic structure |
| JP3344295B2 (en) * | 1997-09-25 | 2002-11-11 | イビデン株式会社 | Solder members and printed wiring boards |
| JP3436101B2 (en) * | 1997-09-26 | 2003-08-11 | イビデン株式会社 | Solder material, printed wiring board and method of manufacturing the same |
| JP3252757B2 (en) * | 1997-06-04 | 2002-02-04 | イビデン株式会社 | Ball grid array |
| JP3341648B2 (en) * | 1997-09-26 | 2002-11-05 | イビデン株式会社 | Printed wiring board |
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2001
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400606B1 (en) * | 2001-09-08 | 2003-10-08 | 정재필 | Double pre-coated substrate using lead free solder plated with low-melting-pointed alloy and manufacturing method thereof |
| KR20040045769A (en) * | 2002-11-25 | 2004-06-02 | 삼성전기주식회사 | Low Temperature Co-fired Ceramic Multi-laminated board enhancing a force of soldering |
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| WO2002056654A1 (en) | 2002-07-18 |
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