KR20010015232A - Gradation display arrangments of plasma display panel and the method thereof - Google Patents

Abstract

PURPOSE: An apparatus for processing gradation display of a plasma display panel and processing method thereof is provided to prevent reduction of gradation of red(R) signal and green(G) signal each whose brightness is dark. CONSTITUTION: A level controller(11A) compresses level for input video signal in band of the input video signal above a predetermined level. An A/D converter(12) A/D converts the input video signal having the level compressed video signal and outputs it as a digital video signal. A 9 bit data generator(13) expands level of the digital video signal corresponding to the level compressed input video signal band of the A/D converted digital video signals by the A/D converter. An apparatus for processing gradation display of a plasma display panel displays the level expanded digital video signal and the A/D converted digital video signal on the plasma display panel(101).

Description

Gradient display processing apparatus of plasma display panel and its processing method {GRADATION DISPLAY ARRANGMENTS OF PLASMA DISPLAY PANEL AND THE METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing apparatus and a method for gradation of a plasma display panel used for video display such as a TV or an advertisement display panel.

In the plasma display panel (hereinafter referred to as PDP), the luminance control method of performing gradation display for image display, as shown in Fig. 2, has a predetermined weighting display luminance within one field period of 1/60 second. ) Is used to install a plurality of subfields SF1, SF2, SF3, ... SF8. Each subfield is divided into a write period for writing discharge of display data, a sustain period for display discharge, and an erasing period for ending sustain discharge, respectively. In the example of FIG. 2, eight subfields SF1, SF2, ... SF8 are provided in one field. The length of each subfield period varies depending on the luminance value (weight, weight).

For example, if the luminance at the time of light emission in each subfield SF1, SF2, ... SF8 is corrected to 20xB0 (B0 = reference luminance), 21xB0, ..., 27xB0, respectively, The emission periods in the subfields SF1, SF2, ..., SF8 are 1 in SF1, 2 in SF2, 4 in SF3, 8 in SF4, 16 in SF5, 32 in SF6, 64 in SF7, and 128 in SF8. The combination of these light emission displays 28 = 256 gray scales.

Such luminance control is realized by the driving circuit of FIG.

In Fig. 1, the PDP unit 100 adopts the AC type, and the PDP 1 is paired with data electrodes D1, D2, D3, ... D8 in the M column and in each row of the N rows. Scan electrodes SC1, SC2, SC3, ..., SCN, sustain electrodes SU1, SU2, SU3, ... SUN are arranged in a matrix.

Further, the PDP unit 100 includes a data driver 102 for driving data electrodes D1, D2, D3, ... DM in column M, and scan electrodes SC1, SC2, SC3, ... SCN and sustain electrodes SU1, SU2. , SU3, ... A scanning, holding and erasing driver 103 for driving the SUN is provided.

As the driving unit for driving the PDP unit 100, as shown in Fig. 1, the level adjusting unit 11, the A / D conversion unit 12, the flame memory 14, the output processing unit 15, and the synchronization separating unit ( 16, a timing pulse generator 17, a memory controller 18 and a drive timing generator 19 are provided.

Next, the flow of signals for driving this PDP unit 100 will be described briefly.

The magnitude of the input signal a representing the input video signal is adjusted by the level adjuster 11 and input to the 8-bit A / D converter 12. The output of the A / D converter 12 is once stored in the flame memory 14 to drive the data driver 102 via the output processor 15.

On the other hand, the timing pulse generator 17 is driven from the input signal a through the synchronization separator 16. The A / D converter 12 is controlled by the output of the timing pulse generator 17, and the memory controller 18 and the drive timing generator 19 are controlled.

Then, the scanning, holding and erasing driver 103 is driven based on the output of the driving timing generating unit 19. The output of the drive timing generator 19 is fed back to the memory controller 18.

The memory controller 18 operates in synchronism with both output signals of the timing pulse generator 17 and the drive timing generator 19, and accordingly the data driver (from the flame memory 14 via the output processor 15) In order to drive 102, control of reading and writing of the frame memory 13 is performed.

Next, the level adjustment of the input signal a will be described.

3 shows a time variation diagram of an input signal of a general TV display. The input signal a is roughly divided into an input signal of average signal level, a maximum input signal of level B which frequently appears, and a peak input signal of level A which sometimes appears. Now, when the signal level input to the A / D converter 12 by the level adjusting unit 11 in FIG. 1 is adjusted to level A (peak input) in FIG. 3, the signal up to level A (peak input) is adjusted. The digital signals are all converted by the 8-bit A / D converter 12. Therefore, as shown in Fig. 4, 56 gray levels are displayed for all the input signals up to the peak luminance corresponding to the peak input. That is, the change in the input signal is displayed on the PDP 101 as a change in luminance as shown in FIG.

In general, in the PDP, the luminous efficiency of each signal of the red (R) signal, the green (G) signal, and the blue (B) signal constituting the input video signal is not equal. For this reason, the color temperature at the time of displaying a white signal becomes a value very low about 6,000 degree | times compared with 11,000 degree | times realized by a CRT.

When the luminous efficiency of each signal of the red (R) signal, the green (G) signal, and the blue (B) signal is corrected by the electric signal in the PDP apparatus, the A / D converter 12 shown in FIG. In the level adjusting unit 11 arranged at the front end of the step), the voltage level is adjusted in accordance with each signal of the red (R) signal, the green (G) signal, and the blue (B) signal. In this case, when the blue (B) signal with bright brightness is adjusted to a voltage level corresponding to, for example, the output value "256" (i.e., 256 gray levels) of the A / D converter 12, the red (B) brightness is low. The level of the R) signal and the green (G) signal is lowered to a voltage level corresponding to the output values "130" to "150" of the A / D converter 12, and as a result, about 1677, which is the original display color number of the PDP. In the case of the PDP in which the color temperature is adjusted to the CRT level for all colors, there is a problem that the number of display colors is considerably reduced as about 5.4 million colors.

Accordingly, an object of the present invention is to increase the number of display colors by suppressing a decrease in the gray levels of red (R) and green (G) signals having low luminance in the PDP.

In order to solve this problem, the present invention, when the video signal is input, converts the input video signal into a digital video signal of a predetermined gray scale, and also displays the converted digital video signal on the plasma display panel A gradation display processing apparatus comprising: a level adjusting section, an A / D converting section, and a level extending section, wherein the level adjusting section level-compresses an input video signal in an input video signal band of a predetermined level or more, and the A / D converting section A / D-converts the input video signal including the level-compressed video signal and outputs it as a digital video signal, and the level extension unit is a digital video corresponding to the level-compressed input video signal band of the A / D converted digital video signal. The feature is to level up the signal.

In this case, the level adjusting unit increases the level so that the number of gradations increases during A / D conversion by the A / D converter for an input video signal of an input video signal band of a predetermined level or less.

In addition, the present invention provides a step of level-compressing an input video signal of an input video signal band of a predetermined level or more, A / D-converting an input video signal including a level-compressed video signal, and outputting the digital video signal; A method of level expanding a digital video signal corresponding to a level-compressed input video signal band is provided.

1 is a block diagram showing a conventional PDP apparatus.

2 is a diagram showing gradation display timing of a conventional PDP apparatus;

3 is a view showing an input signal situation in a conventional PDP apparatus.

4 is a diagram showing a relationship between an input signal and an output signal for a PDP in the conventional PDP apparatus.

Fig. 5 is a diagram showing a situation of display input signals to a conventional PDP.

6 is a block diagram showing the configuration of a PDP apparatus to which the present invention is applied.

Fig. 7 is a diagram showing gradation display timing in the PDP apparatus.

Fig. 8 is a diagram showing the level adjustment of an input signal in the PDP apparatus and the relationship between the level-adjusted input signal and gradation display.

** Description of the symbols for the main parts of the drawings **

11A: level adjuster 12: A / D converter

13: 9-bit data generation unit 14: flame memory

15: output processing section 16: synchronous separation section

17: timing pulse generator 18: memory controller

19: drive timing generator

100: plasma display panel unit

101: plasma display panel (PDP)

102: data driver

a: Input signal (input video signal)

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated with reference to drawings.

Fig. 6 is a block diagram showing the configuration of a PDP apparatus to which the present invention is applied, in which the PDP unit 100 constituting the apparatus is scanned in pairs in each row of N rows with data electrodes D1, ... DM in M columns. PDP 101 having electrodes SC1, ... SCN / sustaining electrodes SU1, ... SUN formed in a matrix, data driver 102 for driving the data electrodes in column M, and scan / hold electrode pairs in the N rows. It is an AC type adaptation comprised by each element of the scanning, holding, and erasing driver 103 which drives the motor.

In the PDP apparatus, a driving unit for driving the PDP unit 100 includes a level adjusting unit 11A, an A / D converter 12, a 9-bit data generator 13, a flame memory 14, and an output processor 15. ), A synchronization separator 16, a timing pulse generator 17, a memory controller 18 and a drive timing generator 19 are provided.

Next, the flow of signals for driving the PDP unit 100 shown in FIG. 6 will be briefly described.

The magnitude of the input signal a representing the input video signal is adjusted by the level adjusting section 11A and is once input to the 8-bit A / D converter section 12. Here, when the output value of the A / D conversion part 12 exceeds the preset value, it is written by the 9-bit data generation part 13 into 9-bit data which added 1 bit. The output from the 9-bit data generation unit 13 is once stored in the flame memory 14 and drives the data driver 102 via the output processing unit 15.

On the other hand, the timing pulse generator 17 is driven from the input signal a through the synchronization separator 16. The A / D converter 12 is controlled by the output of the timing pulse generator 17, and the memory controller 18 and the drive timing generator 19 are controlled. The output of the drive timing generator 19 is fed back to the memory controller 18 while the scan, sustain and erase driver 103 is driven by the output of the drive timing generator 19. The memory control unit 18 operates in synchronization with both output signals of the timing pulse generator 17 and the drive timing generator 19, and accordingly, is output from the flame memory 14 via the output processor 15. The frame memory 13 for driving the data driver 102 is controlled for reading and writing.

In the PDP apparatus of FIG. 6, the method of performing gradation display for TV display includes eight subfields SF1 to SF8, which have been weighted in display luminance within one field period of 1/60 second, as shown in FIG. This is realized by providing one subfield SF9 that performs independent luminance display. In the example shown in Fig. 7, the unit subfields SF1, SF2, ... SF8, SF9 each have a period of write periods for write discharges of display data, sustain periods for display discharges, and erase periods for ending sustain discharges. Nine subfields of are provided in one field. The length of the sustain period of each subfield of SF1 to SF9 varies depending on the luminance value (weight, weight), and is corrected to the luminance ratios 1, 2, 4, 8, 16, 32, 64, 128, 128, respectively. .

In general, the human eye has a characteristic that the sensitivity to the gray level when the brightness is bright is lower than the sensitivity when the brightness is dark. In view of the characteristics of the human eye, the present invention reduces the gray level of a signal (i.e., a blue signal) of a bright part by compression of the signal level, and reduces the amount of the signal (i.e., green) of a dark part of the brightness. By dividing by the gray level of the signal and the red signal, it is possible to suppress the decrease of the gray level of the signal in the dark part of the luminance and to increase the number of display colors.

By the way, the level adjuster 11 of the conventional PDP apparatus shown in FIG. 1 has a linear characteristic of outputting a signal matched to the level of the input signal a to the A / D converter 12 as it is, and an A / D converter. In Fig. 12, the relationship between the input signal outputted from the level adjusting section 11 and the input signal thereof and the output signal outputted by the self (i.e., A / D output) has a linear characteristic as shown in FIG.

Here, in order to reduce the gradation of the signal of the bright part and divide it into the dark part, the level adjusting characteristic of the level adjusting part 11A of FIG. 6 is a linear characteristic as shown by the first straight line L1 and the second straight line L2 of FIG. do.

That is, when the input adjuster 11A inputs the input signal a, the low level signal (i.e., dark green G signal) with a level ranging from 0 to 50% is bounded by the 50% level of the maximum input level. For the red (R) signal, the level is adjusted along the first straight line L1 having a large inclination so as to convert the input signal into 384 gradations, and is output to the A / D converter 12. In addition, for the high level signal (i.e., the blue (B) signal with bright brightness) having an input signal a level of 50% to 100%, the level is adjusted along the second straight line L2 having a small inclination, and the A / D converter ( Output to 12). That is, for the high level where the level of the input signal is 50% or more, the level is compressed and output to the A / D converter 12.

The A / D converter 12 converts an input signal into an 8-bit digital value to perform 256 gray scale display. When the level of the input signal is 0% to 50%, the input signal is the level adjusting unit 11A. By leveling up, the digital conversion is performed so as to display 384 gradations (corresponding to nine subfields), and the digital conversion value is output to the 9-bit data generation unit 13. When the level of the input signal reaches 50%, 192 (384/2) is output as the digital conversion value.

In addition, when the level of the signal from the level adjusting section 11A is 50% to 100%, the A / D converter 12 performs digital conversion of the input signal level-compressed by the level adjusting section 11A. The digital conversion value is output to the 9-bit data generation unit 13. Here, when the level of the input signal is 50%, for example, the digital conversion value 192 is outputted to the 9-bit data generator 13, while when the level of the input signal reaches 100% of the maximum level, the digital conversion value 256 is 9 Output to the bit data generation unit 13.

Here, when the conversion value of the A / D converter 12 is 0 to 192, the 9-bit data generator 13 sends the converted value to the flame memory 14 as it is, and stores the converted value. When the conversion value of (12) is 192 to 256, the conversion value is level converted along the slope of the third straight line L3 indicated by the dotted line in Fig. 3, and the converted value is sent to the flame memory 14. That is, the 9-bit data generation section 13 as the level extension section has a third straight line when the level of the input signal is greater than 50% and therefore the conversion value by the A / D converter section 12 becomes 192 or more. Level increase along the slope of L3. When the maximum value 256 is output from the A / D converter 12, it is expanded to 384 and sent to the flame memory 14 for storage.

By the way, the input signal level-adjusted according to the inclination of each straight line L1, L2 of the figure by the level adjusting part 11A has the brightness ratio 1, 2, 4, 8, 16, 32, 64, 128, respectively, FIG. When 256 gradation display is performed by the conventional eight subfields SF1 to SF8, only saturated display is possible in a portion where brightness is bright.

Therefore, as shown in Fig. 7, conventionally, one subfield SF9 having a luminance ratio of 128 is added to the eight subfields SF1 to SF8 to increase the display grayscale from 256 bits of 8 bits to 384 gray levels of 9 bits, so that the luminance is increased. The bright part (that is, the input signal whose signal level exceeds 50%) is level-extended.

In this case, in addition to the A / D converter 12 that converts the input signal from the level adjuster 11A into 8 bits as in the prior art, the 9-bit data generation described above is generated on the output side of the A / D converter 12. In the case where the unit 13 is provided and the level of the input signal is 50% or more, the 9-bit data generation unit 13 performs the same level decompression operation as described above. As indicated by the section L3, the linear relationship between the input signal and the display luminance can be obtained. By doing in this way, the luminance display which matches the level of an input signal can be performed, avoiding the saturation display of a bright luminance signal.

In this way, when the display gradation of the PDP is increased from 256 gradations to 384 gradations, the 9-bit data generation section 13 is provided so that data processing in a signal processing circuit such as an A / D conversion section can be processed with 8 bits. have.

As described above, the present invention is to increase the gradation in a dark image in which the human eye is more sensitive. As a result, when 60% (10 million colors) of display colors were displayed, only 32% (5.7 million colors) of display colors could be displayed when the number of display colors was to be raised to the CRT level. Since the data processing of the signal processing circuit can be performed with the conventional 8 bits when the gradation is increased, there is no need to add an expensive signal processing circuit for performing the 9-bit processing newly, thus making the apparatus inexpensive. Can be configured to a value.

As described above, according to the present invention, a level compression is performed on a bright blue (B) signal which is an input video signal of an input video signal band of a predetermined level or more, and an input video signal including the level-compressed video signal is A. The digital video signal corresponding to the level-compressed input video signal band of the A / D converted digital video signal is outputted as a digital video signal having a predetermined number of gradations by / D conversion and displayed on the PDP. It is possible to suppress the decrease in the gradation of the red (R) signal and the green (G) signal whose luminance, which is a signal below the level, is dark, thereby increasing the number of display colors as a whole device, and in addition, Since the processing can be performed with a conventional example of 8 bits, it is not necessary to add a new expensive signal processing circuit and perform data processing. The can be configured inexpensively.

Further, since the level is increased so that the number of gray levels increases during A / D conversion for an input video signal of an input video signal band of a predetermined level or less, it is possible to increase the gray level of an image of a dark portion where the human eye is more sensitive.

Claims (4)

In the gradation display processing apparatus of the plasma display panel, inputting a video signal converts the input video signal into a digital video signal having a predetermined number of gradations and displays the converted digital video signal on a plasma display panel. A level adjusting unit for level compressing the input video signal in the input video signal band having a predetermined level or more; An A / D converter configured to A / D convert an input video signal including the level compressed video signal and output the digital video signal; A level expansion unit for level-extending the digital video signal corresponding to the level-compressed input video signal band among the digital video signals A / D converted by the A / D conversion unit, And a digital video signal A / D converted by the A / D converter and a digital video signal level-extended by the level extender on the plasma display panel. The method of claim 1, wherein the level adjusting unit is further configured to increase the gradation number so as to increase the number of gradations during the A / D conversion by the A / D converter for an input video signal of an input video signal band of a predetermined level or less. A gradation display processing apparatus of a plasma display panel. In the gradation display processing method of the plasma display panel, when the video signal is input, the input video signal is converted into a digital video signal having a predetermined number of gradations, and the converted digital video signal is displayed on a plasma display panel. Level compressing an input video signal in an input video signal band of a predetermined level or more, A / D converting the input video signal including the level-compressed video signal and outputting the digital video signal; And level-extending the digital video signal corresponding to the level-compressed input video signal band. The gradation display processing method of a plasma display panel according to claim 3, further comprising a step of increasing the gradation number so as to increase the gradation number during the A / D conversion for an input video signal of an input video signal band of a predetermined level or less.