KR20010012116A - Clock recovery circuit and a receiver having a clock recovery circuit - Google Patents

Abstract

The data receiver comprises: receiving means for receiving a data signal and providing a baseband output, demodulation means connected to an output of said receiving means and providing a data output, coupled to an output of said demodulation means, Symbol recovery means 36, 42 for recovering the presented symbol. The symbol recovery means comprises means 52 for determining the time difference between the rising and falling edge and its nominal reference point at the data output and each clock reference value for the rising and falling edge from the time difference between the rising and falling edge. Means 54 for determining the number of times.

Description

CLOCK RECOVERY CIRCUIT AND A RECEIVER HAVING A CLOCK RECOVERY CIRCUIT}

In receivers used to receive digital signals such as pagers and cellular telephones and cordless telephones, the received signal is demodulated, decoded and converted into one or two bits of non-return to zero (NRZ) data. Lose. In order to process the information completely and properly, a locally generated synchronization clock is required. A clock recovery circuit is provided to generate this synchronization clock.

U. S. Patent No. 5,418, 822 discloses a circuit arrangement for generating a clock signal from a digital signal by evaluating signal edges of the digital signal. The first device generates pulses at the signal edges oriented in the first direction, and the second device generates pulses at the signal edges oriented in the second direction opposite the first direction. Each device has one terminal and one output for receiving digital signals. The voltage controlled trigger oscillator device has at least two trigger inputs, one control input and one output. Each trigger input is connected to the output of each of the first and second devices, and the output of the oscillator device is an output for a clock signal. The integrated device has an input coupled to the output of the oscillator device and an output coupled to the control input of the oscillator device. The purpose of this circuit arrangement is to generate a clock signal whose frequency and phase are both synchronized with the clock signal which is the basis for the data in the digital signal.

A disadvantage of clock recovery circuits that are synchronized to rising and falling edges is that if there is a change in the group delay of the transmitter, there is a gap between the generated jitter and the rising and falling edges of the recovered data, causing a loss of sensitivity of the clock signal. Relative shift occurs.

The present invention relates to a clock recovery circuit, a receiver having the clock recovery circuit and a method for recovering a clock signal.

For convenience of explanation, the present invention will be described with reference to a receiver.

1 is a simplified block schematic diagram of a selective calling system.

2 is a simplified block schematic diagram of a clock recovery circuit.

3 is a vector diagram of a known type of phase locked loop;

4A and 4B are timing diagrams of initial occurring symbols, respectively, and timing diagrams of the same symbols received by the second station.

5 is a simplified block schematic diagram of a clock recovery circuit for use in a receiver made in accordance with the present invention.

6 is a vector diagram of a phase jitter loop that is substantially jitter free.

7 is a block schematic diagram of another embodiment of the present invention;

8 shows a short symbol with δ / 2 error for rising and falling edges.

FIG. 9 illustrates one method of averaging the current phase of a phase locked loop and generating the recovered clock in FIG.

It is an object of the present invention to avoid loss of sensitivity in clock recovery of FSK signals.

Receiving means for receiving a data signal and providing a baseband output according to an aspect of the present invention, demodulation means connected to an output of said receiving means and providing a data output, and said data connected to an output of said demodulation means. A receiver is provided that includes symbol recovery means for recovering a symbol presented at the output, the symbol recovery means being means for determining the occurrence of rising and falling edges at the data output, the difference between the occurrence of the rising and falling edges. Means for determining a mean, and means for using the difference to determine a clock reference position.

Means for determining the occurrence of rising and falling edges of the data signal, means for determining the difference between the occurrence of the rising and falling edges, and determining the clock reference position in accordance with a second aspect of the present invention. A clock recovery circuit is provided that includes means for use.

In one embodiment of the invention, the means for determining the time difference at the rising and falling edges and their common reference point at the data output generates a time difference signal. In addition, a phase locked loop (PLL) means is provided with input means for the rising and falling edges and the time difference signal and means for calculating each reference position for the rising and falling edges.

By means of phase locked loop means for calculating each reference position for the rising and falling edges, the phase locked loop means precedes or delays each symbol change since the rising and falling edges are adjacent to their respective calculated reference positions. Could not be. As a result, the jitter is greatly reduced due to the different bit lengths without reducing the bandwidth of the phase locked loop means. The problem that the sensitivity is degraded due to the difference in the bit lengths is solved without changing the bandwidth of the phase locked loop means. In addition, the requirements of frequency stability for phase locked loop reference oscillators are not stringent, allowing the use of less expensive crystals with less stringent specifications.

In the second embodiment of the present invention, each rising and falling edge phase locked loop means is provided to indicate the occurrence of each edge position with respect to a predetermined phase, and an average means is a rotating means of phase in each phase locked loop. To determine a clock reference position from the.

According to a third aspect of the present invention, there is provided a method for recovering a symbol of a data signal, comprising determining the occurrence of rising and falling edges of the data signal and determining the difference between the occurrence of the rising and falling edges. And using the difference to determine a clock reference position.

The invention will now be described and described by way of example with reference to the drawings.

In the drawings, like reference numerals have been used to designate corresponding parts.

The selective calling system shown in FIG. 1 includes a first station 10 having a second station 20 and having an input 12 for paging a message being relayed to a preselected user. The paging message is encoded and formatted at stage 14 and sent to wireless transmitter 16 for forward transmission as a point-to-point paging signal. The operation of the first station is controlled by the system controller 18.

The second station 20 frequency downs the quadrature associated I and Q signals at the received signal or zero IF to generate an output 24 comprising a receiver 22, e.g., a sequence of bits consisting of a single or a pair of bits. A superheterodyne receiver or a zero IF receiver. This output 24 comprises a baseband stage 26 comprising a demodulator 28 which filters and decodes this output 24 and also converts it into 1 or 2 bits of non-zero return write (NRZ) data 30. Is applied to. The clock recovery circuit 32 generates a symbol clock signal from the NRZ data 30 and supplies the data and symbol clock to the processor 34, the symbol value being in the middle between the rising and falling edges. Is derived by sampling 30).

In general, clock recovery relies on edge detection for synchronization of the received data and the local clock signal, which corresponds to a change in data state. In a selective calling system, such as a paging system operating according to CCIR radio paging code number 1 or known as POCSAG, the data corresponds to the frequency of a radio signal modulated in a frequency shift keyed (FSK) manner. .

A typical clock recovery circuit 32 is shown in FIG. The NRZ data 30 is applied to the edge detector 36 and the edge detector 36 outputs signals 38 and 40, respectively, corresponding to the rising edge or increase at the FSK frequency and the falling edge or reduction at the FSK frequency, respectively. to provide. Rising and falling edge signals 38 and 40 are applied to PLL 42 to synchronize itself with these edge signals and generate a recovery clock signal 44 in the middle between the detected and rising edges. .

The weakening in this typical clock recovery circuit 32 is due to the group delay of the FSK frequency at the transmitter 16 of the first station 10 and / or in the presence of a common channel signal, causing the rising and falling edges and all the symbols to fall off. This is the case where there is a relative shift between the edges of the friction signal, having the same length, hereafter referred to as the “reference point”. In the second station, the edge in demodulated NRZ data 30 does not occur at predetermined reference points but occurs in both regions of the reference point. The effect of this relative shift causes the PLL 42 to precede or delay each symbol change in order to align the PLL side by side with the predetermined reference point, which causes an increase in PLL jitter and a loss of sensitivity.

The vector diagram shown in FIG. 3 shows a rising edge (leading) 46, a falling edge (delay) 47, a reference point 48 and a symbol clock 50 that is 180 degrees away from the reference point 48. .

FIG. 4A shows original undistorted NRZ data with each pulse having a nominal symbol period (T seconds). 4B shows the effect of group delay of symbols, whereby a positive pulse is shorter by δ seconds than a period T, while a negative pulse is longer by δ seconds than a period T, where δ is the time difference between the received symbol period and the ideal period T. Nevertheless, the rising and falling edges 46, 47 (or falling and rising edges) of each pulse are arranged symmetrically with respect to the ideal period represented by the reference point 48 and the time period of δ / 2 is the ideal period edge. And between adjacent rising or falling edges. According to the present invention, a recovered clock can be generated from at least recognizing the occurrence of rising and falling edges.

Referring to FIG. 5, data 30 from a demodulator (not shown) is applied to the edge detector 36, and the edge detector 36 has a rising edge signal 38 and a falling edge signal 40. Each signal is applied to the first portion 52 of the PLL 42 where a value of δ is determined. This value is determined in an adaptive manner by measuring the time between the rising and falling edges or vice versa. Appropriate integration constants allow for a change in δ due to noise limitations, while at the same time allowing δ to be determined quickly enough so that no data is lost during synchronization. In one embodiment of the invention, edge detector 36 includes a state machine that filters any noise near the edges and calculates the midpoint between the edges.

The second portion 54 of the PLL 42 receives not only data edges 38 and 40 but also δ and based on δ, the second portion 54 provides a reference position for the rising edge and another reference for the falling edge. Calculate your location. As a result of calculating these reference positions, the PLL 42 will not precede or delay for each symbol change because the operating rising and falling edges are close to each calculated reference position.

6 shows a vector diagram of a substantially jitter-free PLL. The rising reference point (+ δ / 2) 56 and the falling reference point (−δ / 2) 58 are placed on the right half of the figure and the recovered clock 50 is on the left half of the reference points 56, 58 of the figure. It is arranged symmetrically.

5, the PLL 42 will only precede when the edge occurs after its reference position and will be delayed when the edge occurs before that reference position.

The circuit arrangement shown in FIG. 5 allows jitter to be greatly reduced without reducing the bandwidth of the PLL due to the different symbol lengths. Lock time can be quickly maintained so as not to miss synchronization. Finally, the requirements for the PLL reference oscillator are not stringent, which leads to the use of cheaper crystals with less stringent specifications.

The embodiment of the present invention shown in FIG. 7 includes an edge detector 36 for detecting the edge of the NRZ signal. Edge detector 36 generates a signal indicative of a falling edge at output 38 and a signal indicative of a rising edge at output 40. Outputs 38 and 40 are connected to phase locked loops 60 and 62, respectively. Phase-locked loops 60, 62 proceed to align with rising edge indications at output 38 and falling edge indications at output 40, respectively. Phases 64 and 66 of rising edge PLL 60 and falling edge PLL 62 are provided to stage 68, respectively, and stage 68 calculates the average phase of the PLL, with the average of the phases being relative to the reference point. When the difference is 180 degrees, it indicates the recovered clock.

When the rising edge precedes the falling edge during operation, the phases of the PLLs 60 and 62 will have offsets of δ / 2 and -δ / 2, respectively, relative to the reference point, as shown in FIG. Conversely, when the falling edge precedes the rising edge, the phases of the PLLs 60, 62 will have offsets of δ / 2 and -δ / 2, respectively, relative to the reference point. By determining the average of these two phases in stage 68, the center of the symbol will accurately indicate that there is no error in the output 50.

The point at which the minimum cyclic average of phases 64 and 66 is 180 degrees of phase with respect to the reference point can be calculated in a straightforward manner. With reference to FIG. 9, vectors 46 and 47 show phase values 64 and 66. If two PLLs 60 and 62 are configured such that 180 degrees represent the point where each edge occurs and the angle is represented within the range (-180 degrees to 180 degrees), then the recovered clock 50 has a phase average of 0 degrees. When the output of PLL 60 is equal to the output of negative PLL 62 and both counters are within this range (-90 degrees to 90 degrees).

After reading the present disclosure, other changes will be apparent to those skilled in the art. Such modifications may include known features in the design, product, and use of receivers and components, and may include other features that may be used in addition to, or in addition to, features already described herein.

It can also be used in any application, such as a communication device, that is demodulated and detected to derive a clock signal from a data signal.

Claims (11)

Receiving means for receiving a data signal and providing a baseband output, demodulation means connected to an output of said receiving means for providing a data output, and a symbol presented to said data output connected to an output of said demodulation means. A receiver comprising symbol recovery means for recovering, The symbol recovery means comprises means for determining the occurrence of rising and falling edges at the data output, means for determining the difference between the occurrence of the rising and falling edges, and determining the difference to determine a clock reference position. And means for use. 2. The apparatus of claim 1, wherein the determining means comprises means for determining a time difference between a rising and falling edge and a nominal reference point at the data output to generate a time difference signal, wherein the rising and falling edge and the time difference And a phase locked loop means having input means for the signal and means for calculating each reference position for the rising and falling edges. 3. A receiver as claimed in claim 2, wherein said time difference determining means is used to remove noise edges close to the rising and falling edges. 4. A receiver as claimed in claim 2 or 3, wherein the phase locked loop means comprises means for calculating a clock reference in the middle of each reference position for the rising and falling edges. 2. The apparatus of claim 1, wherein respective rising and falling edge phase locked loop means for determining the occurrence of each rising and falling edge position are provided, wherein the clock locked position is determined from a cyclic average of the minimum value of the phase in the phase locked loop means. A means for providing a receiver is provided. Means for determining the occurrence of rising and falling edges in the data signal, means for determining the difference between occurrence of the rising and falling edges, and means for using the difference to determine a clock reference position. Clock recovery circuit. 7. The apparatus of claim 6, wherein the means for determining comprises means for determining a time difference between a nominal reference point to generate a rising and falling edge and a time difference signal in the data signal, wherein the rising and falling edge and the time difference And a phase locked loop means provided with input means for a signal and means for calculating respective reference positions for said rising and falling edges. 7. The method of claim 6, wherein each rising and falling edge phase locked loop means is provided to determine the occurrence of each rising and falling edge position, and wherein in the phase locked loop means determining a clock reference position from the minimum cyclic average of the phases. Means for providing a circuit. Determining a occurrence of a rising and falling edge in the data signal, determining a difference between the occurrence of the rising and falling edges, and using the difference to determine a clock reference position. Way. 10. The apparatus of claim 9, wherein phase locked loop means determines a time difference between a nominal reference point to generate a rising and falling edge and a time difference signal at the data output, and further comprises the rising and falling edge from the rising and falling edges. And calculate a reference position for the falling edge. 10. The data according to claim 9, wherein the occurrence of each rising and falling edge position is determined by each phase locked loop means, and a clock reference position is determined from the minimum cyclic average of the phases in the phase locked loop means. How to recover a symbol from a signal.