JPH10178458A - Demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulation circuit in which the eliminating effect of a frequency offset is prevented by the increase in the frequency offset resulting in increasing an offset component in a reception symbol wave thereby causing considerable distortion to a waveform of the reception symbol wave. SOLUTION: A frame synchronization detection circuit 14 detects a frame synchronizing signal and provides a detection signal (d) to a counter circuit 15 by using a time given to one frame for the period, the counter circuit 15 counts the time by an oscillation signal P from a voltage controlled oscillator 10 to provide a count N to an error detection circuit 16. The error detection circuit 16 obtains a difference between a reference count stored in advance and a moving mean value of the count N for a plurality of number of times, provides the voltage corresponding to the difference to the voltage controlled oscillator 10 as a control voltage V so as to approach the frequency of an oscillation signal P to the frequency when no frequency offset is present.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a transmission signal having a frame structure which is transmitted in synchronization with a clock signal on a transmission side and whose carrier frequency deviation is sufficiently smaller than that of a local oscillation frequency signal to be described later. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit used in a receiver of a small digital radio communication system, and more particularly to a demodulation circuit having an automatic frequency control function for automatically correcting a frequency offset (a deviation of a frequency of a local oscillation frequency signal for detection from a frequency of a carrier wave).

[0002]

2. Description of the Related Art FIG. 2 shows an example of a circuit configuration of a demodulation circuit conventionally used in a receiver of a digital radio communication system and having a function of automatically correcting deterioration of a received signal waveform due to a frequency offset. Show. In FIG. 1, a local oscillation circuit 1 is a circuit for transmitting a local oscillation frequency signal for detection, and a detection circuit 2 receives a received signal a sent from the antenna side and inputs the received signal a to the local oscillation circuit 1.
Detected using the local oscillation frequency signal from
And sends out the detection signal b. And the detection signal b
Is subtracted from an averaging error e described later in the adder 3, and is sent out as a corrected detection signal f from the adder 3. D
PLL (Digital Phase-Locked)
Loop) 4 receives the corrected detection signal f and receives a received symbol timing signal R synchronized in phase with the received symbol wave.
T is obtained and this received symbol timing signal RT is transmitted. Further, the determination circuit 5 inputs the corrected detection signal f in synchronization with the reception symbol timing signal RT, determines the transmitted symbol based on a preset threshold value, and determines the determination result. Is transmitted. The adder 6 receives the correction detection signal f input to the determination circuit 5 and the reception information signal g output from the determination circuit 5, and outputs a difference between them (an error due to a frequency offset), that is, an error h. And the averaging circuit 7
Obtains an error h in synchronization with the received symbol timing signal RT, obtains a moving average of the error h for a plurality of past times (for example, the past 20 times), and obtains the averaging error of a voltage corresponding to the moving average. e and sends it to the adder 3. Then, as described above, the adder 3 subtracts the averaging error e from the detection signal b to obtain a correction detection signal f and sends it to the decision circuit 5, so that the difference between the correction detection signal f and the reception information signal g (that is, the error h ) Is getting smaller. That is, as long as the determination circuit 5 correctly determines the transmitted symbol, the control automatically proceeds in the direction in which the input / output difference of the determination circuit 5 eventually disappears, and the correction for automatically removing the influence of the frequency offset is performed. Will have the function.

[0003]

However, the conventional demodulation circuit having the function of automatically removing the influence of the frequency offset as described above leaves the existence of the frequency offset itself as described above, and causes the The offset component is detected, and the detected offset component is removed from the received symbol waveform. Therefore, if the frequency offset becomes large and the offset component in the received symbol wave becomes large and the waveform of the received symbol wave is greatly distorted, the offset component in the received symbol wave cannot be detected accurately (mainly the decision (This is because the determination of the circuit 5 cannot be performed accurately), which impairs the function of removing the influence of the frequency offset.

[0004] The present invention has been made in view of the above circumstances, and the frequency offset becomes large, the offset component in the received symbol wave becomes large, and the waveform of the received symbol wave is greatly distorted. An object of the present invention is to provide a demodulation circuit in which an offset component in a received symbol wave cannot be accurately detected and a function of removing the influence of a frequency offset is not impaired.

[0005]

According to the first aspect of the present invention, a transmission signal having a frame structure is transmitted in synchronization with a clock signal on a transmission side, and a carrier frequency shift is controlled by a frequency shift of a local oscillation frequency signal to be described later. The demodulation circuit used in the receiver of the digital radio communication system which is sufficiently smaller than that of the demodulator is configured as follows. That is, an output from an error detection circuit, which will be described later, is input as a control voltage, and a voltage-controlled oscillator that transmits an oscillation signal having a frequency corresponding to the control voltage, and a local signal that receives the oscillation signal from the voltage-controlled oscillator as a reference signal. A frequency synthesizer that outputs an oscillation frequency signal, a detection circuit that detects a reception signal sent from a reception antenna using a local oscillation frequency signal from the frequency synthesizer and sends out a detection signal, and a detection circuit that sends out a detection signal. Input a signal, determine this, get a received information signal,
A determination circuit for transmitting the reception information signal, and a reception information signal from the determination circuit, a frame synchronization signal in the reception information signal, and a frame synchronization detection for transmitting a detection signal each time the detection is performed. A circuit and an oscillation signal from the voltage controlled oscillator are input and counted.
Every time a detection signal is sent from the frame synchronization detection circuit, the count value at that time is sent out, and the count value is set to 0.
And a counter circuit that continues the counting operation and returns a time interval between two consecutive frame synchronization signals (time given to one frame) by an oscillation signal of the voltage controlled oscillator when no frequency offset occurs. The counted value is stored in advance as a reference count value, and the difference between the reference count value and the count value sent from the counter circuit is obtained. If the difference is 0, the voltage-controlled oscillator is And an error detection circuit for changing the control voltage to a voltage acting in a direction to cancel the difference when the difference is not zero.

According to the second aspect of the present invention, the transmission signal having the frame structure is transmitted in synchronization with the clock signal on the transmission side, and the carrier frequency deviation is sufficiently smaller than the frequency deviation of the local oscillation frequency signal described later. A demodulation circuit used in a receiver of a small number of digital wireless communication systems is configured as follows. That is, an output from an error detection circuit, which will be described later, is input as a control voltage, and a voltage-controlled oscillator that transmits an oscillation signal having a frequency corresponding to the control voltage, and a local signal that receives the oscillation signal from the voltage-controlled oscillator as a reference signal. A frequency synthesizer that outputs an oscillation frequency signal, a detection circuit that detects a reception signal sent from a reception antenna using a local oscillation frequency signal from the frequency synthesizer and sends out a detection signal, and a detection circuit that sends out a detection signal. Input the signal,
By determining this, a reception information signal is obtained, a determination circuit for transmitting the reception information signal, and a reception information signal from the determination circuit are input, and a frame synchronization signal in the reception information signal is detected. A frame synchronization detection circuit that sends out a detection signal each time detection is performed, and an oscillation signal from the voltage controlled oscillator is input and counted, and each time a detection signal is sent from the frame synchronization detection circuit, After transmitting the count value at that time, the counter circuit returns the count value to 0 and continues the counting operation, and a counter circuit between the two consecutive frame synchronization signals (time given to one frame)
Is stored in advance as a reference count value with the oscillation signal of the voltage-controlled oscillator when no frequency offset occurs, and a total of a plurality of past counts sequentially sent from the counter circuit is transmitted. A moving average of the numerical values is calculated, and then a difference between the reference count value and the moving average is obtained. When the difference is 0, the control voltage applied to the voltage-controlled oscillator at that time is held. On the other hand, when the difference is not 0, an error detecting circuit for changing the control voltage to a voltage acting in a direction to cancel the difference is provided.

According to the third aspect of the present invention, the transmission signal having the frame structure is transmitted in synchronization with the clock signal on the transmission side, and the carrier frequency deviation is sufficiently smaller than the frequency deviation of the local oscillation frequency signal described later. A demodulation circuit used in a receiver of a small number of digital wireless communication systems is configured as follows. That is, an output from an error detection circuit, which will be described later, is input as a control voltage, and a voltage-controlled oscillator that transmits an oscillation signal having a frequency corresponding to the control voltage, and a local signal that receives the oscillation signal from the voltage-controlled oscillator as a reference signal. A frequency synthesizer that outputs an oscillation frequency signal, a detection circuit that detects a reception signal sent from a reception antenna using a local oscillation frequency signal from the frequency synthesizer and sends out a detection signal, and a detection circuit that sends out a detection signal. Input the signal,
By determining this, a reception information signal is obtained, and a determination circuit for transmitting the reception information signal, and a reception information signal from the determination circuit are input,
A frame synchronization signal in the received information signal is detected, and a frame synchronization detection circuit that sends out a detection signal each time the detection is performed, and an oscillation signal from the voltage controlled oscillator is input,
A counter circuit that counts this, sends a count value at that time each time a detection signal is sent from the frame synchronization detection circuit, returns the count value to 0, and continues the counting operation. The count value counted between two consecutive frame synchronization signals (time given to one frame) with the oscillation signal of the voltage controlled oscillator when no frequency offset occurs is stored in advance as a reference count value. At the same time, a significant and average value of the count value (for example, a count value of 5% or more of the reference count value or a count value of less than 5% based on the count values of the past multiple times sequentially sent from the counter circuit). The most frequent count value for a predetermined number of times) is obtained, and then the difference between the reference count value and the significant and average value is obtained. If the difference is 0, the difference is obtained. An error detection circuit that holds a control voltage applied to the voltage-controlled oscillator at a point in time and, when the difference is not 0, changes the control voltage to one that acts in a direction to cancel the difference. And

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be specifically described with reference to the following embodiments of the present invention. FIG. 1 shows a circuit configuration of the embodiment. The voltage control oscillator 10 is a circuit that receives a control voltage V from an error detection circuit 16 described later and sends out an oscillation signal P having a frequency corresponding to the control voltage V. The frequency synthesizer 11 is a circuit that sends the local oscillation frequency signal Q having a frequency obtained by multiplying the frequency of the oscillation signal P by using the oscillation signal P as a reference signal. The detection circuit 12 is a circuit unit that detects a reception signal a sent from the reception antenna side with the local oscillation frequency signal Q to obtain a detection signal b, and sends out the detection signal b. The received signal a synchronizes each symbol to be transmitted with a clock signal obtained by a high-accuracy clock signal generator (a reference oscillator of the base station), and outputs a signal from the base station transmitted in a frame configuration. The transmission signal is received, and the frequency shift of the carrier related to the received signal a is sufficiently smaller than the frequency shift of the local oscillation frequency signal Q. Judgment circuit 13
Receives the detection signal b, determines the symbol value of each symbol sequentially transmitted based on a process using a preset threshold value, etc., and generates a reception information signal c as a determination result. This is the circuit that sends out.

The frame synchronization detection circuit 14 is a circuit which takes in the received information signal c, detects a frame synchronization signal from the received information signal c, and sends out a detection signal d each time it is detected. The counter circuit 15 receives the oscillation signal P from the voltage controlled oscillator 10 and counts it. The counter circuit 15 receives the detection signal d from the frame synchronization detection circuit 14, and each time, counts the count value at that time. The count value is sent out as N, and then the count value is returned to 0.
This circuit counts up (ie, the counter circuit 15 counts the interval at which the detection signal d is sent out with the oscillation signal P, and sends out the count value N as the counting result). is there). The error detection circuit 16 determines the time between two consecutive frame synchronization signals, that is, the time given to one frame (this is equal to the time interval at which the detection signal d is sent from the frame synchronization detection circuit 14) to the frequency. The oscillating signal of the voltage controlled oscillator when no offset is generated, the counted value is stored in advance as a reference count value, and the counter circuit 15
, A moving average of the count values N for the past plural times sent sequentially is calculated, and then a difference between the reference count value and the moving average is obtained. A voltage corresponding to this difference (the difference is 0
In the case of, the voltage being sent at that time, on the other hand, if the difference is not 0, a voltage acting in a direction to cancel the difference) is obtained, and this voltage is used as the control voltage V by the voltage-controlled oscillator 10. This is the circuit section that sends out.

Next, the operation of the embodiment configured as described above will be described. For example, consider the case where a certain frequency offset has occurred (that is, the frequency of the local oscillation frequency signal Q slightly deviates from the frequency of the carrier wave). At this time, the detection circuit 12 outputs the received signal a
Is detected by the local oscillation frequency signal Q to obtain a detection signal b including an offset component, and this is sent to the determination circuit 13. The determination circuit 13 receives the transmitted detection signal b, determines the symbol value of each symbol sequentially transmitted based on a process using a preset threshold value, etc. A certain reception information signal c is transmitted. The frame synchronization detection circuit 14 takes in the reception information signal c, detects a frame synchronization signal from the reception information signal c, and sends out a detection signal d each time the detection is performed.
The interval time, that is, the period, at which the detection signal d is transmitted from the frame synchronization detection circuit 14 is the time given to one frame, and is configured with reference to the high-precision clock signal on the transmission side. Is a fixed time (hereinafter, this fixed time is referred to as a frame time).

The counter circuit 15 counts the frame time based on the oscillating signal P from the voltage controlled oscillator 10, and counts the counting result N as an error detection circuit 16 each time the detection signal d is sent. Give to. The error detection circuit 16 obtains an average of the count values N sent for a plurality of times, that is, a moving average of the count values N, and obtains the moving average and the reference count value (the frame time is used to generate a frequency offset. (A count value counted by the oscillation signal P of the voltage-controlled oscillator 10 when the voltage is not applied), and when the difference is 0, the control voltage V applied to the voltage-controlled oscillator 10 at that time is left as it is. Value while the difference is 0
If not, the control voltage V is changed to a value that works in a direction to cancel the difference, and is transmitted. The voltage-controlled oscillator 10 is controlled by being supplied with the control voltage V as described above, and updates the frequency of the oscillation signal P to a value close to that when no frequency offset occurs. By updating the frequency of the oscillation signal P, the frequency synthesizer 1
The frequency of the local oscillation frequency signal Q from 1 becomes closer to the carrier frequency. That is, the frequency of the oscillating signal P from the voltage controlled oscillator 10 at that time approaches the frequency of the oscillating signal P when no frequency offset occurs, and the control automatically proceeds so that the difference between the two becomes zero. ,
As a result, the frequency of the local oscillation frequency signal Q from the frequency synthesizer 11 approaches the carrier frequency, and the frequency offset is eliminated.

As described above, in the present embodiment, the offset component is removed from the detection signal b from the detection circuit 12 by eliminating the frequency offset itself. Therefore, the frequency offset increases, the offset component in the received symbol wave increases, the waveform of the received symbol wave is greatly distorted, and the offset component in the received symbol wave cannot be accurately detected, and the influence of the frequency offset is removed. In the event that the function is impaired, it does not happen in the first place.

[0013]

As described in detail above, according to the present invention,
The frequency offset becomes large, the offset component in the received symbol wave becomes large, and the waveform of the received symbol wave is greatly distorted, and the offset component in the received symbol wave cannot be detected accurately. Thus, it is possible to provide a demodulation circuit that does not impair the demodulation.

[Brief description of the drawings]

FIG. 1 shows a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 local oscillation circuit 2 detection circuit 3 adder 4 DPLL 5 determination circuit 6 adder 7 averaging circuit a reception signal b detection signal f correction detection signal g reception information signal h error e averaging error 10 voltage controlled oscillator 11 frequency synthesizer 12 Detection circuit 13 Judgment circuit 14 Frame synchronization detection circuit 15 Counter circuit 16 Error detection circuit c Reception information signal d Detection signal N Count value V Control voltage P Oscillation signal Q Local oscillation frequency signal RT Reception symbol timing signal

Claims (3)

[Claims] 1. A digital radio communication system in which a transmission signal having a frame structure is transmitted in synchronization with a clock signal on a transmission side, and a carrier frequency deviation is sufficiently smaller than a frequency deviation of a local oscillation frequency signal described later. In a demodulation circuit used in a receiver, a voltage-controlled oscillator that inputs an output from an error detection circuit described later as a control voltage and sends out an oscillation signal having a frequency corresponding to the control voltage, and an oscillation from the voltage-controlled oscillator. A frequency synthesizer that inputs a signal as a reference signal and outputs a local oscillation frequency signal, and a detection circuit that detects a reception signal sent from a reception antenna using the local oscillation frequency signal from the frequency synthesizer and transmits a detection signal. Receiving the detection signal from the detection circuit, determining the reception signal to obtain a reception information signal, and A determination circuit that outputs a detection signal; a frame synchronization detection circuit that receives a reception information signal from the determination circuit, detects a frame synchronization signal in the reception information signal, and sends a detection signal each time the detection is performed; An oscillation signal from the control oscillator is input and counted. Each time a detection signal is sent from the frame synchronization detection circuit, the count value at that time is sent out, and the count value is returned to 0. A counter circuit that continues the counting operation, and a count value counted between the two consecutive frame synchronization signals as a reference count value using an oscillation signal of the voltage-controlled oscillator when no frequency offset occurs. The difference between the reference count value and the count value sent from the counter circuit is obtained. If the difference is 0, the control value applied to the voltage-controlled oscillator at that time is obtained. Voltage, while if the difference is not zero, the control voltage is
A demodulation circuit comprising: an error detection circuit that changes the difference into a signal that acts in a direction to cancel the difference. 2. A digital radio communication system in which a transmission signal having a frame structure is transmitted in synchronization with a clock signal on a transmission side, and a carrier frequency deviation is sufficiently smaller than a frequency deviation of a local oscillation frequency signal described later. In a demodulation circuit used in a receiver, a voltage-controlled oscillator that inputs an output from an error detection circuit described later as a control voltage and sends out an oscillation signal having a frequency corresponding to the control voltage, and an oscillation from the voltage-controlled oscillator. A frequency synthesizer that inputs a signal as a reference signal and outputs a local oscillation frequency signal, and a detection circuit that detects a reception signal sent from a reception antenna using the local oscillation frequency signal from the frequency synthesizer and transmits a detection signal. Receiving the detection signal from the detection circuit, determining the reception signal to obtain a reception information signal, and A determination circuit that outputs a detection signal; a frame synchronization detection circuit that receives a reception information signal from the determination circuit, detects a frame synchronization signal in the reception information signal, and sends a detection signal each time the detection is performed; An oscillation signal from the control oscillator is input and counted. Each time a detection signal is sent from the frame synchronization detection circuit, the count value at that time is sent out, and the count value is returned to 0. A counter circuit that continues the counting operation, and a count value counted between the two consecutive frame synchronization signals as a reference count value using an oscillation signal of the voltage-controlled oscillator when no frequency offset occurs. At the same time, from the counter circuit, the moving average of the count values of the past multiple times sequentially sent is calculated, and then the difference between the reference count value and the moving average is calculated. When the difference is 0, the control voltage applied to the voltage-controlled oscillator at that time is held. On the other hand, when the difference is not 0, the control voltage is changed in a direction to cancel the difference. A demodulation circuit, comprising: an error detection circuit that changes to a functioning one. 3. A digital radio communication system in which a transmission signal having a frame configuration is transmitted in synchronization with a clock signal on a transmission side, and a carrier frequency deviation is sufficiently smaller than a frequency deviation of a local oscillation frequency signal described later. In a demodulation circuit used in a receiver, a voltage-controlled oscillator that inputs an output from an error detection circuit described later as a control voltage and sends out an oscillation signal having a frequency corresponding to the control voltage, and an oscillation from the voltage-controlled oscillator. A frequency synthesizer that inputs a signal as a reference signal and outputs a local oscillation frequency signal, and a detection circuit that detects a reception signal sent from a reception antenna using the local oscillation frequency signal from the frequency synthesizer and transmits a detection signal. Receiving the detection signal from the detection circuit, determining the reception signal to obtain a reception information signal, and A determination circuit that outputs a detection signal; a frame synchronization detection circuit that receives a reception information signal from the determination circuit, detects a frame synchronization signal in the reception information signal, and sends a detection signal each time the detection is performed; An oscillation signal from the control oscillator is input and counted. Each time a detection signal is sent from the frame synchronization detection circuit, the count value at that time is sent out, and the count value is returned to 0. A counter circuit that continues the counting operation, and sets the counted value as a reference count value in advance by using an oscillation signal of the voltage-controlled oscillator when a frequency offset does not occur between two consecutive frame synchronization signals. A significant and average value of the count value is obtained from the counter circuit based on the count values of a plurality of past times sequentially sent from the counter circuit. The difference between the numerical value and the above-mentioned significant and average value is obtained, and when this difference is 0,
An error detection circuit that holds the control voltage applied to the voltage-controlled oscillator at that time, and changes the control voltage to one that acts in a direction to cancel the difference when the difference is not zero. A demodulation circuit characterized by the above.