GB9820721D0 - Receiver - Google Patents
ReceiverInfo
- Publication number
- GB9820721D0 GB9820721D0 GBGB9820721.0A GB9820721A GB9820721D0 GB 9820721 D0 GB9820721 D0 GB 9820721D0 GB 9820721 A GB9820721 A GB 9820721A GB 9820721 D0 GB9820721 D0 GB 9820721D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99901851A EP0983659B1 (en) | 1998-02-26 | 1999-02-15 | Clock recovery circuit and a receiver having a clock recovery circuit |
JP54332399A JP4070823B2 (en) | 1998-02-26 | 1999-02-15 | Clock recovery circuit and receiver having clock recovery circuit |
CN99800170.8A CN1227856C (en) | 1998-02-26 | 1999-02-15 | Clock recovery circuit and receiver having clock recovery circuit |
KR1019997009878A KR100613755B1 (en) | 1998-02-26 | 1999-02-15 | Clock recovery circuit and a receiver having a clock recovery circuit and a method for recovering symbols in a data signal |
PCT/IB1999/000264 WO1999044327A2 (en) | 1998-02-26 | 1999-02-15 | Clock recovery circuit and a receiver having a clock recovery circuit |
US09/252,692 US6587531B1 (en) | 1998-02-26 | 1999-02-18 | Clock recovery circuit and a receiver having a clock recovery circuit |
TW088102730A TW417372B (en) | 1998-02-26 | 1999-02-24 | Clock recovery circuit and a receiver having a clock recovery circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9804045.4A GB9804045D0 (en) | 1998-02-26 | 1998-02-26 | Receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
GB9820721D0 true GB9820721D0 (en) | 1998-11-18 |
Family
ID=10827615
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GBGB9804045.4A Ceased GB9804045D0 (en) | 1998-02-26 | 1998-02-26 | Receiver |
GBGB9820721.0A Ceased GB9820721D0 (en) | 1998-02-26 | 1998-09-24 | Receiver |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GBGB9804045.4A Ceased GB9804045D0 (en) | 1998-02-26 | 1998-02-26 | Receiver |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR100613755B1 (en) |
GB (2) | GB9804045D0 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102342830B1 (en) | 2019-12-02 | 2021-12-23 | 홍익대학교 산학협력단 | Multi-phase multiplying delaylocked loop based digital clock data recovery apparatus and method for recovery clock data |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208833A (en) * | 1991-04-08 | 1993-05-04 | Motorola, Inc. | Multi-level symbol synchronizer |
-
1998
- 1998-02-26 GB GBGB9804045.4A patent/GB9804045D0/en not_active Ceased
- 1998-09-24 GB GBGB9820721.0A patent/GB9820721D0/en not_active Ceased
-
1999
- 1999-02-15 KR KR1019997009878A patent/KR100613755B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20010012116A (en) | 2001-02-15 |
KR100613755B1 (en) | 2006-08-22 |
GB9804045D0 (en) | 1998-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AT | Applications terminated before publication under section 16(1) |