KR20010010313A - Method for forming electrodes using electroplating - Google Patents

Abstract

PURPOSE: A method for forming an electrode using an electric plating is provided to prevent a slope etching of a lower electrode and makes a complete cell division, by forming a passivation layer having an etching ratio lower than a seed layer on Pt electrode. CONSTITUTION: An interfacial insulation layer(42) including a contact hole is formed on a substrate(40). A conductive plug(48) is formed on the contact hole. A seed layer is formed on the conductive plug and the interfacial insulation layer. An electrode(56) covering the conductive plug and a passivation layer having an etching ratio lower than the seed layer are sequentially formed on the seed layer. The seed layer around the electrode is removed. The passivation layer is removed. Thereby, the method for forming an electrode using an electric plating forming a passivation layer having an etching ratio lower than a seed layer on Pt electrode, and thus prevents a slope etching of a lower electrode and makes a complete cell division.

Description

Method for forming electrodes using electroplating

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an electrode forming method using electroplating.

When a noble metal such as white electrode or ruthenium is used as the lower electrode material, the formation method is largely divided into sputtering, chemical vapor deposition (CVD), and electroplating.

Although sputtering and chemical vapor deposition have advantages in terms of cost, process stability, and step coverage, sputtering has poor step coverage and difficulty in forming a three-dimensional electrode, and chemical vapor deposition, in particular, source gas, The price of the MO source is high, resulting in a high process cost.

Accordingly, in comparison with other processes, a method of forming a precious metal electrode using electroplating, which has been theoretically well established for a long time, has been attracting attention. Referring to FIGS. 1 to 6, a conventional electrode forming method using the electroplating is referred to. Explain.

Referring to FIG. 1, an interlayer insulating layer 12 is formed on a semiconductor substrate 10. A photoresist film pattern 14 is formed on the interlayer insulating film 12 to expose a predetermined region of the interlayer insulating film 12. The exposed portion of the interlayer insulating layer 12 is removed by etching the entire surface of the interlayer insulating layer 12 using the photoresist layer pattern 14 as an etching mask. Next, the photoresist film pattern 14 is removed.

Referring to FIG. 2, a contact hole 16 through which the semiconductor substrate 10 is exposed is formed in the interlayer insulating layer 12 by the etching. The first conductive plug 18 is formed in the contact hole 16.

Referring to FIG. 3, a seed layer 20 to be used for electroplating is formed on the entire surface of the first conductive plug 18 and the interlayer insulating layer 12. Platinum (Pt), ruthenium (Ru), or the like is used as the seed layer 20. An insulating film 22 is formed on the seed layer 20 to define an electrode formation region. A photoresist film pattern 24 defining an electrode forming region is formed on the insulating film 22. The entire surface of the insulating layer 22 is etched using the photoresist layer pattern 24 as an etching mask. Thereafter, the photoresist film pattern 24 is removed.

Referring to FIG. 4, by etching the insulating layer 22, an exposed portion of the insulating layer 22 is removed to form a via hole 26 through which the seed layer 20 is exposed. The second conductive plug 28 is filled in the via hole 26 by electroplating. The second conductive plug 28 is a platinum plug or ruthenium plug and is used as a lower electrode. Hereinafter, the second conductive plug 28 is referred to as a lower electrode. After the electroplating is completed, the resultant is wet etched to remove the insulating layer 22.

Referring to FIG. 5, the insulating layer 22 is completely removed from the seed layer 20 by the wet etching, and only the lower electrode 28 remains. The insulating layer 22 is removed to expose the seed layer 20 formed around the lower electrode 28. In order to remove the exposed portion of the seed layer 20, the entire surface of the semiconductor substrate 10 from which the insulating layer 22 is removed is etched back 30. The etch back 30 removes the seed layer 22 around the lower electrode 28 to form a seed layer pattern 20a under the lower electrode 28. The lower electrode 28 is a cell unit. Can be separated.

However, as shown in FIG. 6, the front surface of the lower electrode 28 is also etched by the etch back 30 to form a lower electrode 28a having an inclined side. If the inclination is formed on the surface of the lower electrode 28, the surface area is reduced, resulting in a reduction of the capacitance of the capacitor.

Meanwhile, when both the lower electrode 28 and the seed layer 20 are formed of platinum, platinum does not have a volatile compound, and thus etching is mainly performed by sputtering. The platinum and platinum compounds separated from the seed layer 22 by the sputtering have low volatility and are thus attached to the lower electrode 28 again. Platinum and the compound separated from the lower electrode 28 are scattered between the lower electrode 28 and stacked between the lower electrode 28. For this reason, not only the cell unit separation of the lower electrode 28 is not completely performed, but also a problem that the etching is stopped when severe. This phenomenon is further exacerbated as semiconductor devices are highly integrated.

Accordingly, an object of the present invention is to solve the problems of the prior art described above, and to provide an electrode forming method using electroplating which can prevent inclined etching of the lower electrode and achieve complete cell separation. .

1 to 6 are cross-sectional views showing step-by-step methods of forming electrodes according to the prior art using electroplating.

7 to 14 are cross-sectional views illustrating a method of forming an electrode using electroplating according to a first embodiment of the present invention.

15 and 16 are cross-sectional views illustrating an electrode forming method using electroplating according to a second embodiment of the present invention together with FIGS. 7 to 10 and 12 to 14.

<Code Description of Main Parts of Drawing>

40: substrate. 42: interlayer insulation film.

48: conductive plug. 50: Seed layer.

52: insulating film. 53: Beer hall.

56: electrode. 58, 60a: electrode.

In order to achieve the above technical problem, the present invention (A) forming an interlayer insulating film including a contact hole on the substrate; (b) forming a conductive plug in the contact hole; (c) forming a seed layer on the conductive plug and the interlayer insulating film; (d) sequentially forming an electrode covering the conductive plug on the seed layer and a passivation layer having an etching rate lower than that of the seed layer; (e) removing the seed layer around the electrode; And (f) it provides a method for forming an electrode using an electroplating comprising the step of removing the protective film.

Step (d) may include forming an insulating film on the seed layer; Forming a via hole exposing the seed layer on the entire surface of the conductive plug in the insulating film; Sequentially forming an electrode and the protective film in the via hole by electroplating; The method may further include removing the insulating film.

According to another embodiment of the present invention, step (d) comprises: forming an insulating film on the seed layer; Forming a via hole exposing the seed layer on the entire surface of the conductive plug in the insulating film; Forming an electrode in a portion of the via hole using electroplating; Selectively forming a passivation layer having a lower etch rate than the seed layer to fill the remainder of the via hole on the electrode; The method may further include removing the insulating film.

In this process, a protective film is selectively formed on the electrode using a metal organic (MO) source.

According to another embodiment of the present invention, the step (d) comprises the steps of forming an insulating film on the seed layer; Forming a via hole exposing the seed layer on the entire surface of the conductive plug in the insulating film; Forming an electrode in a portion of the via hole by electroplating; Forming a second insulating film filling the rest of the via hole on the insulating film; Planarizing the entire surface of the second insulating film until the insulating film is exposed; The method may further include removing the insulating film.

The seed layer is preferably formed of a noble metal layer such as a platinum (Pt) layer, a ruthenium (Ru) layer, or an iridium (Ir) layer, but may be a metal layer that does not form an oxide in the plating solution.

The electrode is preferably formed of a noble metal layer such as a platinum layer, ruthenium layer or iridium layer.

The protective film is preferably formed of a titanium film, tungsten film, aluminum film or copper film.

The insulating film is removed by wet etching.

As such, by forming a protective film having a lower etching rate than that of the seed layer on the electrode formed by electroplating, the electrode may be etched in the process of removing the subsequent seed layer to prevent the inclination from being formed on the side thereof. The electrode can be completely separated.

Hereinafter, an electrode forming method using electroplating according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention can be modified in many different forms, the scope of the invention should not be construed as limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements.

7 to 14 are cross-sectional views illustrating a method of forming an electrode using electroplating according to a first embodiment of the present invention, and FIGS. 15 and 16 are FIGS. 7 to 10 and 12 to 12. 14 is a cross-sectional view illustrating a method of forming an electrode using electroplating according to a second exemplary embodiment of the present invention.

<First Embodiment>

Referring to FIG. 7, an interlayer insulating layer 42 is formed on a substrate 40, for example, a semiconductor substrate. A photosensitive film pattern 44 exposing a part of the interlayer insulating film 42 is formed on the interlayer insulating film 42. The entire surface of the interlayer insulating layer 42 is etched using the photoresist pattern 44 as an etching mask. Thereafter, the photoresist pattern 44 is removed.

Referring to FIG. 8, a contact hole 46 through which the substrate 40 is exposed is formed in the interlayer insulating layer 42 due to the etching. The conductive plug 48 is filled in the contact hole 46. A seed layer 50 is formed on an entire surface of the conductive plug 48 and the interlayer insulating layer 42. The seed layer 50 may be formed of a noble metal layer such as a platinum (Pt) layer, a ruthenium (Ru) layer, or an iridium (Ir) layer, but may be a metal layer that does not form an oxide in the plating solution.

9, an insulating film 52 is formed on the entire surface of the seed layer 50. A photosensitive film pattern 54 is formed on the insulating film 52 to expose the conductive plug 48 and the insulating film covering the periphery thereof as an electrode forming region. The entire surface of the insulating layer 52 is etched using the photoresist pattern 54 as an etching mask. Thereafter, the photoresist pattern 54 is removed.

Referring to FIG. 10, due to the etching, a via hole 53 is formed in the insulating layer 52 to expose a portion of the seed layer 50 that covers the entire surface of the conductive plug 48 and a portion of the periphery thereof. . A portion of the via hole 53 is filled to form an electrode 56. The electrode 56 is formed using electroplating. The electrode 56 is preferably formed of a noble metal layer such as a platinum layer, ruthenium layer or iridium layer. The passivation layer 58 is formed by electroplating on the remaining portion of the via hole 53 filled with the electrode 56. The passivation layer 58 is formed of a material layer having an etch rate lower than that of the seed layer 50. For example, it is preferable to form a titanium film, a tungsten film, an aluminum film or a copper film. The insulating film 52 is removed by wet etching the resultant formed with the protective film 58.

Referring to FIG. 12, the wet layer exposes the seed layer 50 around the electrode 56. An exposed portion of the seed layer 50 around the electrode 56 is anisotropically etched using the passivation layer 58 as an etch mask.

Referring to FIG. 13, by the anisotropic etching, the seed layer 50 formed on the interlayer insulating layer 42 around the electrode 56, that is, between the electrodes 56 is removed to inter-cell cells of the electrode 56. Separation takes place. At this time, since the upper portion of the electrode 56 is protected by the passivation layer 58 is not affected by the anisotropic etching.

Referring to FIG. 14, after the anisotropic etching is completed, the passivation layer 58 is wet etched. As a result, the electrode 56 separated between the cells on the interlayer insulating film 42 is completed. Thereafter, a cell capacitor is completed by forming a dielectric film and an upper plate (not shown) on the front surface of the electrode 56.

<2nd Example>

The second embodiment is characterized in that the protective film 58 is formed in an optional manner.

Specifically, referring to FIGS. 10 and 11, after forming the electrode 56, the electrode 56 is formed by a metal organic chemical vapor deposition method using a metal organic source (MO) source. The protective film 58 is selectively formed only on the top. The MO source may be aluminum (Al), ruthenium (Ru), or the like, which is selectively formed only on the conductive layer in a metal organic chemical vapor deposition method.

<Third Embodiment>

The third embodiment provides another method for forming the protective film 58.

Referring to FIG. 15, after forming the electrode 56 by electroplating, a second insulating layer 60 is formed on the insulating layer 52 to fill the remaining unfilled portion of the via hole 53. The second insulating layer 60 may be a material layer having a lower etch rate than the seed layer 50.

Referring to FIG. 16, the entire surface of the second insulating layer 60 is planarized until the insulating layer 52 is exposed. As a result, a protective film 60a is formed on the electrode 56. In this case, the passivation layer 60a is a pattern of the second insulating layer 60. Subsequent processes proceed according to the first embodiment.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art may use the material of the seed layer differently according to electrodes, and the above process may be applied to processes other than capacitor formation. Thus, the electrode 56 is not limited to the lower electrode of the capacitor. In addition, the process of forming the protective film 58 or 60a may be various methods other than those mentioned in the first to third embodiments. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, by forming a protective film having an etch rate lower than that of the seed layer on the noble metals formed by electroplating, for example, platinum electrodes, the electrode is etched in the process of removing the subsequent seed layer to prevent the inclination from being formed on the side thereof. It is possible to completely separate the electrodes in units of cells without damaging the electrodes.

Claims (3)

(a) forming an interlayer insulating film including a contact hole on the substrate; (b) forming a conductive plug in the contact hole; (c) forming a seed layer on the conductive plug and the interlayer insulating film; (d) sequentially forming an electrode covering the conductive plug on the seed layer and a protective film having an etch rate lower than that of the seed layer; (e) removing the seed layer around the electrode; And and (f) removing the protective film. 2. The method of claim 1, wherein (d) comprises: forming an insulating film on the seed layer; Forming a via hole exposing the seed layer covering the conductive plug in the insulating film; Sequentially forming an electrode and the passivation layer in the via hole, using electroplating; And The method of forming an electrode using electroplating further comprising the step of removing the insulating film. 2. The method of claim 1, wherein (d) comprises: forming an insulating film on the seed layer; Forming a via hole exposing the seed layer covering the conductive plug in the insulating film; Forming an electrode in a portion of the via hole using electroplating; Selectively forming a passivation layer having a lower etch rate than the seed layer to fill the remainder of the via hole on the electrode; And The method of forming an electrode using electroplating further comprising the step of removing the insulating film.