KR20010010021A - Digital tracking apparatus - Google Patents

Abstract

PURPOSE: A digital tracking apparatus is to increase a lock-up speed of an external horizontal synchronizing signal included in a composite video image signal, thereby preventing a bending phenomenon of an upper portion of an image. CONSTITUTION: A pixel counter(36) counts a system clock signal to be reset to the first value responding to a line counting value. A phase comparing portion(30) compares an external horizontal synchronizing signal extracted from a composite video image signal with a counted value from the pixel counter responding to an enable signal. An operating portion(32) operates an error rate of a phase and outputting a result. An adding portion(34) adds the operated result and a desired offset value. A timing generating portion(38) generates an internal horizontal synchronizing signal using the result value counted from the pixel counter, and extracts the external vertical synchronizing signal from the composite video image signal. And a phase comparison section setting portion(40) compares the result of counting the internal horizontal synchronizing signal with the second value and generating the enable signal responding to a result.

Description

Digital tracking apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for processing video signals, such as a video cassette recorder, and more particularly, to a digital tracking device for digitally tracking a horizontal sync signal included in a video signal.

Hereinafter, the configuration and operation of a general horizontal synchronization signal tracking system in the National Television System Committee (NTSC) method will be described as follows with reference to the accompanying drawings.

1 is a block diagram of a general horizontal synchronization signal tracking system, including a digital tracking device 10, a discrete time oscillator (DTO) 12, a phase-locked-loop (PLL) 14 , First and second dispensing portions 16 and 18.

An external horizontal synchronization signal included in the composite video image signal is generated every 1716T, where T represents a period of the system clock signal SCK having a frequency of 27 MHz. At this time, the digital tracking device 10 shown in FIG. 1 counts the system clock signal SCK and counts the phase error of the external horizontal synchronization signal input through the input terminal IN to the system clock signal SCK. Error amount is extracted in comparison with. That is, the digital tracking device 10 checks the phase error of the external horizontal synchronization signal every horizontal line by the system clock signal SCK, performs a constant operation on the error amount, and then free-running The offset value OFFSET and the added value freq for generating the frequency are output to the discrete time oscillator 12.

On the other hand, the discrete time oscillator 12 receives a signal having a specific frequency in response to an added value freq output from the digital tracking device 10 and a clock signal XCK, which may have a frequency of, for example, 24.576 MHz. And output the generated signal to the phase locked loop 14. At this time, the phase locked loop 14 is used to further reduce the jitter of the signal generated by the discrete time oscillator 12. Here, the phase lock loop 14 and the first and second dividers 16 and 18, which may be constituted by a phase detector (not shown), a voltage controlled oscillator (not shown), or the like, may be configured to have a period of an external horizontal sync signal. Adjusts the frequency and phase of the system clock signal SCK and adjusts the system clock signal SCK having the adjusted frequency and phase so as to be 1716 times the period of the system clock signal SCK. Will output

On the other hand, referring to the operation of the above-described digital tracking device 10, since the conventional horizontal tracking signal is normally tracked even when a video image signal in which a head switch pulse is present is inputted, the phase changes rapidly. The horizontal lock-up speed (the speed at which the horizontal synchronization signal and the system clock signal are synchronized) is somewhat slow, causing a problem that the upper part of the screen that is displayed on the television is bent.

An object of the present invention is to provide a digital tracking device capable of improving the lockup speed of an external horizontal synchronization signal included in a composite video image signal.

1 is a block diagram of a general horizontal sync signal tracking system.

2 is a block diagram of a preferred embodiment of the digital tracking device according to the present invention.

According to an aspect of the present invention, there is provided a digital tracking device including a pixel counter counting a system clock signal and reset to a first predetermined value in response to a line counting value, and an external horizontal sync signal extracted from a composite video image signal. A phase comparison unit for comparing the result counted by the pixel counter in response to an enable signal, outputting the compared result as a phase error amount, and calculating and processing the phase error amount and outputting a result of the calculation process; A timing unit for generating an internal horizontal synchronizing signal by using an adder configured to add the calculated result and a predetermined offset value, and a result counted by the pixel counter, and extracting an external vertical synchronizing signal from the composite video image signal Comparing a result of counting the generator and the internal horizontal synchronization signal with a second predetermined value, and comparing And a phase comparison section setting unit configured to generate the enable signal corresponding to the result and output the counted value of the internal horizontal synchronization signal as the line counting value at the time when the enable signal is generated. A negative output is preferably used to synchronize the system clock signal to the external horizontal sync signal.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the digital tracking device according to the present invention will be described as follows.

2 is a block diagram of a preferred embodiment of the digital tracking device according to the present invention, which includes a phase comparator 30, a calculator 32, an adder 34, a pixel counter 36, a timing generator 38, and a phase. The comparison section setting unit 40 is configured.

The pixel counter 36 shown in FIG. 2 performs a counting operation in response to the system clock signal SCK input to the clock terminal CK, and counts the counted result in the phase comparator 30 and the timing generator 38. ) In addition, the pixel counter 36 is reset to a first predetermined value, for example, 1716 in response to the line counting value LCOUNT output from the phase comparison section setting unit 40. This is because the external horizontal synchronizing signal and the system clock signal were in a synchronous state before the head switch pulse was input, that is, the phase error amount PE was '0'. This is to cause the phase error amount PE of '0' to be generated from the phase comparison unit 30 when the line counting value LCOUNT, which is at the end, is generated. For example, in the NTSC scheme, the pixel counter 36 performs a counting operation from 30 to 1745 to generate 1716T for the external horizontal synchronization signal.

The phase comparator 30 inputs an external horizontal sync signal extracted from the composite video image signal through the input terminal IN, and counts the input external horizontal sync signal and the result counted by the pixel counter 36. The comparison is performed in response to the enable signal EN generated from 40, and the result of the comparison is output to the calculator 22 as the phase error amount PE. Here, in the NTSC system, when counting the system clock signal SCK having a frequency of 27 MHz, one line (37 s * 1716 ㎲ 63.5 외부) of the external horizontal synchronous signal is composed of 1716T, so that the external horizontal synchronous signal is counted. The value obtained by subtracting 1716 from the point where is generated corresponds to the phase error amount PE.

The calculating part 32 calculates and processes the phase error amount PE, and outputs the calculated result to the adder 34. To this end, the calculation unit 32 may be implemented as a tracking filter such as an infinite impulse response (IIR) filter. At this time, the calculation through the tracking filter is closely related to the lockup time. That is, the larger the value calculated by the operation unit 32 every line, the faster the lockup time becomes, but is sensitive to noise, and the smaller the calculated value is, the less sensitive to noise, but the lockup time is slowed. Here, the lockup time means a time required for the external horizontal synchronization signal to be synchronized with the system clock signal SCK.

The adder 34 adds a predetermined offset value OFFSET input from the outside to generate a free running frequency and a result calculated by the operation unit 32, and adds the added result freq to FIG. 1. Output to the discrete time oscillator 12 shown.

Meanwhile, the timing generator 38 generates an internal horizontal sync signal hsync having a period of 1716T by using the result counted by the pixel counter 36 and vertical serrated pulses extracted from the composite video image signal. The external vertical synchronizing signal Vsync is extracted by using the X, and the extracted external vertical synchronizing signal Vsync and the internal horizontal synchronizing signal hsync are output to the phase comparison section setting unit 40.

The phase comparison section setting unit 40 compares the result of counting the internal horizontal synchronization signal hsync output from the timing generator 38 with the second predetermined value, and corresponds to the result of the enable signal EN When the enable signal EN is generated, a value obtained by counting the internal horizontal synchronization signal hsync is output as a line counting value LCOUNT to the reset terminal RESET of the pixel counter 36. Here, the second predetermined value may have a value between 6 and 250. That is, the head switch pulse is input to a section of 250H to 6H (for 20H) (where H represents one period of the horizontal synchronization signal) in the case of NTSC, and the phase comparison section setting section 40 provides a phase comparison section during this section. It plays a role of controlling so that 30 does not operate.

To this end, the phase comparison section setting unit 40 includes a synchronization signal counter 50, a comparator 52, and a counter reset unit 54.

First, the synchronization signal counter 50 of the phase comparison section setting unit 40 performs a counting operation in response to the internal horizontal synchronization signal hsync input from the timing generator 38 through the clock terminal CK and counts. The result is output to the comparator 52 and the counter reset section 54, and is reset in response to the external vertical synchronizing signal Vsync input from the timing generating section 38 through the reset terminal RESET. At this time, the comparator 52 compares whether the result counted by the synchronization signal counter 50 is the second predetermined value, and generates the enable signal EN in response to the compared result. For example, the comparator 52 generates an enable signal EN of "low" logic level when the result counted in the sync signal counter 50 is a value between 5 and 250, and the counted result is 5 to 250. If it is not between, an enable signal EN of "high" logic level is generated. As such, when the enable signal EN is generated, the phase comparator 30 does not perform a phase comparison operation when the enable signal EN having a "high" logic level is input, and the phase error amount PE. Reset to '0'. Therefore, the value previously calculated by the calculating section 32 is added to the predetermined offset value OFFSET, and the added result freq is output to the discrete time oscillating section 12. However, the phase comparison unit 30 performs a phase comparison operation when the enable signal EN having a "low" logic level is input, and calculates the phase error amount PE generated in correspondence with the phase comparison operation. )

On the other hand, when the enable signal EN is switched from the "high" logic level to the "low" logic level, the pixel counter 36 returns to 1716 in response to the line counting value LCOUNT input to the reset terminal RESET. The initialized value 1716 is output to the phase comparison unit 30. Accordingly, since the phase comparator 30 outputs a value of 1716 from the pixel counter 36, the phase comparator 30 may output a phase error amount PE of '0' to the calculator 32. That is, after the operation of the phase comparator 30 is switched from the disable to the enable state, the phase error amount PE is maintained at '0' when the first external horizontal synchronization signal is input. To this end, the counter reset unit 54 outputs the counted result as the line counting value LCOUNT in response to the enable signal EN. That is, the counter reset unit 54 sets the value counted in the synchronization signal counter 50 as the line counting value LCOUNT when the enable signal EN transitions from the "high" logic level to the "low" logic level. Output to the pixel counter 36.

In conclusion, since the head switch pulse is generated in every field of the composite video image signal, when the digital tracking device 10 operates as in the related art, a phase comparison operation is performed in a section where the head switch pulse is generated, thereby causing a phase error amount. (PE) changes so rapidly that a lock-up time of about 50 horizontal lines is required for each field, so that the user can recognize the warpage at the top of the screen displayed on the television. On the other hand, since the apparatus according to the present invention shown in FIG. 2 stops the operation of the phase comparator 30 in the section in which the head switch pulse occurs, the device can be locked horizontally within 20 horizontal lines immediately after the head switch pulse occurs. This can solve the problem of the top of the screen is bent.

As described above, the digital tracking device according to the present invention is configured to disable the phase comparison operation in a section in which a head switch pulse exists that may cause a sudden phase change in every field when a composite video image signal is input. The lock-up speed of the synchronization signal may be improved to prevent the top of the displayed screen from bending.

Claims (3)

A pixel counter counting a system clock signal and reset to a first predetermined value in response to a line counting value; A phase comparator for comparing an external horizontal sync signal extracted from a composite video image signal with a counted result from the pixel counter in response to an enable signal and outputting the compared result as a phase error amount; An operation unit which calculates the phase error amount and outputs a result of the operation process; An adder which adds the calculated result and a predetermined offset value and outputs the added result; A timing generator for generating an internal horizontal sync signal using the result counted by the pixel counter and extracting an external vertical sync signal from the composite video image signal; And A value obtained by comparing the result of counting the internal horizontal synchronization signal with a second predetermined value, generating the enable signal according to the result of the comparison, and counting the internal horizontal synchronization signal at the time when the enable signal is generated; A phase comparison section setting section for outputting a signal as the line counting value, And the output of the adder is used to synchronize the system clock signal to the external horizontal synchronizing signal. The method of claim 1, wherein the phase comparison section setting unit A synchronization signal counter that counts the internal horizontal synchronization signal and resets in response to the external vertical synchronization signal; A comparator for comparing the result counted by the synchronization signal counter with the second predetermined value and generating the enable signal according to the compared result; And And a counter reset unit configured to output a result counted by the synchronization signal counter as the line counting value in response to the enable signal. The digital tracking device of claim 1, wherein the phase comparator initializes the phase error amount in response to the enable signal.