KR20010008559A - Method For Forming The Tungsten Polycide Layer - Google Patents
Method For Forming The Tungsten Polycide Layer Download PDFInfo
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- KR20010008559A KR20010008559A KR1019990026466A KR19990026466A KR20010008559A KR 20010008559 A KR20010008559 A KR 20010008559A KR 1019990026466 A KR1019990026466 A KR 1019990026466A KR 19990026466 A KR19990026466 A KR 19990026466A KR 20010008559 A KR20010008559 A KR 20010008559A
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- layer
- tungsten silicide
- gas
- polysilicon layer
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 43
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 16
- 239000010937 tungsten Substances 0.000 title claims abstract description 16
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 239000000126 substance Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract 4
- 238000004140 cleaning Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 7
- 239000000203 mixture Substances 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 2
- 239000007789 gas Substances 0.000 description 32
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract
Description
본 발명은 텅스텐폴리사이드층을 증착하는 방법에 관한 것으로서, 특히, 비트라인 혹은 게이트전극을 텅스텐폴리사이드층으로 형성할 때, 폴리실리콘층 상에 증착되는 텅스텐실리사이드층에 RF플라즈마를 발생하여 챔버 내부로 공급된 소오스가스를 활성화시켜 자연산화막과 반응시켜 자연산화막을 제거한 후 증착하도록 하는 텅스텐폴리사이드층 형성방법에 관한 것이다.The present invention relates to a method for depositing a tungsten polyside layer, in particular, when forming a bit line or a gate electrode as a tungsten polyside layer, the RF plasma generated in the tungsten silicide layer deposited on the polysilicon layer to the inside of the chamber The present invention relates to a method for forming a tungsten polyside layer by activating a source gas supplied to the reactor to react with a natural oxide film to remove the natural oxide film and then deposit the same.
일반적으로, 텅스텐폴리사이드층(Tungsten Polycide Layer)은 폴리사이드층에 연속 혹은 불연속적으로 텅스텐실리사이드층을 적층한 복합층으로서, 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존의 폴리실리콘층을 대체하여 게이트(Gate)와 비트라인(Bit Line)으로 사용되고 있는 실정이다.In general, a tungsten polycide layer is a composite layer in which a tungsten silicide layer is laminated continuously or discontinuously on a polyside layer. Instead, it is used as a gate and a bit line.
비저항이 낮고 전기전도도가 좋은 텅스텐실리사이드(WSiX)은 산화막과의 접착특성을 좋게하기 위하여 텅스텐실리사이드층을 증착하기 전에 도핑된 폴리실리콘층을 증착한 후에 연속 혹은 불연속적으로 텅스텐실리사이드층을 증착한다.Tungsten silicide (WSi X ), which has low resistivity and good electrical conductivity, deposits a tungsten silicide layer continuously or discontinuously after depositing the doped polysilicon layer before depositing the tungsten silicide layer to improve adhesion properties with the oxide film. .
즉, 텅스텐실리사이드층은 산화막과의 접착특성이 좋지 않기 때문에 이를 개선하기 위하여 텅스텐실리사이드층을 적층하기 전에 인(Phosphorus)이 도핑된 500 ∼ 1000Å의 두께를 갖는 폴리실리콘층을 적층하도록 한다.That is, since the tungsten silicide layer does not have good adhesion properties to the oxide film, in order to improve the tungsten silicide layer, a polysilicon layer having a thickness of 500 to 1000 kPa doped with phosphorus (Phosphorus) is laminated before the tungsten silicide layer is laminated.
도 1은 일반적인 트랜지스터의 게이트를 보인 도면으로서, 게이트를 형성하는 공정을 간략하게 살펴 보면, 반도체기판(1) 상에 게이트산화막(2), 폴리실리콘층(3), 게이트 전극의 역활을 하는 텅스텐실리사이드층(4) 및 반사방지산화막(5) 을 순차적으로 적층한 후 마스킹식각으로 게이트를 형성한다.FIG. 1 is a view illustrating a gate of a general transistor. In brief, a process of forming a gate includes tungsten, which serves as a gate oxide film 2, a polysilicon layer 3, and a gate electrode on a semiconductor substrate 1. The silicide layer 4 and the antireflective oxide film 5 are sequentially stacked, and a gate is formed by masking etching.
그리고, 게이트의 좌,우 양측에 스페이서산화막을 적층하여 블랭킷식각 (Blancket Etch)으로 라운드 형상의 스페이서막(6)을 형성한다.A spacer oxide film is stacked on both left and right sides of the gate to form a round spacer film 6 by blanket etching.
상기 게이트산화막(2)과 텅스텐실리사이드층(4)사이에 적층되는 폴리실리콘층(3)은 텅스텐실리사이드층(4)이 게이트산화막(2)에 접착되는 것을 용이하게 하는 역할을 하게 된다.The polysilicon layer 3 stacked between the gate oxide film 2 and the tungsten silicide layer 4 serves to facilitate the adhesion of the tungsten silicide layer 4 to the gate oxide film 2.
한편, 상기 폴리실리콘층(3)상에 텅스텐실리사이드층(4)을 적층하기 전에 미리 폴리실리콘층(3)의 상부면을 세정하는 공정을 거치게 되는 데, 이 공정을 살펴 보면, (a) 웨이퍼 표면의 유기 오염물질을 제거하기 위하여 황산(H2SO4)으로 세정하는 공정, (b) 웨이퍼의 표면에 존재하는 황산 용액의 잔류물을 70℃이상의 뜨거운 순수와 25℃의 순수를 이용하여 세정하는 퀵 덤프 린스(Quick Dump Rinse)세정공정, (c) 자연산화막을 제거하기 위한 불산계용액에 딥핑(Dipping)하는 공정, (d) 웨이퍼 표면에 존재하는 불산계용액 잔유물을 제거하기 위하여 오버플로우(Over Flow) 방식으로 D.I워터로 린싱(Rinsing)하는 공정, (e) 웨이퍼 표면에 존재하는 이물질 제거 및 웨트 케미컬(Wet Chemical)을 제거하는 최종 린싱(Final Rinsing)공정, (f) 웨이퍼 표면에 잔류하는 순수를 IPA건조기나 혹은 SPIN건조기를 사용하여 건조하도록 한다.Meanwhile, before laminating the tungsten silicide layer 4 on the polysilicon layer 3, a process of cleaning the upper surface of the polysilicon layer 3 is performed in advance. Looking at this process, (a) a wafer Washing with sulfuric acid (H 2 SO 4 ) to remove organic contaminants on the surface, (b) cleaning the residue of sulfuric acid solution on the surface of the wafer using hot and hot water above 70 ℃ and pure water at 25 ℃ Quick Dump Rinse cleaning process, (c) Dipping into hydrofluoric acid solution to remove native oxide film, (d) Overflow to remove hydrofluoric acid residue on wafer surface Process of rinsing with DI water by (Over Flow) method, (e) Final rinsing process of removing foreign substances on the wafer surface and removing wet chemical, (f) Surface of wafer Residual pure water is transferred to IPA dryer or Dry using a spin dryer.
그런데, 상기한 공정을 거쳐 폴리실리콘층(3) 상에 불연속적으로 텅스텐실리사이드층(4)을 증착하는 경우, 폴리실리콘층(3) 상의 오염물질 및 자연산화막을 제거하는 세정공정 중에 불산계 용액 처리 후에 제거되었던 자연산화막이 국부적으로 인이 고농도로 모여져 있는 위치에서 순수 세정 및 건조과정에서 인이 쉽게 옥시데이션 되면서, 자국으로 남겨지는 워터 마크(Water Mark)를 부분적으로 생성하게 되어 텅스텐실리사이드층(4) 적층 및 게이트 패터닝시 폴리실리콘층(3)과 텅스텐실리사이드층(4) 사이의 계면에 존재하는 워터 마크에 의하여 에치스톱(Etch Stop)을 유발하여 전극간에 브릿지 페일(Bridge Fail)을 발생하는 문제점을 지니고 있었다.However, in the case of depositing the tungsten silicide layer 4 discontinuously on the polysilicon layer 3 through the above-described process, a hydrofluoric acid solution during the cleaning process of removing contaminants and natural oxide films on the polysilicon layer 3 As the natural oxide film removed after the treatment is locally oxidized at a high concentration of phosphorus, phosphorus easily oxidizes during pure washing and drying, and partially produces a water mark that remains as a tungsten silicide layer. 4) Etch stop is caused by a water mark present at the interface between the polysilicon layer 3 and the tungsten silicide layer 4 during lamination and gate patterning to generate bridge fail between the electrodes. I had a problem.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 비트라인 혹은 게이트전극을 텅스텐폴리사이드층으로 형성할 때, 폴리실리콘층 상에 증착되는 텅스텐실리사이드층에 RF플라즈마를 발생하여 챔버 내부로 공급된 소오스가스를 활성화시켜 자연산화막과 반응시켜 자연산화막을 제거한 후 증착하므로 폴리실리콘층과 텅스텐실리사이드층 사이의 계면에 존재하는 워터마크를 제거하는 것이 목적이다.The present invention has been made in view of this point, and when the bit line or gate electrode is formed of a tungsten polyside layer, a source gas supplied into the chamber by generating an RF plasma on the tungsten silicide layer deposited on the polysilicon layer Since it is activated by reacting with the natural oxide film to remove the natural oxide film and then deposited, the object is to remove the watermark present at the interface between the polysilicon layer and the tungsten silicide layer.
도 1은 일반적인 트랜지스터의 게이트를 보인 도면이고,1 is a view showing a gate of a typical transistor,
도 2는 일반적인 챔버 및 플라즈마 발생장치를 도시한 도면이다.2 is a view illustrating a general chamber and a plasma generator.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체기판 2 : 게이트산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘층 4 : 텅스텐실리사이드층3: polysilicon layer 4: tungsten silicide layer
5 : 반사방지막 6 : 스페이서막5 antireflection film 6 spacer film
10 : 챔버 20 : 샤워헤드10 chamber 20 shower head
30 : 받침대 40 : 히이터30: pedestal 40: heater
50 : 회전축 60 : 플라즈마 발생수단50: rotation axis 60: plasma generating means
70 : 구동수단70: drive means
이러한 목적은 하부층 상에 SiH4가스와 PH3/SiH4의 혼합가스를 이용하여 인이 도핑된 폴리실리콘층 증착하는 단계와; 상기 단계 후에 연속하여 SiH4가스를 이용하여 인이 도핑되지 않은 폴리실리콘층을 증착하는 단계와; 상기 단계 후에 통상의 화학세정제를 사용하여 웨이퍼를 세정한 후 텅스텐실리사이드층을 적층하는 단계를 포함한 일실시예에 따른 텅스텐 폴리사이드층 형성방법을 제공함으로써 달성된다.This object comprises the steps of depositing a polysilicon layer doped with phosphorus using a mixed gas of SiH 4 gas and PH 3 / SiH 4 on the lower layer; Subsequently depositing a polysilicon layer that is not doped with phosphorus using SiH 4 gas after the step; After the step is achieved by providing a method of forming a tungsten polyside layer according to one embodiment comprising the step of laminating a tungsten silicide layer after cleaning the wafer using a conventional chemical cleaner.
그리고, 상기 인이 도핑된 폴리실리콘층은 550 ∼ 600℃의 온도범위에서 700 ∼ 750Å의 두께로 증착하고, 상기 인이 도핑되지 않은 폴리실리콘층은 520 ∼ 570℃의 온도범위에서 50 ∼ 100Å의 두께로 증착한다.The polysilicon layer doped with phosphorus is deposited to a thickness of 700 to 750 ° C. in the temperature range of 550 to 600 ° C., and the polysilicon layer which is not doped with phosphorus is 50 to 100 ° C. in the temperature range of 520 to 570 ° C. Deposit to thickness.
본 고안의 목적은 하부층 상에 SiH4가스와 PH3/SiH4의 혼합가스를 이용하여 인이 도핑된 폴리실리콘층 증착하는 단계와; 상기 단계 후에 통상의 화학세정제로 웨이퍼를 세정한 후 RF플라즈마(RF Plasma)를 이용하여 공급된 소오스가스(Source Gas)를 활성화시킨 후 웨이퍼상의 자연산화막(Native Oxide Layer)과 반응을 유발하여 제거하는 단계와; 상기 단계 후에 폴리실리콘층 상에 텅스텐실리사이드층을 적층하는 단계를 포함한 다른 실시예에 따른 텅스텐 폴리사이드층 형성방법을 제공함으로써 달성된다.An object of the present invention is the step of depositing a polysilicon layer doped with phosphorus using a mixed gas of SiH 4 gas and PH 3 / SiH 4 on the lower layer; After the step, the wafer is cleaned with a conventional chemical cleaner, and then activated by source gas supplied using RF plasma, and then reacted with a native oxide layer on the wafer to remove it. Steps; It is achieved by providing a method of forming a tungsten polyside layer according to another embodiment including the step of laminating a tungsten silicide layer on the polysilicon layer after the step.
이때, 상기 RF플라즈마의 파워는 50 ∼ 1000Watt이고, 상기 소오스가스는 CHF3, CF4, C2F6NF3가스중에 적어도 어느 하나 이상을 사용하며, 상기 세정공정을 진행할 때, 챔버 내부의 온도는 50 ∼ 100℃의 온도범위에서, 5mTorr ∼ 1000mTorr의 압력으로 진행하며, 상기 세정공정을 진행할 때, 웨이퍼를 10 ∼ 100RPM으로 회전시키는 것이 바람직 하다.At this time, the power of the RF plasma is 50 ~ 1000Watt, the source gas is used at least any one of CHF 3 , CF 4 , C 2 F 6 NF 3 gas, when the cleaning process, the temperature inside the chamber In the temperature range of 50 ~ 100 ℃, proceeds with a pressure of 5mTorr ~ 1000mTorr, when the cleaning process, it is preferable to rotate the wafer to 10 ~ 100RPM.
그리고, 상기 RF플라즈마 세정공정과 후속 텅스텐실리사이드층 증착공정은 인-시튜공정(In-Situ Process)으로 진행하고, 상기 텅스텐실리사이드층은 350 ∼ 450 ℃의 온도범위에서 적층하도록 한다.The RF plasma cleaning process and the subsequent tungsten silicide layer deposition process are performed in an in-situ process, and the tungsten silicide layer is laminated in a temperature range of 350 to 450 ° C.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 일실시예에 대하여 상세히 살펴보도록 한다.Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 폴리실리콘층 상에 불연속적으로 텅스텐실리사이드층을 적층하는 워드라인과 비트라인을 형성하는 반도체 소자 형성공정에서, 하부층 상에 SiH4가스와 PH3/SiH4의 혼합가스를 이용하여 550 ∼ 600℃의 온도범위에서 700 ∼ 750Å의 두께로 인이 도핑된 폴리실리콘층 증착한다.First, in the semiconductor device forming process of forming a word line and a bit line for discontinuously stacking a tungsten silicide layer on a polysilicon layer, a mixture gas of SiH 4 gas and PH 3 / SiH 4 is used on the lower layer. Phosphorus-doped polysilicon layer is deposited to a thickness of 700 to 750 kPa over a temperature range of 600 ° C.
그리고, 상기 단계 후에 연속하여 SiH4가스를 이용하여 520 ∼ 570℃의 온도범위에서 50 ∼ 100Å의 두께로 인이 도핑되지 않은 폴리실리콘층을 증착한다.Subsequently, after the step, a silicon-doped polysilicon layer is deposited to a thickness of 50 to 100 kPa in a temperature range of 520 to 570 ° C using SiH 4 gas.
그리고, 상기 단계 후에 통상의 화학세정제(Wet Chemical)를 사용하여 웨이퍼를 세정한 후 텅스텐실리사이드층을 적층한다.After the step, the wafer is cleaned using a conventional chemical cleaner (Wet Chemical), and then a tungsten silicide layer is laminated.
한편, 본 발명의 다른 실시예에 따른 텅스텐폴리사이드층 형성방법을 살펴 보도록 한다.Meanwhile, the tungsten polyside layer forming method according to another embodiment of the present invention will be described.
도 2는 일반적인 챔버 및 플라즈마 발생장치를 도시한 도면으로서, 도면을 참조하여 워드라인 및 비트라인용으로 적층되는 살펴보도록 한다.FIG. 2 is a diagram illustrating a general chamber and a plasma generating apparatus, which will be described with reference to the drawings.
웨이퍼의 하부층 상에 SiH4가스와 PH3/SiH4의 혼합가스를 이용하여 인이 도핑된 폴리실리콘층 증착하도록 한다.Phosphorus-doped polysilicon layer is deposited using a mixed gas of SiH 4 gas and PH 3 / SiH 4 on the lower layer of the wafer.
상기 단계 후에 통상의 화학세정제로 웨이퍼를 세정한 후 웨이퍼(A)를 챔버 (10)의 받침대(30)상에 안치시킨 후에 RF플라즈마 발생수단(60)에서 발생된 RF플라즈마를 이용하여 소오스가스유입구(12)를 통하여 유입되고, 샤워헤드(20)에서 균일하게 공급되는 소오스가스를 활성화시킨 후 웨이퍼상의 자연산화막과 반응을 유발하여 제거하도록 한다.After the above steps, the wafer is cleaned with a conventional chemical cleaner, and the wafer A is placed on the pedestal 30 of the chamber 10, and then the source gas inlet is formed using the RF plasma generated by the RF plasma generating means 60. After flowing through 12 and activating the source gas uniformly supplied from the shower head 20, it reacts with the natural oxide film on the wafer to remove it.
상기 RF플라즈마의 파워는 50 ∼ 1000Watt이고, 소오스가스는 CHF3, CF4, C2F6NF3가스중에 적어도 어느 하나 이상을 사용하고, 세정공정을 진행할 때, 챔버 내부의 온도는 50 ∼ 100℃의 온도범위에서, 5mTorr ∼ 1000mTorr의 압력으로 진행한다.The RF plasma power is 50 to 1000 Watts, the source gas is at least any one of CHF 3 , CF 4 , C 2 F 6 NF 3 gas, when the cleaning process, the temperature inside the chamber is 50 ~ 100 In the temperature range of ℃, it proceeds with a pressure of 5mTorr ~ 1000mTorr.
그리고, 상기 세정공정을 진행할 때, 웨이퍼(A)를 안치한 받침대(30)를 구동수단(70)에 의하여 회전하는 회전축(50)을 사용하여 식각균일도를 좋게 하기 위하여 10 ∼ 100RPM으로 회전시키면서 공정을 진행하도록 하고, 받침대(30)는 히이터 (40)에 의하여 골고루 히이팅 된다.When the cleaning process is performed, the process is performed while the pedestal 30 having the wafer A placed thereon is rotated at 10 to 100 RPM in order to improve the etching uniformity using the rotation shaft 50 rotating by the driving means 70. To proceed, the pedestal 30 is evenly heated by the heater 40.
상기 RF플라즈마 세정공정과 후속 텅스텐실리사이드층 증착공정은 인-시튜공정으로 진행할 수 있으며, NF3소오스가스를 사용할 때, 인시튜 공정을 상세하게 살펴 보면, 챔버(10) 내부의 온도를 낮춘 후에 웨이퍼(A)를 받침대(30)에 안치시키도록 한다.The RF plasma cleaning process and the subsequent tungsten silicide layer deposition process may be performed in-situ process. When using NF 3 source gas, the in-situ process is described in detail. (A) is placed on the pedestal (30).
상기 NF3소오스가스를 공급하여서 안정화(Stabilization)시키고, RF프라즈마 발생수단(60)에 플라즈마를 발생한 후 소정시간 경과하여 플라즈마를 오프하고, NF3소오스가스의 공급을 차단하도록 한다.Stabilization by supplying the NF 3 source gas, the plasma is turned off after a predetermined time after the plasma is generated in the RF plasma generating means 60, and the supply of the NF 3 source gas is cut off.
그리고, 아르곤가스를 온 시켜 공급하여 히이터(40)를 작동하여 받침대(30)의 온도를 상승시킨 후 아르곤가스의 공급을 차단하고, SiH4가스를 유동시키도록 한다.Then, the argon gas is turned on and supplied to operate the heater 40 to raise the temperature of the pedestal 30, to cut off the supply of argon gas, and to flow the SiH 4 gas.
그리고, SiH4/WF6혼합가스를 공급하고, SiH4/가스를 먼저, 차단하고, 연이어 WF6가스를 차단하도록 한 후 챔버(10)의 온도를 낮춘 후에 웨이퍼를 외부로 인출하도록 한다.Then, the SiH 4 / WF 6 mixed gas is supplied, the SiH 4 / gas is first blocked, the WF 6 gas is subsequently blocked, and the temperature of the chamber 10 is lowered, and then the wafer is taken out.
이와 같이. 폴리실리콘층 상에 텅스텐실리사이드층을 인-시튜공정으로 적층하도록 한다.like this. The tungsten silicide layer is deposited on the polysilicon layer by an in-situ process.
상기 텅스텐실리사이드층을 적층 할 때, 사용되는 소오스가스는 SiCl2H2혹은 SiH4가스와 WF6 가스를 1 ∼ 2.9 : 1.7 ∼ 3.2 의 혼합비율로 사용하고, 350 ∼ 450 ℃의 온도범위에서 진행하도록 한다.When stacking the tungsten silicide layer, the source gas used is SiCl 2 H 2 or SiH 4 gas and WF6 gas in a mixing ratio of 1 to 2.9: 1.7 to 3.2, and proceed in a temperature range of 350 to 450 ℃ do.
따라서, 상기한 바와 같이, 본 발명에 따른 텅스텐폴리사이드층 형성방법을 이용하게 되면, 비트라인 혹은 게이트전극을 텅스텐폴리사이드층으로 형성할 때, 폴리실리콘층 상에 증착되는 텅스텐실리사이드층에 RF플라즈마를 발생하여 챔버 내부로 공급된 소오스가스를 활성화시켜 자연산화막과 반응시켜 자연산화막을 제거한 후 증착하므로 폴리실리콘층과 텅스텐실리사이드층 사이의 계면에 발생되는 워터마크의 발생을 차단하고, 결국에는 에치스톱(Etch Stop)을 억제하여 패턴형성을 향상시키므로 반도체소자의 전기적인 특성을 증대시킬 뿐만 아니라 소자의 수율을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the tungsten polyside layer forming method according to the present invention is used, an RF plasma is formed on the tungsten silicide layer deposited on the polysilicon layer when the bit line or the gate electrode is formed of the tungsten polyside layer. To activate the source gas supplied into the chamber, react with the natural oxide film to remove the natural oxide film, and then deposit it to block the generation of watermarks generated at the interface between the polysilicon layer and the tungsten silicide layer, and eventually etch stop. It is a very useful and effective invention to improve the yield of the device as well as to increase the electrical properties of the semiconductor device by suppressing the (Etch Stop) to improve the pattern formation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100455847B1 (en) * | 2001-12-29 | 2004-11-06 | 주식회사 하이닉스반도체 | Method of forming a gate electrode in semiconductor device |
| KR100617068B1 (en) * | 2005-07-12 | 2006-08-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100455847B1 (en) * | 2001-12-29 | 2004-11-06 | 주식회사 하이닉스반도체 | Method of forming a gate electrode in semiconductor device |
| US6818506B2 (en) | 2001-12-29 | 2004-11-16 | Hynix Semiconductor Inc. | Method of forming a gate electrode in a semiconductor device |
| KR100617068B1 (en) * | 2005-07-12 | 2006-08-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing of semiconductor device |
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