TW471079B - Surface treatment method of bit line conductive layer - Google Patents

Abstract

A surface treatment method of bit line conductive layer is disclosed, which comprises: first, providing a bit line contact diffusion layer formed on a semiconductor substrate inside it; forming a dielectric layer on this substrate; forming a bit line contact plug in this dielectric layer and contacting one surface of this bit line contact layer; forming a conductive layer on this dielectric layer and bit line contact plug; etching the pattern of this conductive layer; and finally applying plasma etching to this pattern-etched conductive layer. After oxygen plasma processing, the charge will distribute uniformly on the surface of this conductive layer, and won't be concentrated on a specific surface. Therefore, since the remained etching gas won't be absorbed and concentrated on this specific surface during the formation of bit line contact plug, it is able to prevent the bit line formed by this conductive layer from being etched and broken.

Description

V. Description of the invention (1) ~ ----< 5-1 Field of invention: The present invention relates to a semi-dynamic random access memory (dynamT body I process; in particular, it relates to a method of manufacturing a piece) 1C random access memory) 5-2 Background of the Invention: Dynamic random access memory cells (pcs. These devices provide temporary storage (Ce1)) are a well-known semiconductor cell system, such as a computer. According to the device, it is usually used in digital DRAM products due to the intense competition in the DRAM market. To reduce the holiday ::: It is necessary for the manufacturer to reduce it and increase the integrated circuit memory.

Small brings the semiconductor technology: the size, the shrinkage of these circuit patterns, the manufacture of the circuit brings this; θ ° § And, the reduced geometric structure in DRAM

2—Manufacturing problems are exemplified in Section III, and a. Semi-finished products of conventional DRAM components. In @ j ^ ^ Mouth, Feng Fu, Washing light and replacing P-type monocrystalline stone this / its style is wide. The RAM cell contains a substrate 11 which is typically composed of the open pole ^ of the NMOS transistor. 2 And -guan 0S transistor K, its pole is used as a word line. NM0S transistor

I. V. Description of the invention (2) The bit line contact diffusion layer is used. The force / primary / drain 1 4 series is connected to a Lei Liu stored charge in the memory cell ... polycrystalline silicon: (not shown in the figure) 'for a dielectric contact plug 16 series located above the substrate 11 The surface of the contact diffusion layer 13 is formed. Do more than two and do it against this bit line. The silicon bit contacts above the plug. Polycrystalline slab = line 17 is formed in this polycrystal and is connected to the charge storage region of the storage capacitor. ;: 2: 7 By looking at the transistor 12 spar xi bit line Π, ㈣ polycrystalline sac contact: = 二 胄, 胄 charge-start from the multi-contact diffusion layer 13 and enter the storage capacitor. Soil 16, and then pass through the bit line ~ In order to form a polycrystalline silicon bit line contact plug, the technology is formed-self-aligned contact ^ 2 bit line contacts the surface of the diffusion layer 13. After: η:; :: Snow 屛 1 u αα The core deposits a polycrystalline silicon layer on the detached worm column, and then aligns itself with the contact window hole, and then uses reactive gas instead of HBr, ⑽Ηπ The mixed gas is used to cook the bit impurity f 'to etch this polycrystalline silicon layer. 11 * Dagger to obtain this polycrystalline Hfl J plug 16. During the etching, the etching gases HBr, Cl 戌 and ^ are adsorbed on the exposed substrate 11 in the self-aligned contact hole. The surface of the polycrystalline silicon bit line 17 that is formed next is not subjected to any treatment, and it is likely that the second charge will be concentrated on a specific surface area. With these residues, the wonderfully engraved gas will be attracted and concentrated on the surface area of the charge accumulation. The surname engraved the polycrystalline stone bit line 17, which makes part of the polycrystalline stone bit two & dagger, 'Even a broken line, this phenomenon is very likely to occur near the bit line contact " as shown by the dashed line in the first picture and in the second picture A and the second picture B

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Page 5 471079 V. Description of the invention (3). Accordingly, there is an urgent need to provide a method for treating the surface of the bit line conductive layer, which can overcome the shortcomings faced by the conventional technology. 5 _3 Purpose and summary of the invention: The main object of the present invention is to provide a method for treating the surface of a bit line conductive layer, wherein an oxygen plasma is applied to the surface of the bit line conductive layer so that the charge can be more Evenly distributed on the surface of the bit line conductive layer. Thereby, the etching gas remaining when a bit line contact plug is formed will not be attracted and concentrated on a specific surface area of the bit line conductive layer. Therefore, it is possible to prevent the conductive layer of the bit line from being engraved and broken. Another object of the present invention is to provide a method for treating the surface of a bit line conductive layer, wherein an oxygen plasma is applied to the surface of an anti-reflection layer located above the bit line conductive layer, so that the charge can be more Evenly distributed on the surface of this anti-reflection layer. Thereby, when the bit line contact plug is formed, the remaining etching gas will not be attracted and concentrated on a specific surface area of the anti-reflection layer. Therefore, the bit line conductive layer can be prevented from being disconnected due to being engraved for 4 minutes.

471079 V. Description of the invention (4) According to the above-mentioned purpose, at least a layer of a surface treatment method for a layer is formed over one of the semiconductor substrates therein. Then, a conductive layer contacting the bit line is formed on the dielectric layer and the substrate includes a bit line connected to the first conductive layer. One surface of the last conductive layer is evenly distributed on the first conductive layer. Therefore, this bit of the interstitial layer formed by the body will not be absorbed by the electric layer, and is given. The bit line that is concentrated in this one through the contact of the bit line is broken. A line is connected to the oxygen and oxygen surfaces, and the plugs are specifically provided with a contact surface. However, the contact plug is treated with slurry without forming the surface. One kind of bit has a dielectric wire and a conductive wire connection layer is electrically expanded based on this dielectric layer, and then a first conductive layer is formed. Up. After the drawing, the charge will be concentrated in a specific, and the remaining etch can be etched to prevent the etching of the relatively uniform surface at the moment. This guides the purpose and many advantages of the present invention through the following specific examples. Detailed description, and referring to the attached drawings, will become clear. 5-4 Detailed description of specific embodiments: As mentioned above, in order to avoid charge concentration on a specific surface area of a bit line conductive layer, the present invention applies oxygen electroforging to the bit line conductive layer. surface. The third figure is a flowchart of the method of the present invention. The fourth figure is a partial cross-sectional view of a DRAM cell of one of the inventions, in which an oxygen plasma treatment is applied to the top surface of the DRAM cell of the fourth figure.

471079 V. Description of the invention (5) First, 'step 3 1' is performed to provide a semiconductor substrate 41, a dielectric layer 42 is formed over it 'and a bit line contact window hole penetrates this dielectric layer 42. This semiconductor substrate 41 is typically formed of a p-type single crystal. It also includes an NMOS transistor 43 formed therein. The gate of this QS transistor 4 3 is used to make a word line of this DRAM cell, and its source / pole 4 4 is used to make a single line to contact the diffusion layer (层 丨 t 1 丨 ne). contact diffusion layer), the other source / drain 4 5 is connected to a residual capacitor (not shown). The dielectric layer 42 may be a silicon dioxide layer formed by a conventional chemical vapor deposition method. The bit line contact opening is made by the traditional lithography and etching technology-self-alig two ontact opening. Then 'step 3 2 is performed to deposit a first conductive layer Above the dielectric layer 42 to fill the bit line contact window hole. The first conductive layer may be a polycrystalline layer formed by a conventional chemical vapor deposition method, such as a low pressure chemical vapor deposition method.

Next, step 3 3 is performed, and the first conductive layer is anisotropically etched to form a one-bit line contact plug 4 6. When the first conductive layer is formed of polycrystalline silicon, the polycrystalline silicon layer can be formed by reactive ion etching using a mixed gas of HBr, C 1 and HC 1 as an etching gas, and the polycrystalline silicon bit line contact is formed by anisotropic etching. Plug.

471079 V. Description of the invention (6) Lamination of the 4th method Essence sinking ο Electrical phase ο Conducting gas ο Two studies I—I first reduce the pressure. The low-thickness square is the same as above, the product 2 method sinks 4 products, and the layer sinks 4 electrical phases. 3 The gas layer is a dream that walks through the multiple advances and unifications of the chemical crystal line 7. The subsequentity of the layer transmission is the electrical conductivity in the form of a conductive element. 7 Next, proceed to step 3 5 using traditional lithography. And an etching technique, the second conductive layer 47 is pattern-etched to form a bit line. When the second conductive layer 47 is formed of polycrystalline silicon, a mixed gas of HBr, C1, and HC1 can be used as an etching gas, and an anisotropic etching is performed by a reactive ion etching method to form a polycrystalline silicon bit line. . Finally, step 36 is performed, and an oxygen plasma treatment is applied to the surface of the patterned second conductive layer 47. This oxygen plasma treatment uses oxygen (Oz) to provide oxygen ions, and its flow rate is about 3000 ~ 4200sccm; where 0 dissociates into 0+ + e_ + 0 *, 0 is a 0 molecular complex, some are positively charged and some are negatively charged And some are uncharged. This oxygen plasma treatment is performed under the conditions of a power of about 60 0 ~ 800 watts, a temperature of about 250 ° C and a pressure of about 1.1 ~ 1.31 〇rr, and the processing time is about 30 seconds ~ 60 seconds. In addition, after step 35, step 37 can be performed before oxygen plasma treatment. At step 37, an anti-reflective coating 49 having a thickness of about 400 angstroms is formed over the second conductive layer 47 which is etched by the pattern I. Then, the oxygen plasma treatment is applied here

Page 9 471079 V. Description of the invention (7) On the surface of the anti-reflection layer 49. The anti-reflection layer 49 can be a silicon oxynitride layer, which can be deposited by plasma chemical vapor deposition using Si Η 4, N 20 and N as a reaction gas. The formed layer 1 can be approximately silicon, and the crystallinity is so thick. * 1 S 4 W is reduced to helium tungsten, and the number of silicided intergranular fragments is as large as 9 to 4, 4 7 8 layers 4 4 The sexual anti-electricity and the conductive layer are much more diverse. This resistance ο to electricity. Finally, after step 37 is completed, step 3 8 is performed, and the same oxygen plasma treatment as described above is applied to the surface of the anti-reflection layer 49. When the oxygen plasma treatment is applied to the surface of the bit line conductive layer 47 or the surface of the antireflection layer 49. The charge will be distributed more evenly on the surface treated with oxygen plasma without concentrating on a specific surface area. Therefore, the remaining etching gases HBr, C1, and HC1 are not attracted and are concentrated on a specific surface, so that the bit line conductive layer is not etched, thereby preventing the bit line from being disconnected. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.

Page 10471079 The diagram is briefly explained. The first diagram depicts a partial cross-sectional view of a conventional DRAM cell. The second diagram A and the second diagram B are partial top views of the first diagram, which respectively show the bit line contact plugs. The polycrystalline silicon bit lines near the plug are thinned or even broken. The third figure is a flowchart of the method of the present invention; and the fourth figure is a partial cross-sectional view of a DRAM cell according to the present invention. Symbols of main parts: 1 1 semiconductor substrate 1 2 NMOS transistor 1 3 source / drain 1 4 source / drain 1 5 dielectric layer 1 6 polycrystalline silicon contact plug 1 7 polycrystalline silicon layer 4 1 semiconductor Substrate 4 2 Dielectric layer 4 3 NMOS transistor 4 4 Source / inverter 4 5 Source / drain 4 6-bit line contact plug

Page 11 471079

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Claims (1)

471079 VI. Application Patent Scope 1. A method for treating the surface of a bit line conductive layer, which at least comprises: providing a semiconductor substrate having a bit line contact diffusion layer formed therein; and forming a dielectric layer on the bit line Above the substrate; forming a bit line contact plug in the dielectric layer and contacting one surface of the bit line contact diffusion layer; forming a first conductive layer on the dielectric layer and the bit line contact plug Over the plug; pattern etching the first conductive layer; and applying an oxygen plasma treatment on a surface of the first conductive layer subjected to the pattern etching. 2. The method according to item 1 of the patent application, wherein the above-mentioned dielectric layer comprises a silicon dioxide layer. 3. The method according to item 1 of the patent application scope, wherein the bit line contact plug described above comprises a polycrystalline stone plug. 4. The method according to item 1 of the scope of patent application, wherein the step of forming the bit line contact plugs includes at least pattern etching the dielectric layer and forming a second conductive layer. The patterned etching layer is the dielectric layer. And etching the second conductive layer anisotropically until the dielectric layer is exposed. 5. For the method of applying for item 3 of the patent scope, the above-mentioned bit line contact plug Page 13 471079 VI. Scope of patent application Phase, gas. The layer of the interlayer should be low and the layer should be exposed and the remaining layer should be directly etched. The layer is engraved with silicon on the contact layer. The silicon is a picture. The package is included. The package is included. Step-by-step formation and non-deposition and plugging method. 6. The method of item 5 in the scope of patent application, wherein the first polycrystalline sand layer is a reactive ion etching method using HBr, C 1 and HC 1 The mixed gas is used as an etching gas to perform this anisotropic etching. 7. The method of claim 1 in the scope of patent application, wherein the first conductive layer includes a second polycrystalline layer. 8. The method according to item 1 of the scope of patent application, wherein the first conductive layer pattern etching step includes at least a lithography and etching process. 9. The method according to item 7 of the scope of patent application, wherein the above-mentioned second polycrystalline stone layer pattern etching step includes at least a lithography and etching process, and the etching process uses a reactive ion etching method using HBr, C 1 A mixed gas of HC1 and HC1 is used as an etching gas to perform anisotropic etching. 10. The method according to item 1 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen (02), and the flow rate is about 3 0 0 to 4 2 0 seem. 1 1. The method according to item 1 of the patent application range, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. Page 14 471079 VI. Application scope of patent 1 2. The method of item 1 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is carried out under a pressure of about 1.1 to 1.3 Torr. 13. The method according to item 1 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment has a processing time of about 30 seconds to 60 seconds. 1 4 · The method according to item 1 of the patent application range, wherein the above-mentioned oxygen plasma treatment is performed at a power of about 60 0 ~ 80 0 watts, a temperature of about 2 5 Ot, and a pressure of about 1. 1 ~ 1. 3 Torr Under the conditions, the processing time is about 30 seconds to 60 seconds. 15. The method according to item 1 of the scope of patent application, wherein an anti-reflection layer is formed on the first conductive layer before the oxygen plasma treatment is performed. 1 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned anti-reflection layer comprises a silicon oxynitride layer (silicon oxynitride) 0 1 7. The method according to item 16 of the scope of patent application, wherein the above The silicon oxynitride layer is formed by plasma chemical vapor deposition using Si Η 4, N 20 and N as reaction gases. 1 8. The method according to item 15 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen (02), and the flow rate is about 3 0 0 0 ~ 4 2 0 seem. Page 15 471079 VI. Application for patent scope 1 9. The method according to item 15 of the patent application scope, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 2 0. The method according to item 15 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1 to 1.3 Torr. 2 1 · The method according to item 15 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. 2 2. The method according to item 15 of the scope of patent application, wherein the above-mentioned oxygen plasma || system is at a power of about 60 0 ~ 80 0 watts, a temperature of about 250 ° C and a pressure of about 1.1 It is carried out under conditions of ~ 1, 3 Torr, and its processing time is about 30 seconds to 60 seconds. 2 3. The method according to item 16 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen (02), and the flow rate is about 3 0 0 to 4 2 0 seem. 24. The method according to item 16 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 2 5 · The method according to item 16 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1 to 1.3 Torr. 2 6. The method according to item 16 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. Page 16 471079 VI. Application for patent scope 2 7. The method of applying for patent scope No. 16 wherein the above-mentioned oxygen plasma treatment is performed at a power of about 60 0 ~ 80 0 watts and a temperature of about 250 ° C And the pressure is performed under the conditions of about 1.1 to 1.3 Torr, and the processing time is 30 seconds to 60 seconds. 2 8. The method of claim 7 in the scope of patent application, wherein before the oxygen plasma treatment is performed, an anti-reflection layer is formed on the second polycrystalline silicon layer. 29. The method according to item 28 of the scope of patent application, wherein the above-mentioned anti-reflection layer includes a silicon oxynitride layer. 30. The method according to item 28 of the scope of patent application, wherein the above silicon oxynitride layer is formed by plasma chemical vapor deposition using Si Η 4, N 20 and N as reaction gases. 3 1. The method according to item 28 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment uses oxygen (02) to provide oxygen ions, and the flow rate is about 3 0 0 to 4 2 0 seem. 3 2. The method according to item 28 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 3 3. The method according to item 28 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1 to 1.3 Torr. Page 17 471079 VI. Application scope of patent 34. The method of item 28 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. 35, such as the method of claim 28 in the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a power of about 60 0 ~ 80 0 watts, a temperature of about 2 50 ° C and a pressure of about 1.1 ~: L Under the condition of 3 Torr, the processing time is about 30 seconds to 60 seconds. 36. The method according to item 29 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen, and the flow rate is about 3 0 0 to 4 2 0 Osc cm. 37 7. The method according to item 29 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 3 8. The method according to item 29 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1 to 1.3 Torr. 39. The method according to item 29 of the patent application range, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. 40. The method according to item 29 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a power of about 60 0 ~ 80 0 watts, a temperature of about 2 50 ° C, and a pressure of about 1.1 ~ 1. Under the condition of 3 Torr, the processing time is about 30 seconds to 60 seconds. 41. A method for processing the surface of a polycrystalline silicon bit line, comprising at least ... Page 18 471079 6. The scope of the patent application provides a semiconductor substrate having a bit line contact diffusion layer formed therein; forming a dielectric layer over the substrate; forming a polycrystalline silicon bit line contact plug in the dielectric And forming a first polycrystalline silicon layer on the dielectric layer and the polycrystalline silicon bit line contact plug in the electrical layer and in contact with one surface of the bit line in contact with the diffusion layer; pattern etching the first A polycrystalline silicon layer to form the polycrystalline silicon bit line; and applying an oxygen plasma treatment on the surface of the polycrystalline silicon bit line. Round. Fan Lili's specialization of silicon requires the application of two-for-one method. The method includes 2 4 packages and 41 items. The above dielectric layer is 43. For the method of patent application No. 41, the above polycrystalline silicon bit line is included. The contact plug formation step includes at least pattern etching the dielectric layer and forming a second polycrystalline silicon layer on the dielectric layer by pattern etching using a low pressure chemical vapor deposition method, and using reactive ion etching using HBr A mixed gas of C1, C1 and HC1 is used as an etching gas, and the second polycrystalline silicon layer is etched until the dielectric layer is exposed. 4. The method according to item 41 of the scope of patent application, wherein the first polycrystalline stone layer pattern etching step includes at least a lithography and etching process, and the etching process uses a reactive ion etching method using HBr, A mixed gas of C 1 戌 HC 1 is used as an etching gas to perform anisotropic etching. Page 19,471079 VI. Patent Application Range 45. For the method according to item 41 of the patent application range, wherein before the above-mentioned oxygen plasma treatment is performed, a silicon oxynitride anti-reflective layer is formed on the first polycrystalline silicon first. On the floor. 4 6. The method according to item 41 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen (02), and the flow rate is about 3000 to 4200 sccm. 4 7. The method according to item 41 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 4 8. The method according to item 41 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1L 3 Torr. 49. The method according to item 41 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. 50, such as the method of claim 41 in the scope of patent applications, wherein the above-mentioned oxygen plasma treatment is performed at a power of about 60 0 ~ 80 0 watts, a temperature of about 2 5 (TC and pressure of about 1.1 ~ 1.3 The processing time is about 30 seconds to 60 seconds under the conditions of a torch. 5 1. The method according to item 45 of the patent application range, wherein the above-mentioned oxygen plasma treatment is to provide oxygen ions with oxygen (0 2), Its flow rate is about 3000 ~ 4200sccm. Page 20 471079 VI. Application scope of patent 5 2. The method according to item 45 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a temperature of about 250 ° C. 5 3 · The method according to item 45 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed under a pressure of about 1.1 to 1.3 Torr. 54. The method according to item 45 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment processing time is about 30 seconds to 60 seconds. 5 5. The method according to item 45 of the scope of patent application, wherein the above-mentioned oxygen plasma treatment is performed at a power of about 6 0 ~ 80 0 watts, a temperature of about 2 50 ° C, and a pressure of about 1. bu 1.3. The processing time is about 30 seconds to 60 seconds.