KR20010005150A - Method of fabricating capacitor of semiconductor device using top surface image process by silylation - Google Patents

Method of fabricating capacitor of semiconductor device using top surface image process by silylation Download PDF

Info

Publication number
KR20010005150A
KR20010005150A KR1019990025948A KR19990025948A KR20010005150A KR 20010005150 A KR20010005150 A KR 20010005150A KR 1019990025948 A KR1019990025948 A KR 1019990025948A KR 19990025948 A KR19990025948 A KR 19990025948A KR 20010005150 A KR20010005150 A KR 20010005150A
Authority
KR
South Korea
Prior art keywords
photoresist
etching
mask
forming
capacitor
Prior art date
Application number
KR1019990025948A
Other languages
Korean (ko)
Other versions
KR100349697B1 (en
Inventor
조성윤
이진욱
Original Assignee
김영환
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업 주식회사 filed Critical 김영환
Priority to KR1019990025948A priority Critical patent/KR100349697B1/en
Publication of KR20010005150A publication Critical patent/KR20010005150A/en
Application granted granted Critical
Publication of KR100349697B1 publication Critical patent/KR100349697B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided to ensure a charge storage capacitance of a large-capacity by using a silylation of a photoresist layer, using a polymer generated in etching the photoresist layer, and forming a cylinder-type charge storage electrode. CONSTITUTION: A conductive layer for forming a charge storage electrode is formed on a semiconductor substrate. The first photoresist layer(3) is deposited on the conductive layer, its surface part is selectively light-exposed according to a predetermined mask pattern, and then a silylation is performed. The second photoresist layer(4) is deposited on the first photoresist layer, its surface part is selectively light-exposed according to a predetermined mask pattern, and then a silylation is performed. The silylation part of the second photoresist layer is used as a mask, and the first and second photoresist layers are etched. A polymer sidewall is formed on a side of the etched photoreisist layer pattern. The conductive layer positioned to a polymer sidewall outer part is partially etched by using the photoresist pattern and the polymer sidewall as a mask. The first and second photoresist layers are etched by using the silylation part of the first photoresist layer as a mask. The polymer sidewall is formed on a side of the etched photoresist pattern. The residual photoresist layer is removed. The conductive layer of a predetermined thickness is etched by using the polymer sidewall as a mask. The residual polymer is removed.

Description

실릴레이션에 의한 패턴묘사를 이용한 반도체소자의 커패시터 형성방법{Method of fabricating capacitor of semiconductor device using top surface image process by silylation}Method for fabricating capacitor of semiconductor device using top surface image process by silylation}

본 발명은 TIPS(top surface image process by silylation)를 이용한 반도체소자의 커패시터 형성방법에 관한 것으로, 감광막을 이층으로 코팅하고 폴리머를 이용하여 실린더형 커패시터를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device using top surface image process by silylation (TIPS). The present invention relates to a method of forming a cylindrical capacitor by coating a photoresist with two layers and using a polymer.

반도체 메모리소자의 고집적화로 인해 소자의 설계마진이 감소함에 따라 큰 전하저장용량값을 가지는 커패시터에 대한 필요성이 더욱 높아지고 있다. 이를 충족시키기 위한 방법은 크게 두가지로 나눌 수 있다. 첫째는 고유전상수값을 갖는 강유전체의 개발이고, 둘째는 커패시터의 물리적 형상 변화를 통한 커패시터의 전극면적 증대이다. 특히 전극의 면적을 증대시키기 위한 많은 연구가 이루어졌으나, 집적도가 높아짐에 따라 기존의 커패시터 형상으로는 충분한 전하저장이 어려운 실정이다.As the design margin of the device decreases due to the high integration of semiconductor memory devices, the need for a capacitor having a large charge storage capacity value is increasing. There are two ways to meet this problem. The first is the development of ferroelectric with high dielectric constant, and the second is the increase in the electrode area of the capacitor through the change in the physical shape of the capacitor. In particular, many studies have been made to increase the area of the electrode, but as the degree of integration increases, it is difficult to store sufficient charge in a conventional capacitor shape.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 이중층의 감광막을 사용한 TIPS에 의해 보다 큰 전하저장용량을 갖는 실린더구조의 커패시터를 형성하는 방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method for forming a capacitor having a larger charge storage capacity by TIPS using a double layer photosensitive film.

상기 목적을 달성하기 위한 본 발명의 TIPS를 이용한 반도체소자의 커패시터 형성방법은 반도체기판상에 커패시터 전하저장전극 형성을 위한 도전층을 형성하는 단계와, 상기 도전층상에 제1감광막을 도포하고 소정의 마스크패턴에 따라 그 표면부위를 선택적으로 노광하고 실릴레이션을 실시하는 단계, 상기 제1감광막상에 제2감광막을 도포하고 소정의 마스크패턴에 따라 그 표면부위를 선택적으로 노광하고 실릴레이션을 실시하는 단계, 상기 제2감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계, 상기 식각된 감광막 패턴의 측면에 폴리머 측벽을 생성하는 단계, 상기 감광막패턴과 폴리머 측벽을 마스크로 이용하여 폴리머 측벽 외측의 상기 도전층 부분을 소정두께 식각하는 단계, 상기 제1감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계, 상기 식각된 감광막 패턴의 측면에 폴리머 측벽을 생성하는 단계, 남아 있는 감광막을 제거하는 단계, 상기 폴리머 측벽들을 마스크로 이용하여 상기 도전층을 소정두께 식각하는 단계, 및 상기 남아 있는 폴리머를 제거하는 단계를 포함한다.The capacitor forming method of the semiconductor device using the TIPS of the present invention for achieving the above object is to form a conductive layer for forming a capacitor charge storage electrode on the semiconductor substrate, and to apply a first photosensitive film on the conductive layer Selectively exposing the surface portion according to a mask pattern and performing silylization; applying a second photosensitive layer on the first photosensitive film, and selectively exposing the surface portion according to a predetermined mask pattern and performing silylation. Etching the first and second photoresist layer using the silylated portion of the second photoresist layer as a mask, generating a polymer sidewall on the side of the etched photoresist pattern, masking the photoresist pattern and the polymer sidewall Etching a portion of the conductive layer outside the sidewall of the polymer by a predetermined thickness, and silicide of the first photoresist film. Etching the first and second photoresist films using the portion as a mask, creating a polymer sidewall on the side of the etched photoresist pattern, removing the remaining photoresist film, and using the polymer sidewalls as a mask for the conductive Etching the layer to a predetermined thickness, and removing the remaining polymer.

도 1a 내지 1i는 본 발명에 의한 TIPS를 이용한 반도체소자의 커패시터 전하저장전극 형성방법을 도시한 공정순서도.1A to 1I are process flowcharts illustrating a method of forming a capacitor charge storage electrode of a semiconductor device using TIPS according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1.폴리실리콘층 2.반사방지층1. Polysilicon layer 2. Anti-reflective layer

3.제1감광막 4.제2감광막3. First photosensitive film 4. Second photosensitive film

3A,4A.실릴레이션된 부분 5,6.폴리머3A, 4A. Silylated Part 5, 6. Polymer

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1a 내지 1i는 본 발명에 의한 TIPS를 이용한 실린더 구조의 커패시터의 전하저장전극 형성방법을 공정순서에 따라 도시한 것이다.1A to 1I illustrate a method of forming a charge storage electrode of a capacitor having a cylindrical structure using TIPS according to the present invention.

먼저, 도 1a를 참조하면, 반도체기판(도시하지 않음)상에 커패시터 전하저장전극 형성을 위한 도전층으로서, 예컨대 폴리실리콘(1)을 증착하고, 이위에 반사방지층(anti-reflection coating)(2)을 형성한다. 이어서 반사방지층(2)상에 제1감광막(3)을 도포한 후, 소정의 마스크패턴에 따라 그 표면부위(3A)를 선택적으로 노광하고 실릴레이션을 실시한다. 이어서 제1감광막(3)상에 제2감광막(4)을 도포한 후, 소정의 마스크패턴에 따라 그 표면부위(4A)를 선택적으로 노광하고 실릴레이션을 실시한다. 이때, 제2감광막(4)의 실릴레이션된 부분(4A)의 양단이 제1감광막(3)의 실릴레이션된 부분(3A)과 겹쳐지도록 패턴을 형성한다.First, referring to FIG. 1A, as a conductive layer for forming a capacitor charge storage electrode, for example, polysilicon 1 is deposited on a semiconductor substrate (not shown), and an anti-reflection coating (2) is disposed thereon. ). Subsequently, after applying the first photosensitive film 3 on the antireflection layer 2, the surface portion 3A is selectively exposed in accordance with a predetermined mask pattern and subjected to siliculation. Subsequently, after applying the second photoresist film 4 on the first photoresist film 3, the surface portion 4A is selectively exposed in accordance with a predetermined mask pattern and subjected to siliculation. At this time, a pattern is formed such that both ends of the silylated portion 4A of the second photosensitive film 4 overlap the silylated portion 3A of the first photosensitive film 3.

다음에 도 1b에 나타낸 바와 같이 상기 제2감광막(4)의 실릴레이션된 패턴(4A)을 마스크로 이용하여 제1감광막(3)을 식각한다. 이때, 감광막의 식각은 O2/SO2/He계열을 이용하여 식각하며, 감광막의 식각시 제1감광막의 실릴레이션된 부분(3A)이 노출될때 이를 제거하기 위해 B.T(breakthrough)단계에서 CF4로 제거한 뒤 다시 감광막을 식각한다.Next, as illustrated in FIG. 1B, the first photosensitive film 3 is etched using the silylated pattern 4A of the second photosensitive film 4 as a mask. At this time, the etching of the photoresist layer is etched using O2 / SO2 / He series, and then removed with CF4 in the BT (breakthrough) step to remove when the silylated portion 3A of the first photoresist layer is exposed during etching of the photoresist layer. Etch the photoresist again.

이어서 상기 식각된 감광막 패턴의 측면에 HBr가스를 이용하여 폴리머(5)을 생성한다.Subsequently, the polymer 5 is formed on the side of the etched photoresist pattern by using HBr gas.

다음에 도 1d에 나타낸 바와 같이 감광막패턴과 폴리머(5)를 마스크로 이용하여 폴리머 측벽(5) 외측의 폴리실리콘층(1)을 Cl2가스를 이용하여 소정두께 부분적으로 식각한다.Next, as illustrated in FIG. 1D, the polysilicon layer 1 outside the polymer sidewall 5 is partially etched using Cl 2 gas by using the photoresist pattern and the polymer 5 as a mask.

이어서 도 1e에 나타낸 바와 같이 상기 제1및 제2감광막(3,4)을 식각하는바, 이때, 제1감광막(3)의 실릴레이션된 부분(3A)이 마스크로 작용하여 식각이 일어나게 되며, 감광막 식각시 에천트(etchant)인 O2가 실릴레이션된 Si과 반응하여 제1감광막(3)의 실릴레이션된 부분(3A)이 산화막으로 변하게 된다. 감광막의 식각은 O2/SO2/He계열을 이용하여 식각한다.Subsequently, as illustrated in FIG. 1E, the first and second photoresist layers 3 and 4 are etched, and at this time, the silylated portion 3A of the first photoresist layer 3 serves as a mask to perform etching. When the photoresist is etched, an etchant (O 2) reacts with the silized Si to convert the silized portion 3A of the first photoresist 3 into an oxide film. The photoresist layer is etched using the O 2 / SO 2 / He series.

다음에 도 1f에 나타낸 바와 같이 상기 식각된 감광막 패턴의 측면에 다시 HBr가스를 이용하여 폴리머(6)을 생성한다.Next, as shown in FIG. 1F, the polymer 6 is formed on the side of the etched photoresist pattern again using HBr gas.

이어서 도 1g에 나타낸 바와 같이 남아 있는 감광막을 제거한다. 이때, 감광막 식각시 하부층인 폴리실리콘과의 선택비가 수십:1 이상이 되도록 하여 식각을 실시한다.Then, the remaining photoresist film is removed as shown in FIG. 1G. At this time, the etching is performed so that the selectivity with polysilicon as the lower layer during the photoresist film is set to several tens or more.

다음에 도 1h에 나타낸 바와 같이 상기 폴리머 측벽들(5,6)을 마스크로 이용하여 하부의 폴리실리콘층(1)을 Cl2가스를 이용하여 소정두께 식각한 다음 도 1i에 나타낸 바와 같이 남아 있는 폴리머를 제거함으로써 이중 실린더구조의 커패시터 전하저장전극(1A)을 완성한다.Next, as shown in FIG. 1H, the lower side of the polysilicon layer 1 is etched using Cl 2 gas using the polymer sidewalls 5 and 6 as a mask, and then the remaining polymer as shown in FIG. The capacitor charge storage electrode 1A of the double cylinder structure is completed by removing?

상기한 식각공정들은 모두 인시튜(in-situ)로 진행하며, 식각장비는 ICP, TCP, MERIE등을 사용한다.All of the above etching processes are performed in-situ, and the etching equipment uses ICP, TCP, MERIE, and the like.

상기와 같은 방법으로 폴리실리콘층을 식각하여 전하저장전극을 형성할 경우, 표면적을 기존의 실린더형 전하저장전극에 비해 더욱 확보할 수 있고, 식각단계가 기존의 공정보다 많지만 모두 인시튜(in-situ)로 진행 가능하므로 공정 지연시간을 크게 발생하지 않는다.When the charge storage electrode is formed by etching the polysilicon layer as described above, the surface area can be more secured than the conventional cylindrical charge storage electrode, and the etching step is more than that of the conventional process, but all are in situ (in- As it is possible to proceed to situ, process delay time is not large.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

본 발명에 의하면, 이중 감광막층의 실릴레이션을 이용하고 감광막 식각시 생성된 폴리머를 사용하여 실린더형 전하저장전극을 형성함으로써 대용량의 전하저장용량을 확보할 수 있다.According to the present invention, a large-capacity charge storage capacity can be secured by using a siliculation of the double photoresist layer and forming a cylindrical charge storage electrode using a polymer produced during photoresist etching.

Claims (10)

반도체기판상에 커패시터 전하저장전극 형성을 위한 도전층을 형성하는 단계와,Forming a conductive layer for forming a capacitor charge storage electrode on the semiconductor substrate; 상기 도전층상에 제1감광막을 도포하고 소정의 마스크패턴에 따라 그 표면부위를 선택적으로 노광하고 실릴레이션을 실시하는 단계,Applying a first photoresist film on the conductive layer, selectively exposing the surface portion according to a predetermined mask pattern, and performing siliculation; 상기 제1감광막상에 제2감광막을 도포하고 소정의 마스크패턴에 따라 그 표면부위를 선택적으로 노광하고 실릴레이션을 실시하는 단계,Applying a second photoresist film on the first photoresist film, selectively exposing the surface portion according to a predetermined mask pattern, and performing siliculation; 상기 제2감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계,Etching the first and second photoresist films using the silylated portion of the second photoresist film as a mask; 상기 식각된 감광막 패턴의 측면에 폴리머 측벽을 생성하는 단계,Generating a polymer sidewall on a side of the etched photoresist pattern, 상기 감광막패턴과 폴리머 측벽을 마스크로 이용하여 폴리머 측벽 외측의 상기 도전층 부분을 소정두께 식각하는 단계,Etching the conductive layer portion outside the polymer sidewall by a predetermined thickness using the photoresist pattern and the polymer sidewall as a mask; 상기 제1감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계,Etching the first and second photoresist films using the silylated portion of the first photoresist film as a mask; 상기 식각된 감광막 패턴의 측면에 폴리머 측벽을 생성하는 단계,Generating a polymer sidewall on a side of the etched photoresist pattern, 남아 있는 감광막을 제거하는 단계,Removing the remaining photoresist, 상기 폴리머 측벽들을 마스크로 이용하여 상기 도전층을 소정두께 식각하는 단계, 및Etching the conductive layer by a predetermined thickness using the polymer sidewalls as a mask, and 상기 남아 있는 폴리머를 제거하는 단계를 포함하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.Capacitor forming method of a semiconductor device using a TIPS comprising the step of removing the remaining polymer. 제1항에 있어서,The method of claim 1, 상기 제2감광막의 실릴레이션된 부분의 양단이 제1감광막의 실릴레이션된 부분과 겹쳐지도록 하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.And both ends of the silylated portion of the second photosensitive film overlap with the silylated portion of the first photosensitive film. 제1항에 있어서,The method of claim 1, 상기 도전층을 형성한 후, 그 상부에 반사방지층을 형성하는 단계가 더 포함되는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.After the conductive layer is formed, the method of forming a capacitor of a semiconductor device using a TIPS, characterized in that further comprising the step of forming an anti-reflection layer on top. 제1항에 있어서,The method of claim 1, 상기 감광막의 식각은 O2/SO2/He계열을 이용하여 수행하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.The etching of the photosensitive film is a capacitor forming method of a semiconductor device using a TIPS, characterized in that performed using the O2 / SO2 / He series. 제1항에 있어서,The method of claim 1, 상기 제2감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계에서 감광막의 식각시 제1감광막의 실릴레이션된 부분이 노출될때 이를 제거하기 위해 B.T(breakthrough)단계에서 CF4로 제거한 뒤 다시 감광막을 식각하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.In the step of etching the first and second photoresist film by using the sililated part of the second photoresist film as a mask to remove the silicified part of the first photoresist film during the etching of the photoresist film, in a BT (breakthrough) step. A method of forming a capacitor of a semiconductor device using a TIPS, characterized in that the photosensitive film is etched again after removing with CF4. 제1항에 있어서,The method of claim 1, 상기 폴리머 생성시 HBr가스를 이용하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.A method of forming a capacitor of a semiconductor device using a TIPS, characterized in that to use the HBr gas when producing the polymer. 제1항에 있어서,The method of claim 1, 상기 도전층은 폴리실리콘을 증착하여 형성하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.The conductive layer is a capacitor forming method of a semiconductor device using a TIPS, characterized in that formed by depositing polysilicon. 제1항에 있어서,The method of claim 1, 상기 폴리실리콘 식각시 Cl2가스를 이용하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.The method of forming a capacitor of a semiconductor device using TIPS, characterized in that Cl2 gas is used when etching the polysilicon. 제1항에 있어서,The method of claim 1, 상기 제1감광막의 실릴레이션된 부분을 마스크로 이용하여 제1 및 제2감광막을 식각하는 단계에서 감광막 식각시 에천트인 O2가 실릴레이션된 Si과 반응하여 제1감광막의 실릴레이션된 부분이 산화막으로 변하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.In the step of etching the first and second photoresist films by using the silylated portion of the first photoresist film as a mask, when the photoresist is etched, the reacted Si reacts with the siliced Si and the silylated part of the first photoresist film becomes an oxide film. Capacitor formation method of a semiconductor device using a TIPS characterized in that it changes. 제1항에 있어서,The method of claim 1, 상기 식각공정들을 모두 인시튜(in-situ)로 진행하는 것을 특징으로 하는 TIPS를 이용한 반도체소자의 커패시터 형성방법.And all the etching processes are performed in-situ.
KR1019990025948A 1999-06-30 1999-06-30 Method of fabricating capacitor of semiconductor device using top surface image process by silylation KR100349697B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990025948A KR100349697B1 (en) 1999-06-30 1999-06-30 Method of fabricating capacitor of semiconductor device using top surface image process by silylation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990025948A KR100349697B1 (en) 1999-06-30 1999-06-30 Method of fabricating capacitor of semiconductor device using top surface image process by silylation

Publications (2)

Publication Number Publication Date
KR20010005150A true KR20010005150A (en) 2001-01-15
KR100349697B1 KR100349697B1 (en) 2002-08-22

Family

ID=19597999

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990025948A KR100349697B1 (en) 1999-06-30 1999-06-30 Method of fabricating capacitor of semiconductor device using top surface image process by silylation

Country Status (1)

Country Link
KR (1) KR100349697B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8274777B2 (en) 2008-04-08 2012-09-25 Micron Technology, Inc. High aspect ratio openings

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960013511B1 (en) * 1993-08-13 1996-10-05 현대전자산업 주식회사 Method for manufacturing dram cell storage pole
KR0170323B1 (en) * 1995-08-31 1999-02-01 김광호 Method of fabricating semiconductor capacitor
US5753419A (en) * 1995-09-18 1998-05-19 Texas Instruments Incorporated Increase dram node capacitance by etching rough surface
KR970030823A (en) * 1995-11-21 1997-06-26 김광호 Capacitor Manufacturing Method of Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8274777B2 (en) 2008-04-08 2012-09-25 Micron Technology, Inc. High aspect ratio openings
US8760841B2 (en) 2008-04-08 2014-06-24 Micron Technology, Inc. High aspect ratio openings
US9595387B2 (en) 2008-04-08 2017-03-14 Micron Technology, Inc. High aspect ratio openings

Also Published As

Publication number Publication date
KR100349697B1 (en) 2002-08-22

Similar Documents

Publication Publication Date Title
CN109659222B (en) Method for forming semiconductor device
US6124162A (en) Method for manufacturing cylindrical lower electrode of DRAM capacitor
KR100349697B1 (en) Method of fabricating capacitor of semiconductor device using top surface image process by silylation
KR960026803A (en) Cylindrical Capacitor Manufacturing Method
US5804489A (en) Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching
KR100304946B1 (en) Method for manufacturing semiconductor device
KR100347543B1 (en) Method of manufacturing a capacitor in a semiconductor device
WO2022160629A1 (en) Manufacturing method for semiconductor structure and semiconductor structure
KR100191464B1 (en) Method of fabricating a capacitor in a semiconductor device
KR950013900B1 (en) Dram cell manufacturing process
KR960005568B1 (en) Method for manufacturing a storage node of semiconductor memory device
KR100419748B1 (en) Method for fabricating semiconductor device
KR100218730B1 (en) Fabricating method of semiconductor device
KR100275934B1 (en) A method for forming fine concuctive line of semiconductor device
KR100388213B1 (en) method for forming a storage node in a semiconductor device
KR940009617B1 (en) Method of manufacturing capacitor of semiconductor memory device
KR100348297B1 (en) Method for manufacturing capacitor in semiconductor device
KR100189969B1 (en) Capacitor fabrication method of semiconductor device
KR100641083B1 (en) Method for forming a contact portion of storage node electrode
KR100498605B1 (en) A method for forming inner cylinder capacitor in semiconductor device
KR940009620B1 (en) Method of manufacturing capacitor of semiconductor cell
KR100358138B1 (en) A method for forming cylindrical storage node in semiconductor device
KR20000025018A (en) Method for forming lower electrode for capacitors of semiconductor
KR20030054310A (en) Method for fabricating capacitor in semiconductor device
US20040197710A1 (en) Method for defining ring pattern

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee