KR20010004717A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20010004717A KR20010004717A KR1019990025431A KR19990025431A KR20010004717A KR 20010004717 A KR20010004717 A KR 20010004717A KR 1019990025431 A KR1019990025431 A KR 1019990025431A KR 19990025431 A KR19990025431 A KR 19990025431A KR 20010004717 A KR20010004717 A KR 20010004717A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리(Cu)를 사용하여 구리 금속 배선을 형성할 때, 구리 전해 도금법을 사용하여 크롬이 1%로 이내로 함유된 구리 합금을 용이하게 매립시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, when a copper metal wiring is formed using copper (Cu), a copper alloy containing less than 1% of chromium is easily embedded using a copper electrolytic plating method. A metal wiring formation method of a semiconductor element which can be made.
반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리 박막은 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다. 한편, 구리 합금 배선은 순수한 구리 배선에 비하여 비저항이 다소 크지만 배선의 내식성과 신뢰성이 매우 우수한 것으로 알려져 있다.As the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of the device continues to shrink to the sub-half-micron region, while improving circuitry in terms of performance and reliability. Circuit density is increasing. In response to these demands, the copper thin film has a higher melting point than aluminum in forming metal wirings of the semiconductor device, and thus has high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and providing a specific resistance. This low rate can increase the signal transfer rate, making it a useful interconnect material for integration circuits. On the other hand, although copper alloy wiring has a rather large specific resistance compared to pure copper wiring, it is known that corrosion resistance and reliability of wiring are very excellent.
구리 합금 증착은 주로 스퍼터링 방법에 의하여 증착할 수 있다. 원하는 조성의 스퍼터링 타겟을 제조한 후, 이를 스퍼터링하므로써, 구리 합금 박막을 증착시킬 수 있다. 그러나, 일반적으로 스퍼터링은 스텝 커버리지가 작은 공정이다. 그러므로, 비아 콘택홀의 크기가 감소하고 어스펙트 비가 증가함에 따라 구리 합금을 스퍼터링에 의하여 비아 콘택홀에 매립하기가 어려워진다. 구리 매립 특성이 불량할 경우에는 비아 콘택홀의 저항이 높거나 구리 플러그가 단락(fail)되는 문제가 발생한다. 또한 반도체 소자의 속도가 느려지며(RC time delay 증가), 신뢰성이 열악해지고, 수율이 감소하는 문제점이 발생한다. 따라서, 구리 합금의 비아 콘택홀 매립 특성이 우수한 증착 공정을 개발하여야 한다.Copper alloy deposition can be deposited mainly by the sputtering method. After producing a sputtering target of a desired composition, by sputtering it, a copper alloy thin film can be deposited. In general, however, sputtering is a process with small step coverage. Therefore, as the size of the via contact hole decreases and the aspect ratio increases, it becomes difficult to embed the copper alloy in the via contact hole by sputtering. If the copper buried property is poor, a high resistance of the via contact hole or a shortage of the copper plug may occur. In addition, there is a problem that the speed of the semiconductor device becomes slow (increased RC time delay), the reliability becomes poor, and the yield decreases. Therefore, a deposition process having excellent via contact hole filling properties of copper alloys should be developed.
현재, 가능한 순수 구리 매립 방법으로는 물리기상증착(PVD)법/리플로우 (reflow), 화학기상증착법(CVD), 전해 도금(Electroplating)법, 무전해 도금(Electroless-plating)법 등이 있으며, 이 중에서 선호되는 방법은 구리 매립 특성이 비교적 양호한 전해 도금법 및 화학기상증착법이다.Currently, possible pure copper filling methods include physical vapor deposition (PVD) method / reflow, chemical vapor deposition (CVD), electroplating method, electroless-plating method, etc. Among these, preferred methods are electroplating and chemical vapor deposition, which have relatively good copper embedding properties.
따라서, 본 발명은 기존의 순수한 구리 전해 도금법을 사용하여 크롬이 1% 이내 함유된 구리 합금을 용이하게 매립시켜 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method for forming a metal wiring of a semiconductor device capable of easily embedding a copper alloy containing chromium within 1% by using a conventional pure copper electroplating method to improve the reliability, stability and performance of the metal wiring. The purpose is to provide.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 하지층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 비아 콘택홀 및 트렌치를 형성하는 단계; 클리닝 공정을 실시한 후, 상기 비아 콘택홀 및 트렌치를 포함한 상기 층간 절연막 표면에 확산 장벽층을 형성하는 단계; 상기 확산 장벽층 상에 구리 시드층을 형성하는 단계; 전해 도금법으로 1차 구리 매립 공정을 진행하여 상기 구리 시드층 상에 제 1 구리층을 형성하는 단계; 상기 제 1 구리층 상에 크롬층을 형성하는 단계; 전해 도금법으로 2차 구리 매립 공정을 진행하여 상기 크롬층 상에 제 2 구리층을 형성하는 단계; 상기 구리 시드층, 제 1 구리층, 크롬층 및 제 2 구리층이 적층된 층을 열처리하여 크롬을 균일하게 분산시켜 구리 합금층을 형성하는 단계; 및 상기 구리 합금층을 연마하여 구리 합금 배선을 형성한 후, 웨이퍼의 표면에 캡핑층을 전면 증착하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention may include forming a via contact hole and a trench by forming an interlayer insulating film on an underlayer and then etching a portion of the interlayer insulating film; After the cleaning process, forming a diffusion barrier layer on a surface of the interlayer insulating layer including the via contact hole and the trench; Forming a copper seed layer on the diffusion barrier layer; Performing a first copper embedding process by an electroplating method to form a first copper layer on the copper seed layer; Forming a chromium layer on the first copper layer; Forming a second copper layer on the chromium layer by performing a second copper embedding process by an electroplating method; Heat-treating the layer in which the copper seed layer, the first copper layer, the chromium layer, and the second copper layer are laminated to uniformly disperse chromium to form a copper alloy layer; And polishing the copper alloy layer to form a copper alloy wire, and then depositing a capping layer on the entire surface of the wafer.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1H are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11: 하지층 12: 층간 절연막11: base layer 12: interlayer insulating film
13: 비아 콘택홀 14: 트렌치13: via contact hole 14: trench
15: 확산 장벽층 16: 구리 합금층15: diffusion barrier layer 16: copper alloy layer
16a: 구리 시드층 16b: 제 1 구리층16a: copper seed layer 16b: first copper layer
16c: 크롬층 16d: 제 2 구리층16c: chromium layer 16d: second copper layer
160: 구리 합금 배선160: copper alloy wiring
17: 캡핑층17: capping layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1H are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 하지층(11)상에 층간 절연막(12)을 형성한 후, 층간 절연막(12)의 일부분을 식각하여 비아 콘택홀(13) 및 트렌치(14)를 형성한다.Referring to FIG. 1A, after forming the interlayer insulating layer 12 on the base layer 11, a portion of the interlayer insulating layer 12 is etched to form the via contact hole 13 and the trench 14.
상기에서, 하지층(11)은 반도체 기판, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층이다. 층간 절연막(12)은 낮은 유전 상수(low k)를 갖는 절연 물질로 형성한다. 비아 콘택홀(13) 및 트렌치(14)는 듀얼 다마신(dual damascene) 방식으로 형성한다.In the above, the base layer 11 is a layer formed of a conductive material such as a semiconductor substrate, polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or the like, or a layer formed of an insulating material. The interlayer insulating film 12 is formed of an insulating material having a low dielectric constant (low k). The via contact hole 13 and the trench 14 are formed in a dual damascene method.
도 1b를 참조하면, 클리닝(cleaning) 공정을 실시한 후, 비아 콘택홀(13) 및 트렌치(14)를 포함한 층간 절연막(12) 표면에 확산 장벽층(15)을 형성한다.Referring to FIG. 1B, after performing a cleaning process, the diffusion barrier layer 15 is formed on the surface of the interlayer insulating layer 12 including the via contact hole 13 and the trench 14.
상기에서, 클리닝 공정은 하지층(11)이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마(RP plasma)를 이용하고, 하지층(11)이 구리(Cu)일 경우 리액티브 클리닝(reactive cleaning) 방식을 적용하며, 하지층(11)이 절연 물질일 경우 스퍼터링(sputtering) 방식을 적용하고, 이외에도 NF3클리닝, 습식(wet) 클리닝이 있다. 확산 장벽층(15)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 적어도 어느 하나로 형성하며, 100 내지 700Å 두께의 접착층과 100 내지 1000Å 두께의 베리어 메탈층이 적층되어 있다.In the above, the cleaning process uses high-frequency plasma (RP plasma) when the base layer 11 is a metal such as tungsten (W) or aluminum (Al), and reactive when the base layer 11 is copper (Cu). Reactive cleaning is applied, and if the base layer 11 is an insulating material, a sputtering method is applied. In addition, there are NF 3 cleaning and wet cleaning. The diffusion barrier layer 15 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN, and has an adhesive layer having a thickness of 100 to 700 GPa and a thickness of 100 to 1000 GPa. The barrier metal layer of thickness is laminated | stacked.
도 1c를 참조하면, 전해 도금 공정을 진행하기 위해 촉매 역할을 하는 구리 시드층(16a)을 확산 장벽층(15) 상에 형성한다.Referring to FIG. 1C, a copper seed layer 16a is formed on the diffusion barrier layer 15 to serve as a catalyst for the electroplating process.
상기에서, 구리 시드층(16a)은 스퍼터링법, 화학기상증착법, 메탈 이온 플라즈마(Ionic Metal Plasma; IMP)-물리기상증착법 등으로 100 내지 1000Å의 두께로 증착한다. 구리 시드층(16a)은 스텝 커버리지가 우수하여야 한다.In the above, the copper seed layer 16a is deposited to a thickness of 100 to 1000 mW by sputtering, chemical vapor deposition, Ionic Metal Plasma (IMP) -physical vapor deposition, or the like. The copper seed layer 16a should have good step coverage.
도 1d를 참조하면, 전해 도금법으로 1차 구리 매립 공정을 진행하여 구리 시드층(16a) 상에 제 1 구리층(16b)을 형성한다.Referring to FIG. 1D, a first copper embedding process is performed by an electroplating method to form a first copper layer 16b on a copper seed layer 16a.
상기에서, 전해 도금법은 매립 특성이 비교적 양호한 방법이며, 황산 구리(CuSO4) 수용액 내에서 웨이퍼의 표면에 음극의 전해 포텐셜을 인가하면 전해액 내의 구리 이온이 환원되어 웨이퍼의 구리 시드층(16a)에 도금되어 제 1 구리층(16b)이 형성된다. 제 1 구리층(16b)은 후속 공정인 크롬 원자의 합금 과정 진행이 용이해지도록 비아 콘택홀(13) 크기의 1/2 정도의 두께로 형성한다.In the above, the electroplating method is a method of embedding relatively good, and when the electrolytic potential of the cathode is applied to the surface of the wafer in a copper sulfate (CuSO 4 ) aqueous solution, copper ions in the electrolyte is reduced to the copper seed layer 16a of the wafer. It is plated and the 1st copper layer 16b is formed. The first copper layer 16b is formed to a thickness of about 1/2 of the size of the via contact hole 13 so that an alloy process of chromium atoms, which is a subsequent process, may be easily performed.
도 1e를 참조하면, 제 1 구리층(16b) 상에 크롬층(16c)을 형성한다.Referring to FIG. 1E, a chromium layer 16c is formed on the first copper layer 16b.
상기에서, 크롬층(16c)은 전해 도금 또는 스퍼터링에 의해 형성한다. 크롬층(16c)의 두께는 경우에 따라 달라지는데, 구리 합금 내의 크롬의 함유량이 1% 이내가 되도록 제어하여야 한다. 이는 구리 배선의 비저항을 크게 증가시키지 않으면서 배선의 신뢰성 및 내식성을 크게 증가시킬 수 있는 크롬의 적정한 투입량이 약 1% 이내이기 때문이다.In the above, the chromium layer 16c is formed by electroplating or sputtering. The thickness of the chromium layer 16c varies from case to case, and should be controlled so that the content of chromium in the copper alloy is within 1%. This is because an adequate amount of chromium that can significantly increase the reliability and corrosion resistance of the wiring without significantly increasing the specific resistance of the copper wiring is within about 1%.
도 1f를 참조하면, 전해 도금법으로 2차 구리 매립 공정을 진행하여 크롬층(16c) 상에 제 2 구리층(16d)을 형성한다.Referring to FIG. 1F, a second copper buried process is performed by electroplating to form a second copper layer 16d on the chromium layer 16c.
상기에서, 제 2 구리층(16d)은 비아 콘택홀(13) 및 트렌치(14)를 완전히 매립시킬 수 있는 두께로 형성한다.In the above, the second copper layer 16d is formed to a thickness capable of completely filling the via contact hole 13 and the trench 14.
도 1g를 참조하면, 구리 시드층(16a), 제 1 구리층(16b), 크롬층(16c) 및 제 2 구리층(16d)이 적층된 층을 열처리하여 크롬을 균일하게 분산시키므로 구리 합금층(16)이 형성된다.Referring to FIG. 1G, a copper alloy layer is formed by uniformly dispersing chromium by heat-treating the stacked layer of the copper seed layer 16a, the first copper layer 16b, the chromium layer 16c, and the second copper layer 16d. 16 is formed.
상기에서, 열처리는 400 내지 600℃의 온도에서 0.5 내지 2시간 동안 반응로(furnace)에서 실시한다. 이때, 열처리 온도는 하지층(11)이 어떠한 물질로 형성되었는지를 고려하여 구체적으로 결정하여야 한다. 예를 들어, 하지층(11)이 알루미늄 합금(Al-0.5%Cu)인 경우에는 550℃를 넘지 않아야 한다.In the above, the heat treatment is carried out in a furnace (furnace) for 0.5 to 2 hours at a temperature of 400 to 600 ℃. At this time, the heat treatment temperature should be specifically determined in consideration of what material the base layer 11 is formed. For example, when the base layer 11 is aluminum alloy (Al-0.5% Cu), it should not exceed 550 degreeC.
도 1h를 참조하면, 구리 합금층(16)을 화학적 기계적 연마(CMP)법으로 연마하는 공정 및 포스트-클리닝(post-cleaning) 공정을 실시하여 구리 합금 배선(160)을 형성한다. 이후, 웨이퍼의 표면에 캡핑층(17)을 전면 증착한다.Referring to FIG. 1H, a copper alloy layer 160 is formed by a process of polishing the copper alloy layer 16 by chemical mechanical polishing (CMP) and a post-cleaning process. Thereafter, the capping layer 17 is entirely deposited on the wafer surface.
상기에서, 캡핑층(17)은 구리 합금 배선(160)으로부터 구리 원자가 이후에 구리 합금 배선(160) 상부쪽에 형성될 층간 절연막으로 확산하는 것을 막는 역할을 하며, 주로 실리콘 나이트라이드(SiN)로 형성한다. 이로써, 듀얼 다마신 공정에 의한 최종적인 구리 합금 배선이 완성된다.In the above, the capping layer 17 serves to prevent the copper atoms from diffusing from the copper alloy wiring 160 to the interlayer insulating film to be formed later on the copper alloy wiring 160, and mainly formed of silicon nitride (SiN). do. This completes the final copper alloy wiring by the dual damascene process.
상술한 바와 같이, 본 발명은 구리의 전해 도금법을 적용함에 의한 구리 매립 특성의 향상으로, 비아 콘택홀 내부에 보이드(void)와 키홀(keyhole)과 같은 결함 발생을 방지할 수 있을 뿐만 아니라, 서로 다른 크기의 비아 콘택홀과 서로 다른 폭의 트렌치가 존재하는 경우에도 구리 합금을 동시에 매립시킬 수 있어, 공정의 재현성 및 안정성을 향상시킬 수 있다. 또한, 본 발명은 기존의 순수한 구리 전해 도금법을 사용하여 크롬이 1% 이내 함유된 구리 합금을 용이하게 매립시켜 금속 배선에 대한 신뢰성, 내식성 및 성능을 향상시킬 수 있다.As described above, the present invention improves the copper embedding characteristics by applying the electrolytic plating method of copper, and it is possible to prevent defects such as voids and keyholes in the via contact holes, and to prevent each other. Copper alloys may be buried at the same time even when different sizes of via contact holes and trenches of different widths exist, thereby improving process reproducibility and stability. In addition, the present invention can easily embed the copper alloy containing chromium within 1% by using the conventional pure copper electroplating method to improve the reliability, corrosion resistance and performance for the metal wiring.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056612A1 (en) * | 2001-12-28 | 2003-07-10 | Genitech Co., Ltd. | Method of forming copper interconnections for semiconductor integrated circuits on a substrate |
| KR100456259B1 (en) * | 2002-07-15 | 2004-11-09 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100498454B1 (en) * | 2002-09-03 | 2005-07-01 | 삼성전자주식회사 | Method for creating a damascene interconnect using a two-step plating process |
| KR100499557B1 (en) * | 2001-06-11 | 2005-07-07 | 주식회사 하이닉스반도체 | method for fabricating the wire of semiconductor device |
| KR100782790B1 (en) * | 2002-07-30 | 2007-12-05 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method of thereof |
| KR100859952B1 (en) * | 2006-12-21 | 2008-09-23 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
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| KR100975652B1 (en) * | 2007-10-05 | 2010-08-17 | 한국과학기술원 | via using Zn or Zn alloys and its making method, 3D chip stack packages using therof |
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| KR100462759B1 (en) * | 2002-05-06 | 2004-12-20 | 동부전자 주식회사 | Metal line with a diffusion barrier and fabrication method thereof |
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- 1999-06-29 KR KR1019990025431A patent/KR100301248B1/en not_active IP Right Cessation
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| KR100499557B1 (en) * | 2001-06-11 | 2005-07-07 | 주식회사 하이닉스반도체 | method for fabricating the wire of semiconductor device |
| WO2003056612A1 (en) * | 2001-12-28 | 2003-07-10 | Genitech Co., Ltd. | Method of forming copper interconnections for semiconductor integrated circuits on a substrate |
| KR100871368B1 (en) * | 2002-07-11 | 2008-12-02 | 주식회사 하이닉스반도체 | Method For Forming Bit Line Spacer Of Semiconductor Device |
| KR100456259B1 (en) * | 2002-07-15 | 2004-11-09 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100782790B1 (en) * | 2002-07-30 | 2007-12-05 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method of thereof |
| KR100498454B1 (en) * | 2002-09-03 | 2005-07-01 | 삼성전자주식회사 | Method for creating a damascene interconnect using a two-step plating process |
| US8025922B2 (en) | 2005-03-15 | 2011-09-27 | Asm International N.V. | Enhanced deposition of noble metals |
| US9587307B2 (en) | 2005-03-15 | 2017-03-07 | Asm International N.V. | Enhanced deposition of noble metals |
| KR100859952B1 (en) * | 2006-12-21 | 2008-09-23 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
| KR100975652B1 (en) * | 2007-10-05 | 2010-08-17 | 한국과학기술원 | via using Zn or Zn alloys and its making method, 3D chip stack packages using therof |
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