KR20000044849A - Method for forming copper alloy wiring of semiconductor device - Google Patents

Method for forming copper alloy wiring of semiconductor device Download PDF

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Publication number
KR20000044849A
KR20000044849A KR1019980061352A KR19980061352A KR20000044849A KR 20000044849 A KR20000044849 A KR 20000044849A KR 1019980061352 A KR1019980061352 A KR 1019980061352A KR 19980061352 A KR19980061352 A KR 19980061352A KR 20000044849 A KR20000044849 A KR 20000044849A
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layer
copper alloy
copper
forming
wiring
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KR1019980061352A
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Korean (ko)
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이병주
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김영환
현대전자산업 주식회사
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Publication of KR20000044849A publication Critical patent/KR20000044849A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Abstract

PURPOSE: A method for forming a copper alloy wiring of a semiconductor device is provided to improve a via contact burying characteristic and reliability of wiring. CONSTITUTION: A method for forming a copper alloy wire of a semiconductor device comprises the following steps. A substrate(11) is formed with a dual damascene pattern including an interlayer dielectric(12), a via contact hole, and a trench. A barrier metal layer(14) is formed on a surface portion of the interlayer dielectric including the dual damascene pattern. A copper burying layer is formed on the barrier metal layer. A copper alloy layer is formed by distributing the alloy elements within the copper-burying layer. A copper alloy wiring(150) is formed by polishing the copper alloy layer and a capping layer(16) is formed thereon.

Description

반도체 소자의 구리 합금 배선 형성 방법Copper alloy wiring formation method of semiconductor device

본 발명은 반도체 소자의 구리 합금 배선 형성 방법에 관한 것으로, 특히 순수한 구리 배선에 비하여 비저항이 크게 높지 않으면서 신뢰성과 내식성이 우수한 구리 합금 배선을 형성함에 있어서, 듀얼 다마신(dual damascene) 공정에 합금화 원소 투입 공정 및 열처리 공정을 도입시켜 비아 콘택 매립 특성을 향상시킬 수 있고, 배선의 신뢰성 향상 및 소자의 고집적화를 실현할 수 있는 구리 합금 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper alloy wiring of a semiconductor device, and in particular, to alloy a dual damascene process in forming a copper alloy wiring having excellent reliability and corrosion resistance without significantly higher specific resistance than pure copper wiring. The present invention relates to a copper alloy wiring forming method capable of improving via contact embedding characteristics by introducing an element input process and a heat treatment process, and to improve wiring reliability and high integration of devices.

일반적으로, 반도체 소자 제조시 소자와 소자간 또는 배선과 배선간을 전기적으로 연결시키기 위해 금속 배선을 사용하고 있다. 금속 배선 재료로 알루미늄(Al) 또는 텅스텐(W)이 널리 사용되고 있으나, 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. 반도체 소자의 초고집적화에 따라 비저항은 낮고 일렉트로마이그레이션(electromigration; EM) 및 스트레스마이그레이션(stressmigration; SM) 등의 신뢰성이 우수한 물질의 이용이 필요하게 되었으며, 이에 부합할 수 있는 가장 적합한 재료로 구리가 최근에 관심의 대상이 되고 있으며, 그 이유로는 구리의 녹는점이 1080℃로서 비교적 높을 뿐만 아니라(알루미늄; 660℃, 텅스텐; 3400℃), 비저항은 1.7μΩ㎝로서(알루미늄;2.7μΩ㎝, 텅스텐; 5.6μΩ㎝) 매우 낮기 때문이다. 구리와 같이 널리 사용되는 금속 배선 재료로 순수 구리에 비하여 비저항이 크게 높지 않으면서 신뢰성과 내식성이 우수한 구리 합금이 있다.In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect between devices and devices or between wires and wires. Although aluminum (Al) or tungsten (W) is widely used as a metal wiring material, its low melting point and high resistivity make it difficult to apply to ultra-high density semiconductor devices. Due to the ultra-high integration of semiconductor devices, it is necessary to use materials having low resistivity and highly reliable materials such as electromigration (EM) and stress migration (SM), and copper is the most suitable material to cope with this. In addition, the melting point of copper is relatively high as 1080 ° C. (aluminum; 660 ° C., tungsten; 3400 ° C.), and the specific resistance is 1.7 μΩ cm (aluminum; 2.7 μΩ cm, tungsten; 5.6). μΩcm) is very low. As a widely used metal wiring material such as copper, there is a copper alloy that is excellent in reliability and corrosion resistance without significantly higher specific resistance than pure copper.

구리 합금 증착은 주로 스퍼터링(sputtering) 방법에 의하여 증착할 수 있다. 원하는 조성의 스퍼터링 타겟(target)을 제조한 후, 이를 스퍼터링하므로써 구리 합금 박막을 증착시킬 수 있다. 그러나, 일반적으로 스퍼터링은 스텝 커버리지(step coverage)가 작은 공정이다. 그러므로, 비아 콘택홀의 크기가 감소하고 애스팩트 비(aspect ratio)가 커짐에 따라 스퍼터링에 의하여 구리 합금을 비아 콘택홀에 매립하기가 어려워진다. 따라서, 비아 콘택 매립 특성이 좋지 않을 경우, 금속 배선이 단락 되거나 금속 배선의 신뢰성이 저하되는 문제점이 발생한다. 이에 따라 구리 합금의 비아 콘택 매립 특성이 우수한 증착 공정의 개발이 연구되고 있다.Copper alloy deposition can be deposited mainly by the sputtering method. After the sputtering target of the desired composition is prepared, the copper alloy thin film can be deposited by sputtering it. In general, however, sputtering is a process with small step coverage. Therefore, as the size of the via contact hole decreases and the aspect ratio increases, it becomes difficult to embed the copper alloy in the via contact hole by sputtering. Therefore, when the via contact filling property is not good, there is a problem that the metal wiring is shorted or the reliability of the metal wiring is degraded. Accordingly, development of a deposition process having excellent via contact buried characteristics of copper alloys has been studied.

따라서, 본 발명은 순수한 구리 배선에 비하여 비저항이 크게 높지 않으면서 신뢰성과 내식성이 우수한 구리 합금 배선을 형성함에 있어서, 듀얼 다마신(dual damascene) 공정에 합금화 원소 투입 공정 및 열처리 공정을 도입시켜 비아 콘택 매립 특성을 향상시킬 수 있고, 배선의 신뢰성 향상 및 소자의 고집적화를 실현할 수 있는 구리 합금 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a via contact by introducing an alloying element input process and a heat treatment process in a dual damascene process in forming a copper alloy wiring having excellent resistivity and corrosion resistance without significantly higher specific resistance than pure copper wiring. It is an object of the present invention to provide a copper alloy wiring forming method capable of improving the embedding characteristics and realizing the improvement of wiring reliability and the high integration of devices.

이러한 목적을 달성하기 위한 본 발명의 구리 합금 배선 형성 방법은 층간 절연막에 비아 콘택홀 및 트랜치로 이루어진 듀얼 다마신 패턴이 형성된 기판이 제공되는 단계; 상기 듀얼 다마신 패턴을 포함한 층간 절연막의 표면부에 배리어 메탈층을 형성하는 단계; 상기 배리어 메탈층상에 구리 매립층을 형성하는 단계; 상기 구리 매립층 내부에 합금화 원소를 균일하게 분포시켜 구리 합금층을 형성하는 단계; 및 상기 구리 합금층을 화학기계적 연마법으로 연마하여 구리 합금 배선을 형성하고, 그 상부에 캡핑층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The copper alloy wiring forming method of the present invention for achieving the above object comprises the steps of providing a substrate having a dual damascene pattern formed of a via contact hole and a trench in the interlayer insulating film; Forming a barrier metal layer on a surface portion of the interlayer insulating layer including the dual damascene pattern; Forming a copper buried layer on the barrier metal layer; Uniformly distributing an alloying element in the copper buried layer to form a copper alloy layer; And polishing the copper alloy layer by chemical mechanical polishing to form a copper alloy wire, and forming a capping layer thereon.

도 1a 내지 1f는 본 발명의 실시예에 따른 반도체 소자의 구리 합금 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming a copper alloy wire of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11: 기판 12: 층간 절연막11: substrate 12: interlayer insulating film

13: 듀얼 다마신 패턴 13A: 비아 콘택홀13: Dual damascene pattern 13A: Via contact hole

13B: 트랜치 14: 배리어 메탈층13B: trench 14: barrier metal layer

15A: 구리 매립층 15: 구리 합금층15A: copper buried layer 15: copper alloy layer

16: 캡핑층 100: 합금화 원소16: capping layer 100: alloying element

150: 구리 합금 배선150: copper alloy wiring

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 1f는 본 발명의 실시예에 따른 반도체 소자의 구리 합금 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for explaining a method of forming a copper alloy wire of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 공정을 거친 기판(11)상에 층간 절연막(12)을 형성한다. 듀얼 다마신 공정으로 층간 절연막(12)의 일부분을 식각 하여 비아 콘택홀(via contact hole; 13A) 및 트랜치(trench; 13B)로 이루어진 듀얼 다마신 패턴(dual damascene pattern; 13)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a substrate 11 that has undergone various processes for forming a semiconductor device. A portion of the interlayer insulating layer 12 is etched by a dual damascene process to form a dual damascene pattern 13 including a via contact hole 13A and a trench 13B.

상기에서, 기판(11)은 반도체 기판에 형성되는 접합부이거나 전극 또는 배선으로 사용되는 도전성 패턴을 포함한다. 비아 콘택홀(13A)은 기판(11)과 배선을 연결시켜주는 부분이고, 트랜치(13B)는 배선이 형성될 부분이다.In the above, the substrate 11 includes a junction formed on a semiconductor substrate or a conductive pattern used as an electrode or a wiring. The via contact hole 13A is a portion connecting the substrate 11 and the wiring, and the trench 13B is a portion where the wiring is to be formed.

도 1b를 참조하면, 듀얼 다마신 패턴(13)을 포함한 층간 절연막(12)의 표면부에 배리어 메탈층(barrier metal layer; 14)을 형성한다.Referring to FIG. 1B, a barrier metal layer 14 is formed on the surface of the interlayer insulating layer 12 including the dual damascene pattern 13.

상기에서, 배리어 메탈층(14)은 스퍼터링법이나 화학기상증착법으로 타이타늄나이트라이드(TiN), 탄탈륨(Ta), 탄탈륨나이트라이드(TaN), 텅스텐나이트라이드(WNX), 등으로 증착하여 형성되며, 구리를 이용하는 배선 공정에서는 300 내지 500Å 두께의 탄탈륨(Ta)과 300 내지 1000Å 두께의 탄탈륨나이트라이드(TaN)가 적층된 구조가 널리 사용되며, 구리 원자가 층간 절연막(12)으로 확산하는 것을 방지하는 역할을 한다.In the above, the barrier metal layer 14 is formed by depositing with titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN X ), or the like by sputtering or chemical vapor deposition. In the wiring process using copper, a structure in which tantalum (Ta) having a thickness of 300 to 500 GPa and tantalum nitride (TaN) having a thickness of 300 to 1000 GPa is laminated is widely used, and copper atoms are prevented from diffusing into the interlayer insulating film 12. Play a role.

도 1c를 참조하면, 배리어 메탈층(14)상에 구리 매립층(15A)을 형성한다.Referring to FIG. 1C, a copper buried layer 15A is formed on the barrier metal layer 14.

상기에서, 구리 매립층(15A)은 무전해도금법, 전해도금법, 스퍼터링법, 화학기상증착법 등의 방법으로 구리를 증착하여 듀얼 다마신 패턴(13)이 매립되도록 형성된다. 듀얼 다마신 패턴(13)의 크기가 작고 애스팩트 비가 클 경우 비아 콘택 매립 특성이 우수한 전해도금법 및 화학기상증착법을 적용하는 것이 유리하다.In the above, the copper buried layer 15A is formed such that the dual damascene pattern 13 is embedded by depositing copper by a method such as electroless plating, electroplating, sputtering, chemical vapor deposition, or the like. When the size of the dual damascene pattern 13 is small and the aspect ratio is large, it is advantageous to apply an electroplating method and a chemical vapor deposition method having excellent via contact filling properties.

도 1d를 참조하면, 구리 매립층(15A) 내부에 합금화 원소(100)를 이온 주입 공정에 의해 투입시킨 후, 투입된 합금화 원소(100)를 열처리 공정에 의해 구리 매립층(15A) 내에 균일하게 분포시켜 구리 합금층(15)을 형성한다.Referring to FIG. 1D, after the alloying element 100 is introduced into the copper buried layer 15A by an ion implantation process, the injected alloying element 100 is uniformly distributed in the copper buried layer 15A by a heat treatment process, and copper The alloy layer 15 is formed.

상기에서, 합금화 원소(100)로 크롬(Cr)을 사용한다. 크롬(Cr) 원소는 구리 배선의 신뢰성과 내식성을 향상시키는 것으로 알려져 있다. 구리 배선의 비저항을 크게 증가시키지 않으면서 배선의 신뢰성을 크게 증가시키기 위한 크롬(Cr)의 적정 투입량은 약 1% 이내이다. 즉, 구리 합금층(15) 내의 크롬(Cr)은 약 1% 이내로 함유되도록 한다. 구리 합금층(15)을 형성하기 위한 열처리 공정은 합금화 원소(100)가 투입된 구리 매립층(15A)을 400 내지 700℃ 온도 범위에서 0.5 내지 2시간 동안 반응로(furnace)에서 진행하여 구리 매립층(15A) 내부의 결함을 줄이고 또한 합금화 원소(100)를 균일하게 분포시킨다. 열처리 공정은 반응로를 이용한 열처리 대신에 급속 열처리 장치를 이용할 수 있다.In the above, chromium (Cr) is used as the alloying element 100. The chromium (Cr) element is known to improve the reliability and corrosion resistance of copper wiring. The proper amount of chromium (Cr) to increase the reliability of the wiring without significantly increasing the specific resistance of the copper wiring is within about 1%. In other words, chromium (Cr) in the copper alloy layer 15 is contained within about 1%. The heat treatment process for forming the copper alloy layer 15 is carried out in the furnace (furnace) for 0.5 to 2 hours in the copper buried layer (15A) to which the alloying element 100 is added in a 400 to 700 ℃ temperature range for a copper buried layer (15A) The internal defects of the alloying element 100 can be evenly distributed. The heat treatment process may use a rapid heat treatment apparatus instead of the heat treatment using the reactor.

한편, 구리 합금층(15)을 형성하기 위한 다른 방법으로 구리 매립층(15A)의 표면에 합금화 원소의 증착층을 형성한 후 열처리 공정을 진행하는 방법이 있다.On the other hand, another method for forming the copper alloy layer 15 is a method of forming a deposited layer of the alloying element on the surface of the copper buried layer 15A and then performing a heat treatment process.

도 1e를 참조하면, 구리 합금층(15)을 화학기계적 연마(CMP)법으로 층간 절연막(12)의 표면이 충분히 노출되는 시점까지 연마하여 듀얼 다마신 패턴(13)에만 구리 합금층(15)을 남겨 구리 합금 배선(150)이 형성된다.Referring to FIG. 1E, the copper alloy layer 15 is polished to a point where the surface of the interlayer insulating layer 12 is sufficiently exposed by chemical mechanical polishing (CMP) method, so that the copper alloy layer 15 only on the dual damascene pattern 13. The copper alloy wiring 150 is formed to leave.

도 1f를 참조하면, 구리 합금 배선(150)을 포함한 층간 절연막(12) 표면에 캡핑층(capping layer; 16)을 형성한다.Referring to FIG. 1F, a capping layer 16 is formed on the surface of the interlayer insulating layer 12 including the copper alloy wire 150.

상기에서, 캡핑층(16)은 실리콘나이트라이드(SiN)를 증착하여 형성하며, 이는 구리 원자가 주변의 절연막으로 확산되는 것을 방지하는 역할을 한다.In the above, the capping layer 16 is formed by depositing silicon nitride (SiN), which serves to prevent the copper atoms from diffusing into the surrounding insulating film.

상술한 바와 같이, 본 발명은 비아 콘택홀 및 트랜치를 갖는 듀얼 다마신 패턴을 형성하고, 듀얼 다마신 패턴에 배리어 메탈층을 형성하고, 배리어 메탈층 상에 구리를 무전해도금법, 전해도금법, 스퍼터링법, 화학기상증착법 등의 방법으로 증착하여 듀얼 다마신 패턴을 매립시키고, 구리 매립층에 합금화 원소를 투입시키고, 열처리 공정으로 합금화 원소를 구리 매립층 내부에 균일하게 분포시켜 구리 합금층을 형성하고, 이후 구리 합금층의 평탄화 공정 및 캡핑층 증착 공정으로 구리 합금 배선을 형성하므로써, 기존의 스퍼터링 방식에 의한 구리 합금층 형성 방법보다 매립 특성이 우수한 전해도금법 및 화학기상증착 방법 등을 이용할 수 있어 구리 합금 배선을 용이하게 형성할 수 있으며, 비아 콘택 매립 특성의 향상으로 배선의 신뢰성 향상 및 소자의 고집적화를 실현할 수 있다.As described above, the present invention forms a dual damascene pattern having via contact holes and trenches, a barrier metal layer is formed on the dual damascene pattern, and electroless plating, electroplating, and sputtering of copper on the barrier metal layer. Depositing the dual damascene pattern by depositing by a method such as a chemical vapor deposition method, a chemical vapor deposition method, an alloying element is introduced into the copper embedding layer, and a copper alloy layer is formed by uniformly distributing the alloying element within the copper embedding layer by a heat treatment process. By forming the copper alloy wiring by the planarization process of the copper alloy layer and the capping layer deposition process, an electroplating method, a chemical vapor deposition method, etc., which have better embedding characteristics than the conventional copper alloy layer formation method by the sputtering method, can be used. Can be easily formed, and the reliability of wiring can be improved by improving the via contact filling property. It is possible to realize a high integration party.

Claims (7)

층간 절연막에 비아 콘택홀 및 트랜치로 이루어진 듀얼 다마신 패턴이 형성된 기판이 제공되는 단계;Providing a substrate having a dual damascene pattern formed of a via contact hole and a trench in the interlayer insulating film; 상기 듀얼 다마신 패턴을 포함한 층간 절연막의 표면부에 배리어 메탈층을 형성하는 단계;Forming a barrier metal layer on a surface portion of the interlayer insulating layer including the dual damascene pattern; 상기 배리어 메탈층상에 구리 매립층을 형성하는 단계;Forming a copper buried layer on the barrier metal layer; 상기 구리 매립층 내부에 합금화 원소를 균일하게 분포시켜 구리 합금층을 형성하는 단계; 및Uniformly distributing an alloying element in the copper buried layer to form a copper alloy layer; And 상기 구리 합금층을 화학기계적 연마법으로 연마하여 구리 합금 배선을 형성하고, 그 상부에 캡핑층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.Polishing the copper alloy layer by a chemical mechanical polishing method to form a copper alloy wiring, and forming a capping layer thereon. 제 1 항에 있어서,The method of claim 1, 상기 배리어 메탈층은 스퍼터링법이나 화학기상증착법으로 타이타늄나이트라이드(TiN), 탄탈륨(Ta), 탄탈륨나이트라이드(TaN), 텅스텐나이트라이드(WNX) 중 적어도 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.The barrier metal layer is formed of at least one of titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and tungsten nitride (WN X ) by sputtering or chemical vapor deposition. Copper alloy wiring formation method. 제 1 항에 있어서,The method of claim 1, 상기 합금화 원소는 크롬(Cr)을 사용하며, 상기 구리 합금층에 1% 이내로 함유되도록 하는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.The alloying element is chromium (Cr), and the copper alloy wiring forming method of the semiconductor device, characterized in that contained in the copper alloy layer within 1%. 제 1 항에 있어서,The method of claim 1, 상기 구리 합금층은 상기 합금화 원소를 이온 주입 공정에 의해 상기 구리 매립층 내에 투입시킨 후, 열처리 공정에 의해 상기 구리 매립층 내에 균일하게 분포시켜 형성되는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.And the copper alloy layer is formed by injecting the alloying element into the copper buried layer by an ion implantation process, and then uniformly distributing it in the copper buried layer by a heat treatment process. 제 1 항에 있어서,The method of claim 1, 상기 구리 합금층은 상기 구리 매립층의 표면에 상기 합금화 원소의 증착층을 형성한 후, 열처리 공정을 의해 상기 구리 매립층 내에 균일하게 분포시켜 형성되는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.And the copper alloy layer is formed by uniformly distributing the copper alloy layer in the copper buried layer by a heat treatment step after forming a deposition layer of the alloying element on the surface of the copper buried layer. 제 6 항 또는 제 7 항에 있어서,The method according to claim 6 or 7, 상기 열처리 공정은 400 내지 700℃ 온도 범위에서 0.5 내지 2시간 동안 진행하는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.The heat treatment process is a copper alloy wiring forming method of a semiconductor device, characterized in that for 0.5 to 2 hours in the 400 to 700 ℃ temperature range. 제 1 항에 있어서,The method of claim 1, 상기 캡핑층은 실리콘나이트라이드(SiN)를 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 구리 합금 배선 형성 방법.The capping layer is a copper alloy wire forming method of a semiconductor device, characterized in that formed by depositing silicon nitride (SiN).
KR1019980061352A 1998-12-30 1998-12-30 Method for forming copper alloy wiring of semiconductor device KR20000044849A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574912B1 (en) * 1999-01-18 2006-05-02 삼성전자주식회사 Meta wiring structure body protecting metal bridge due to scratch by chemical mechanical polishing on insulating layer, for semiconductor device &manufacturing method thereof
KR100690993B1 (en) * 2000-08-02 2007-03-08 주식회사 하이닉스반도체 The method of fabricating metal-line utilized metal-capping layer in damascene structure
KR100710192B1 (en) * 2005-12-28 2007-04-20 동부일렉트로닉스 주식회사 Method for forming line in semiconductor device
KR100723465B1 (en) * 2000-12-29 2007-05-30 삼성전자주식회사 Method for forming a metal line of semiconductor device using a damascene process
KR100732747B1 (en) * 2001-12-12 2007-06-27 주식회사 하이닉스반도체 Method for Forming Copper Wires in Semiconductor Device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574912B1 (en) * 1999-01-18 2006-05-02 삼성전자주식회사 Meta wiring structure body protecting metal bridge due to scratch by chemical mechanical polishing on insulating layer, for semiconductor device &manufacturing method thereof
KR100690993B1 (en) * 2000-08-02 2007-03-08 주식회사 하이닉스반도체 The method of fabricating metal-line utilized metal-capping layer in damascene structure
KR100723465B1 (en) * 2000-12-29 2007-05-30 삼성전자주식회사 Method for forming a metal line of semiconductor device using a damascene process
KR100732747B1 (en) * 2001-12-12 2007-06-27 주식회사 하이닉스반도체 Method for Forming Copper Wires in Semiconductor Device
KR100710192B1 (en) * 2005-12-28 2007-04-20 동부일렉트로닉스 주식회사 Method for forming line in semiconductor device

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