KR100690993B1 - The method of fabricating metal-line utilized metal-capping layer in damascene structure - Google Patents

The method of fabricating metal-line utilized metal-capping layer in damascene structure Download PDF

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KR100690993B1
KR100690993B1 KR1020000044756A KR20000044756A KR100690993B1 KR 100690993 B1 KR100690993 B1 KR 100690993B1 KR 1020000044756 A KR1020000044756 A KR 1020000044756A KR 20000044756 A KR20000044756 A KR 20000044756A KR 100690993 B1 KR100690993 B1 KR 100690993B1
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damascene structure
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KR20020011477A (en
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정철모
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 금속캡핑층을 이용한 다마신구조의 금속배선방법을 개시하며, 개시된 본 발명의 금속캡핑층을 이용한 다마신구조의 금속배선방법은, 금속배선을 위한 베이스층의 상부에 소정의 공간이 존재하도록 다마신 공정에 의한 다마신구조층을 형성하는 제1단계; 상기 다마신구조층의 표면에 확산방지막을 형성하는 제2단계; 상기 확산방지막이 형성된 상기 소정의 공간을 매립하도록 금속매립층을 형성하는 제3단계; 상기 금속매립층의 표면을 덮도록 CVD용 질화티타늄(TiN), PVD용 질화티타늄(TiN) 및 Si3N4물질 중 어느 하나로 이루어진 캡핑층을 형성하는 제4단계; 상기 캡핑층 및 금속매립층을 연마하여 상기 다마신구조층의 상부면을 기준으로 평탄화시키는 제5단계; 및 상기 평탄화된 다마신구조층의 상부표면에 상부증착막을 형성하는 제6단계;를 포함한다. 본 발명에 따르면, 금속 디싱(dishing)의 최소화 및 CMP의 효율의 증대를 통해 소자 특성을 개선하고 공정비를 감소시킬 수 있다.The present invention discloses a metal wiring method having a damascene structure using a metal capping layer, and the metal wiring method having a damascene structure using the metal capping layer of the present invention has a predetermined space on the base layer for metal wiring. A first step of forming a damascene structure layer by a damascene process to be present; Forming a diffusion barrier on the surface of the damascene structure layer; A third step of forming a metal buried layer to fill the predetermined space in which the diffusion barrier is formed; A fourth step of forming a capping layer made of any one of CVD titanium nitride (TiN), PVD titanium nitride (TiN), and Si 3 N 4 material to cover the surface of the metal buried layer; A fifth step of grinding the capping layer and the metal buried layer to planarize the upper surface of the damascene structure layer; And a sixth step of forming an upper deposition film on an upper surface of the planarized damascene structure layer. According to the present invention, it is possible to improve device characteristics and reduce process costs through minimizing metal dishing and increasing efficiency of CMP.

Description

금속캡핑층을 이용한 다마신구조의 금속배선방법{THE METHOD OF FABRICATING METAL-LINE UTILIZED METAL-CAPPING LAYER IN DAMASCENE STRUCTURE}Metal wiring method of damascene structure using metal capping layer {THE METHOD OF FABRICATING METAL-LINE UTILIZED METAL-CAPPING LAYER IN DAMASCENE STRUCTURE}

도 1a 내지 도 1e는 본 발명의 실시예에 따른 금속캡핑층을 이용한 다마신구조의 금속배선방법을 설명하기 위한 공정도.1a to 1e is a process diagram for explaining a metal wiring method of the damascene structure using a metal capping layer according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10 : 베이스층 12 : 다마신구조층10: base layer 12: damascene structure layer

14 : 확산방지막 16 : 금속매립층14 diffusion barrier 16 metal buried layer

18 : 캡핑층 20 : 상부증착막18: capping layer 20: upper deposition film

본 발명은 다마신(damascene) 공정의 금속배선방법에 관한 것으로, 자세하게는 트렌치 및 콘택홀에 구리금속을 매립하고 캡핑층에 비금속물질을 증착한 후 평탄화시키므로써, 금속 디싱(dishing)을 최소화하여 소자의 특성을 개선하기 위한, 금속캡핑층을 이용한 다마신구조의 금속배선방법에 관한 것이다.The present invention relates to a metal wiring method of a damascene process, and in detail, by embedding a copper metal in trenches and contact holes, and depositing a non-metallic material in a capping layer to planarize, thereby minimizing metal dishing. In order to improve the characteristics of the device, a metal wiring method of the damascene structure using a metal capping layer.

메모리소자의 집적도가 증가함에 따라, 향후 금속배선 형성방법이 기존의 반응성이온식각법(RIE)대신 다마신(damascene)방법으로 변화를 추구하고 있다. 이러 한 다마신방법은 비아(Via)의 매립이 가능하고 비용을 최소화하면서도 소자의 특성이 양호하게 개선시킬 수 있다. 아울러 0.13㎛이하의 논리소자 및 메모리소자에서 광범위하게 적용이 가능하다.As the integration of memory devices increases, metal wiring forming methods are being changed to damascene instead of conventional reactive ion etching (RIE). This damascene method allows the filling of vias and enables improved device properties while minimizing costs. In addition, it is widely applicable to logic devices and memory devices of less than 0.13㎛.

이러한 다마신 공정에서는 새로운 방식의 금속증착 및 금속연마기술이 요구된다. 종래에는 통상적으로 구리금속을 화학기상증착(Chemical Vapor Deposition; 이하 'CVD'라 함)방식으로 증착하여, 금속배선을 실시하였다.The damascene process requires a new method of metal deposition and metal polishing. Conventionally, copper metal is deposited by chemical vapor deposition (Chemical Vapor Deposition).

그러나, 전술한 종래 금속증착방식을 이용한 금속배선방법은 다음과 같은 문제점이 있다.However, the metal wiring method using the above-described conventional metal deposition method has the following problems.

CVD방식으로 구리(Cu)금속을 증착하는 경우, 구리의 증착두께가 너무 크기 때문에 증착효율이 낮은 문제점이 있다. 따라서 트렌치의 깊이에 비하여 약 50∼100%의 추가증착이 필요하다. 일례로 종래에는 트렌치의 깊이가 10000Å인 경우 구리금속은 약 15000∼20000Å을 증착하였다.When depositing a copper (Cu) metal by the CVD method, there is a problem that the deposition efficiency is low because the deposition thickness of copper is too large. Therefore, additional deposition of about 50-100% is required compared to the depth of the trench. For example, conventionally, when the depth of the trench is 10000 mm 3, copper metal deposits about 15000-20,000 mm 3.

전술한 구리금속의 추가증착은 후술공정에 많은 문제를 야기시켰다. 즉, 높게 증착된 구리를 화학기계적연마(CMP)로 평탄화시켜야 하기 때문에, 스크레치(scratch)등이 발생하여 CMP의 효율이 떨어지고, 넓은 금속패턴에서는 디싱(dishing)이 과도하게 발생하는 문제점이 있다. 또한 슬러리(slurry)의 소모량이 증가하여 단위공정당의 공정비용이 높다. The further deposition of the above-mentioned copper metal has caused many problems in the process described later. That is, since high-deposited copper must be planarized by chemical mechanical polishing (CMP), scratches, etc. occur, and thus the efficiency of CMP is reduced, and dishing is excessively generated in a wide metal pattern. In addition, the consumption of slurry (slurry) is increased, the process cost per unit process is high.

따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, 트렌치 및 콘택홀에 구리금속을 매립하고 캡핑층에 비금속물질을 증착한 후 평탄화시키므로써, 금속 디싱(dishing)의 최소화 및 CMP의 효율의 증대를 통하여 소자의 특성을 개선할 수 있는, 금속캡핑층을 이용한 다마신구조의 금속배선방법을 제공하는 데 있다.Accordingly, an object of the present invention for solving the above problems is to embed a copper metal in trenches and contact holes, and to planarize after depositing a non-metallic material on the capping layer, thereby minimizing metal dishing and increasing the efficiency of CMP. It is to provide a metal wiring method of the damascene structure using a metal capping layer, which can improve the characteristics of the device through.

본 발명에 따른 금속캡핑층을 이용한 다마신구조의 금속배선방법은, 금속배선을 위한 베이스층의 상부에 소정의 공간이 존재하도록 다마신 공정에 의한 다마신구조층을 형성하는 제1단계; 상기 다마신구조층의 표면에 확산방지막을 형성하는 제2단계; 상기 확산방지막이 형성된 상기 소정의 공간을 매립하도록 금속매립층을 형성하는 제3단계; 상기 금속매립층의 표면을 덮도록 CVD용 질화티타늄(TiN), PVD용 질화티타늄(TiN) 및 Si3N4물질 중 어느 하나로 이루어진 캡핑층을 형성하는 제4단계; 상기 캡핑층 및 금속매립층을 연마하여 상기 다마신구조층의 상부면을 기준으로 평탄화시키는 제5단계; 및 상기 평탄화된 다마신구조층의 상부표면에 상부증착막을 형성하는 제6단계;를 포함하는 것을 특징으로 한다. A metal wiring method of a damascene structure using a metal capping layer according to the present invention includes: a first step of forming a damascene structure layer by a damascene process such that a predetermined space exists on an upper portion of a base layer for metal wiring; Forming a diffusion barrier on the surface of the damascene structure layer; A third step of forming a metal buried layer to fill the predetermined space in which the diffusion barrier is formed; A fourth step of forming a capping layer made of any one of CVD titanium nitride (TiN), PVD titanium nitride (TiN), and Si 3 N 4 material to cover the surface of the metal buried layer; A fifth step of grinding the capping layer and the metal buried layer to planarize the upper surface of the damascene structure layer; And a sixth step of forming an upper deposition film on the upper surface of the planarized damascene structure layer.

삭제delete

이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 금속캡핑층을 이용한 다마신구조의 금속배선방법을 설명하기 위한 공정도이다.1A to 1E are process diagrams illustrating a metal wiring method of a damascene structure using a metal capping layer according to an embodiment of the present invention.

도 1a에 도시한 바와 같이, 본 실시예에서는 먼저 베이스층(10)상부에 공지된 이중(dual) 다마신 공정을 실시하여, 트렌치 또는 콘택홀 등이 존재하는 다마신구조층(12)을 형성한다. 베이스층(10)은 실리콘기판이나, 특정된 금속층 또는 동작 영역이 될 수 있다. 그리고 다마신구조층은 베이스층(10)의 상부로부터 절연막, 식각차단막 그리고 절연막이 차례로 증착된 상태로 형성된다.As shown in FIG. 1A, in the present embodiment, a known dual damascene process is first performed on the base layer 10 to form a damascene structure layer 12 having trenches or contact holes. do. The base layer 10 may be a silicon substrate, a specified metal layer or an operating region. The damascene structure layer is formed in such a manner that an insulating film, an etch barrier film, and an insulating film are sequentially deposited from the top of the base layer 10.

이 후 도 1b와 같이, 매립금속의 확산방지를 위해 다마신구조층(12)의 표면에 확산방지막(14)을 증착한다. 이 확산방지막(14)은 티타늄(Ti)계열이나 탄탈(Ta)계열의 물질을 이용한다. 티타늄(Ti)계열의 물질로 확산방지막(14)을 형성하는 경우, 먼저 티타늄(Ti)을 증착하고 그 표면에 질화티타늄(TiN)을 증착시킨다. 탄탈(Ta)계열의 물질로 확산방지막(14)을 형성하는 경우, 먼저 탄탈(Ta)을 증착하고 그 표면에 질화탄탈(TaN)을 증착시킨다. 이 후 In-Situ 방식에 따라 구리(Cu)금속으로 화학기상증착(CVD)공정을 실시하여 금속매립층(16)을 형성한다. 여기서 구리금속의 매립깊이는 종래기술과 달리, 형성된 트렌치 및 콘택홀의 깊이와 같다. 일예로 트렌치의 깊이가 10000Å이면 구리금속의 매립깊이도 10000Å이다. Thereafter, as shown in FIG. 1B, the diffusion barrier 14 is deposited on the surface of the damascene structure layer 12 to prevent diffusion of the buried metal. The diffusion barrier 14 is made of titanium (Ti) or tantalum (Ta). When the diffusion barrier layer 14 is formed of a titanium (Ti) -based material, first, titanium (Ti) is deposited and titanium nitride (TiN) is deposited on the surface thereof. When the diffusion barrier layer 14 is formed of a tantalum (Ta) -based material, tantalum (Ta) is first deposited and tantalum nitride (TaN) is deposited on the surface thereof. After that, a chemical vapor deposition (CVD) process is performed on a copper (Cu) metal according to an In-Situ method to form a metal buried layer 16. Here, the buried depth of the copper metal, unlike the prior art, is equal to the depth of the formed trench and contact hole. For example, if the trench depth is 10000 mm 3, the buried depth of the copper metal is 10000 mm 3.

이 후 도 1c와 같이, 금속매립층(16)의 상부에 캡핑물질을 증착시켜 500∼1000Å두께의 캡핑층(18)을 형성한다. 이 과정에서 캡핑물질로는 CVD용 질화티타늄(TiN), PVD(물리기상증착)용 질화티타늄(TiN), WN, Si3N4 등이 가능하지만, 산화물(Oxide) 계열은 사용하지 않는다.Thereafter, as shown in FIG. 1C, a capping material is deposited on the metal buried layer 16 to form a capping layer 18 having a thickness of 500 to 1000 mm 3. In this process, the capping material may be titanium nitride (TiN) for CVD, titanium nitride (TiN) for PVD (Physical Vapor Deposition), WN, Si 3 N4, etc., but oxide type is not used.

이 후 도 1d와 같이, 다마신구조층(12)의 상부까지 CMP를 실시하여 평탄화시킨다. 이 때, 상부의 캡핑층(18)은 300Å 이하가 되도록 연마함이 바람직하다. 이 과정에서는 다마신구조층(12)의 절연막(Oxide)이 종점(end point)이 되도록 EPM(End Point Monitor)방식으로 실시하며, 다마신구조층(12) 상부의 확산방지막(14)은 CMP를 가중하여 실시함으로써 제거시킨다. 이 후 CMP공정 후의 세정(cleaning)공정으로서 산성 및 염기성 용액을 적절히 사용하여, 불필요한 산화물 및 금속 등의 부산물을 제거한다. Thereafter, as shown in FIG. 1D, CMP is applied to the upper portion of the damascene structure layer 12 to be planarized. At this time, the upper capping layer 18 is preferably polished to 300 kPa or less. In this process, an end point monitor (EPM) method is used so that the oxide layer of the damascene structure layer 12 becomes an end point, and the diffusion barrier 14 on the damascene structure layer 12 is CMP. Remove by weighting. Thereafter, as a cleaning process after the CMP process, acid and basic solutions are appropriately used to remove unnecessary by-products such as oxides and metals.

이 후 도 1e와 같이, 실리콘나이트라이드를 증착하여 상부증착막(20)을 형성함으로써, 트렌치 및 콘택층이 매립된 다마신구조의 금속배선을 완성한다.Thereafter, as illustrated in FIG. 1E, silicon nitride is deposited to form the upper deposition layer 20, thereby completing a metal wiring having a damascene structure in which trenches and contact layers are embedded.

전술한 바와 같이, 본 발명은 트렌치 및 콘택홀에 구리금속을 매립하고 캡핑층에 비금속물질을 증착한 후 평탄화시키므로써, 금속 디싱(dishing)의 최소화 및 CMP의 효율의 증대를 통하여 소자의 특성을 개선하는 효과가 있다.
As described above, according to the present invention, a copper metal is embedded in trenches and contact holes, and a non-metallic material is deposited in the capping layer and then planarized, thereby minimizing metal dishing and increasing the efficiency of CMP. It is effective to improve.

Claims (19)

금속배선을 위한 베이스층의 상부에 소정의 공간이 존재하도록 다마신 공정에 의한 다마신구조층을 형성하는 제1단계; A first step of forming a damascene structure layer by a damascene process such that a predetermined space exists on an upper portion of the base layer for metal wiring; 상기 다마신구조층의 표면에 확산방지막을 형성하는 제2단계; Forming a diffusion barrier on the surface of the damascene structure layer; 상기 확산방지막이 형성된 상기 소정의 공간을 매립하도록 금속매립층을 형성하는 제3단계; A third step of forming a metal buried layer to fill the predetermined space in which the diffusion barrier is formed; 상기 금속매립층의 표면을 덮도록 CVD용 질화티타늄(TiN), PVD용 질화티타늄(TiN) 및 Si3N4물질 중 어느 하나로 이루어진 캡핑층을 형성하는 제4단계; A fourth step of forming a capping layer made of any one of CVD titanium nitride (TiN), PVD titanium nitride (TiN), and Si 3 N 4 material to cover the surface of the metal buried layer; 상기 캡핑층 및 금속매립층을 연마하여 상기 다마신구조층의 상부면을 기준으로 평탄화시키는 제5단계; 및 A fifth step of grinding the capping layer and the metal buried layer to planarize the upper surface of the damascene structure layer; And 상기 평탄화된 다마신구조층의 상부표면에 상부증착막을 형성하는 제6단계; A sixth step of forming an upper deposition film on an upper surface of the planarized damascene structure layer; 를 포함하는 것을 특징으로 하는, 금속캡핑층을 이용한 다마신구조의 금속배선방법.The metal wiring method of the damascene structure using a metal capping layer, comprising a. 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 제 1항에 있어서, 상기 제5단계는,The method of claim 1, wherein the fifth step, 상기 캡핑층의 두께가 약 300Å 이하가 되도록 연마하는 것을 특징으로 하는, 금속캡핑층을 이용한 다마신구조의 금속배선방법.And a metal capping layer, wherein the capping layer has a thickness of about 300 kPa or less. 삭제delete 삭제delete 삭제delete
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