KR20010001734A - Semiconductor device comprising poly SiGe gate having a low resistance - Google Patents

Abstract

PURPOSE: A semiconductor device having a low resistance polysilicon germanium gate is provided to reduce resistance of an alloy layer consisting of silicon and germanium, by forming a gate stack including germanium, by forming an impurity layer, by selectively forming a silicon layer on the gate stack and substrate, and by forming and annealing a metal layer on the entire surface, so that a metal silicide layer is formed on the gate stack and substrate. CONSTITUTION: A semiconductor device having a low resistance polysilicon germanium gate comprises a substrate(40), a trench(42), an isolation layer(44), a gate stack, a gate spacer(52), a metal silicide layer(66) and an impurity layer. The trench is formed in the substrate. The isolation layer fills the trench. The gate stack consists of a germanium-containing silicon layer and a metal silicide layer sequentially formed on the substrate between the trenches. A gate spacer is formed on a side surface of the gate stack under the metal silicide layer. The metal silicide layer is formed on the substrate between the gate spacer and the trench. The impurity layer is formed on the substrate between the gate stack and the trench.

Description

Semiconductor device comprising a low resistance poly-silicon germanium (P-Si) gate and a method for manufacturing the same {Semiconductor device comprising poly SiGe gate having a low resistance}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a low resistance poly-silicon germanium (P-SiGe) gate and a method for manufacturing the same.

Higher integration of semiconductor devices, increased operating speeds, and reduced power consumption are conditions that must always be considered in the manufacture of semiconductor devices. In order to satisfy these conditions, a method of using a silicide-based material having a low specific resistance to reduce the thickness of the gate oxide layer or reduce the resistance of the gate line has been proposed. However, when using a P ⁺ gate, the concentration of boron (B) doped in polysilicon is lowered near the gate / silicon oxide interface, which eventually results in an increase in Cox, thereby degrading the characteristics of the transistor.

As a solution to this problem, an alloy layer of polysilicon and germanium (Ge) and a method of forming a gate electrode using a polysilicon layer as a capping layer on the alloy layer are proposed, but the alloy layer in a subsequent heat treatment process There is a problem in that germanium is diffused from the capping layer to form a silicide layer having a high specific resistance in the silicideation process.

Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the resistance of a gate including an alloy layer made of silicon and germanium, in order to solve the problems of the prior art described above.

Another object of the present invention is to provide a method of manufacturing the above semiconductor device.

1 to 5 are cross-sectional views illustrating a semiconductor device having a low resistance poly silicon germanium (P-SiGe) gate and a method of manufacturing the same according to an embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40: substrate. 42: trench.

44: device isolation membrane. 46: gate insulating film.

48: polysilicon germanium. 50: first silicon layer.

52: gate spacer. 54, 56: source and drain regions.

58: Polysilicon layer in which germanium is diffused.

60, 62: second silicon layer.

64: metal layer. 66: metal silicide layer.

In order to achieve the above technical problem, the present invention provides a substrate, a trench formed in the substrate, a device isolation film filling the trench, a silicon layer comprising germanium sequentially formed on the substrate between the trench and a silicide layer of a metal selectively formed. A gate stack comprising: a gate spacer formed on a side of the gate stack under the metal silicide layer; a metal silicide layer formed on a substrate between the gate spacer and the trench; and a gate spacer formed on a substrate between the gate stack and the trench. Provided is a semiconductor device having a low-resistance silicon-germanium gate comprising an impurity layer.

According to an embodiment of the present invention, the gate stack is formed of a gate insulating film, an alloy layer made of silicon and germanium, a polysilicon layer formed on the alloy layer and diffused germanium from the alloy layer, and silicide of a metal selectively formed. It is characterized by consisting of layers.

According to the exemplary embodiment of the present invention, the gate spacer is formed on a side surface of the silicon layer including the gate insulating layer and the germanium.

According to an embodiment of the present invention, the silicon layer including germanium is formed of an alloy layer made of silicon and germanium, and a polysilicon layer in which germanium is diffused from the alloy layer.

According to an embodiment of the present invention, the metal silicide layer is at least one selected from the group consisting of a titanium silicide layer, a cobalt silicide layer, a nickel silicide layer, and a platinum silicide layer.

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device having a low resistance polysilicon germanium gate according to the present invention may include: (a) forming a trench in a substrate; (b) forming a device isolation layer filling the trench; Forming; (c) forming a gate stack comprising an alloy layer of polysilicon and germanium on the substrate between the trenches; (d) forming a shallow impurity layer in the substrate between the gate stack and the trench; (e) forming a gate spacer on the side of the gate stack; (f) forming an impurity layer deeper than the impurity layer formed in step (d) on the substrate between the gate spacer and the trench; (g) selectively forming a silicon layer on the gate stack and a substrate between the gate spacer and the trench; (h) forming a metal layer on the selectively formed silicon layer; And (i) annealing the resultant to form a metal silicide layer on the gate stack and the substrate between the gate spacer and the trench.

According to an embodiment of the present invention, the gate stack is formed by sequentially forming a gate insulating film, an alloy layer of polysilicon and germanium, and a silicon layer, and then patterning in a reverse order.

According to an embodiment of the present invention, the metal layer is formed using at least one selected from the group consisting of titanium, cobalt, nickel and platinum.

As such, in the case of adding a process of selectively forming a silicon layer on the gate including the alloy layer of polysilicon-germanium, the germanium is less in the silicon layer to form the metal silicide layer without increasing the specific resistance during the silicideation reaction. Can be. Therefore, it is possible to lower the resistance of the gate including the alloy layer of polysilicon-germanium.

Hereinafter, a semiconductor device having a low resistance poly-silicon germanium (P-SiGe) gate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention can be modified in many different forms, the scope of the invention should not be construed as limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements.

1 to 5 are cross-sectional views illustrating a semiconductor device having a low resistance polysilicon germanium (P-SiGe) gate and a method of manufacturing the same according to an embodiment of the present invention.

First, a semiconductor device including a low resistance polysilicon germanium (P-SiGe) gate according to an embodiment of the present invention will be described with reference to FIG. 5.

In detail, a trench 42 is formed in the substrate 40, and the trench 42 is filled with an isolation layer 44. A gate stack S is formed on the substrate 40 between the device isolation layers 44. The gate stack S may include a gate insulating layer 46, an alloy layer 48 of polysilicon and germanium, a polysilicon layer 58 in which germanium is diffused, and a metal silicide layer 66. The thickness of the alloy layer 48 of polysilicon and germanium is about 500 kPa to 2,500 kPa. The thickness of the polysilicon layer 58 in which the germanium is diffused is about 500 kPa to about 2,000 kPa. The metal silicide layer 66 is one selected from the group consisting of a titanium silicide layer, a cobalt silicide layer, a nickel silicide layer, and a platinum silicide layer. The gate spacer 52 is formed on the side of the gate stack S. Specifically, the gate insulating film 46 is formed on the side surface of the laminate made of the polysilicon and germanium alloy layer 48 and the germanium-diffused polysilicon layer 58. The metal silicide layer 66 is also formed on the substrate 40 between the gate spacer 52 and the trench 42. Impurity regions 54 and 56 of an LDD (Lightly Doped Drain) structure are formed on the substrate below the gate spacer 52. One of the impurity regions 54 of the LDD structure is a source region and the other is a drain region.

Next, a method of manufacturing a semiconductor device having the low resistance polysilicon germanium gate as described above will be described.

Referring to FIG. 1, the semiconductor substrate 40 is set as a field region and an active region. A trench 42 is then formed in the field region at a predetermined depth. An insulating material layer is formed on the substrate 40 to fill the trench 42. The entire surface of the insulating material film is planarized until the surface of the substrate 40 is exposed. As a result, the insulating material layer is removed on the substrate except for the trench 42, and the device isolation layer 44 is formed in the trench 42. A gate insulating layer 46, an alloy layer 48 of polysilicon and germanium, and a first silicon layer 50 are sequentially formed on the substrate 40 on which the device isolation layer 44 is formed. The first silicon layer 50 is a polysilicon layer. The alloy layer 48 of polysilicon and germanium is formed to a thickness of about 500 kPa to about 2,500 kPa. The first silicon layer 50 is formed to a thickness of about 500 kPa to about 2,000 kPa. After applying a photoresist film, for example, a photoresist film, on the first silicon layer 50, a photoresist is applied to form a photoresist pattern (not shown) defining a gate region. The first silicon layer 50, the alloy layer 48 of polysilicon and germanium, and the gate insulating layer 46 are sequentially anisotropically etched using the photoresist pattern as an etching mask. And the photosensitive film pattern is removed. As a result, a gate stack composed of the gate insulating film 46, an alloy layer 48 of polysilicon and germanium and the first silicon layer 50 is formed on a portion of the substrate 40 between the trenches 42. Water is formed. Thereafter, a buffer oxide layer (not shown) is formed on the substrate 40 to prevent the surface of the substrate 40 from being damaged in a subsequent ion implantation process. Subsequently, conductive impurities are implanted into the substrate 40 on which the gate stack S is formed to form shallow impurity layers 51 and 51a on the substrate between the gate stack S and the trench 42. .

Referring to FIG. 2, an insulating film (not shown) for forming a gate spacer is formed on the entire surface of the resultant product on which the shallow impurity layers 51 and 51a are formed. The entire surface of the insulating film is anisotropically etched until the surface of the substrate 40 is exposed. As a result, due to the characteristics of the anisotropic etching, the gate spacer 52 is formed on the side surface of the gate stack including the gate insulating layer 46, an alloy layer 48 of polysilicon and germanium, and the first silicon layer 50. ) Is formed. Subsequently, ion implantation is performed on the entire surface of the substrate 40 on which the gate spacer 52 is formed, and then the resultant is annealed to activate the conductive impurity. At this time, the ion implantation energy is larger than when the shallow impurity layers 51 and 51a are formed. As a result, an impurity layer deeper than the shallow impurity layers 51 and 51a is formed in the substrate 40 between the gate spacer 52 and the trench 42. However, the gate spacer 52 serves as a mask in the ion implantation process after the gate spacer 52 is formed to form a shallow impurity layer on the substrate 40 under the gate spacer 52. Therefore, impurity layers 54 and 56 of the LDD structure are formed on the substrate between the gate stack S and the trench 42. One of the impurity layers 54 and 56 of the LDD structure (for example, 54) is used as a source region and the other 56 is used as a drain region.

On the other hand, as can be seen by comparing Figures 1 and 2, the heat budget until the formation of the impurity layers 54 and 56 of the LDD structure, the property of the first silicon layer 50 is Different.

That is, germanium (Ge) is diffused from the alloy layer 48 of polysilicon and germanium formed under the first silicon layer 50 to the first silicon layer 50 by the heat budget. As a result, the first silicon layer 50 becomes a polysilicon layer 58 in which germanium is diffused. Thus, the alloy layer 48 of polysilicon and germanium and the polysilicon layer 58 in which the germanium is diffused together become a similar material layer including germanium.

Referring to FIG. 3, second silicon layers 60 and 62 are selectively formed only on the surfaces of the impurity layers 54 and 56 of the LDD structure and the surface of the polysilicon layer 58 in which the germanium is diffused. The second silicon layers 60 and 62 are formed by a selective epitaxial growth method. In this case, an epitaxial silicon layer is formed on the surfaces of the impurity layers 54 and 56 of the LDD structure, and a general polysilicon or amorphous polysilicon layer is formed on the surface of the polysilicon layer 58 in which the germanium is diffused. . The second silicon layers 60 and 62 are layers formed to cover silicon for subsequent silicide processes. Therefore, the thickness of the second silicon layers 60 and 62 is preferably formed to be the thickness of the silicon layer expected to be required for the subsequent silicide formation process.

Referring to FIG. 4, the metal layer 64 is formed on the entire surface of the substrate on which the second silicon layers 60 and 62 are formed. The metal layer 64 is formed of any one selected from the group consisting of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt). Subsequently, the resultant metal layer 64 is annealed to induce a silicidation reaction between the metal layer 64 and the second silicon layers 60 and 62. As a result, a metal silicide layer 66 is formed between the second silicon layers 60 and 62 and the metal layer 64. The metal silicide layer 66 is formed of one selected from a group consisting of a titanium silicide layer, a cobalt silicide layer, a nickel silicide layer, and a platinum silicide layer. Since the silicided reaction occurs between the second silicon layers 60 and 62 and the metal layer 64, the second silicon layers 60 and 62 of the metal layer 64 even after the silicided reaction is completed. The part which is not in contact with remains. Therefore, after the metal silicide layer 66 is formed, the metal layer that is not consumed by the silicideation reaction is removed. As a result, as shown in FIG. 5, the metal silicide layer 66 having low amorphousness is formed on the substrate 40 between the gate spacer 52 and the trench 42, and the germanium is diffused. The metal silicide layer 66 is also formed on the polysilicon layer 58, and the second gate stack S in which the low-resistance metal silicide layer 66 is added to the gate stack is the substrate 40. ) Is formed on.

Meanwhile, according to another embodiment of the present invention, an impurity layer, for example, the LDD, is formed on the substrate 40 without the first silicon layer (50 in FIG. 1) used as a capping layer. Impurity layers 54 and 56 of the structure may be formed. In this case, other materials than those mentioned above may be used as the metal layer 64.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those of ordinary skill in the art, instead of forming the second silicon layers 60 and 62, an alloy layer 48 and the second silicon layer 60 made of the polysilicon and germanium It is apparent that the present invention can be practiced by forming a diffusion barrier layer between the layers 62 and 62, or by transforming it into a layer of low resistance material other than the metal silicide layer 66. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, the semiconductor device according to the present invention includes a gate stack including an alloy layer made of polysilicon and germanium, wherein a low-resistance metal silicide layer is provided on the gate stack. Equipped. In addition, in order to manufacture such a semiconductor device, a gate stack including germanium is formed, and then a high temperature process such as an impurity layer is formed first, and then a silicon layer is selectively formed on the gate stack and the substrate. After forming, a metal layer is formed on the entire surface of the resultant and then annealed to form a metal silicide layer on the gate stack and the substrate. Therefore, by using the present invention, it is possible to lower the resistance of the gate electrode including the alloy layer made of silicon and germanium.

Claims (6)

Board; A trench formed in the substrate; An isolation layer filling the trench; A gate stack comprising a silicon layer comprising germanium sequentially formed on a substrate between the trenches and a silicide layer of metal optionally formed; A gate spacer formed on a side of the gate stack under the metal silicide layer; A metal silicide layer formed on a substrate between the gate spacer and the trench; And And a silicon germanium gate having a low resistance, the impurity layer formed on a substrate between the gate stack and the trench. 2. The gate stack of claim 1, wherein the gate stack is a gate insulating film, an alloy layer made of silicon and germanium, a polysilicon layer formed on the alloy layer and in which germanium is diffused from the alloy layer, and a silicide layer of the selectively formed metal. A semiconductor device having a low resistance silicon-germanium gate, characterized in that consisting of. 3. The semiconductor device according to claim 2, wherein the metal silicide layer is any one selected from the group consisting of a titanium silicide layer, a nickel silicide layer, a cobalt silicide layer, and a platinum silicide layer. (a) forming a trench in the substrate; (b) forming an isolation layer filling the trench; (c) forming a gate stack comprising an alloy layer of polysilicon and germanium on the substrate between the trenches; (d) forming a shallow impurity layer in the substrate between the gate stack and the trench; (e) forming a gate spacer on the side of the gate stack; (f) forming an impurity layer deeper than the impurity layer formed in step (d) on the substrate between the gate spacer and the trench; And (g) selectively forming a silicon layer on the gate stack and a substrate between the gate spacer and the trench; (h) forming a metal layer on the selectively formed silicon layer; And (i) annealing the resultant to form a metal silicide layer on the substrate between the gate stack and the gate spacer and the trench, wherein the semiconductor device has a low resistance silicon-germanium gate. Manufacturing method. The low-resistance silicon-germanium gate according to claim 4, wherein the gate stack is formed by sequentially forming a gate insulating film, an alloy layer of polysilicon and germanium, and a silicon layer, and patterning in reverse order. Method of manufacturing a semiconductor device. The method of claim 4, wherein the metal layer is formed using one selected from the group consisting of titanium, cobalt, nickel, and platinum. 6.