KR20000066339A - Method for Forming Silicide of Semiconductor Device - Google Patents
Method for Forming Silicide of Semiconductor Device Download PDFInfo
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- KR20000066339A KR20000066339A KR1019990013362A KR19990013362A KR20000066339A KR 20000066339 A KR20000066339 A KR 20000066339A KR 1019990013362 A KR1019990013362 A KR 1019990013362A KR 19990013362 A KR19990013362 A KR 19990013362A KR 20000066339 A KR20000066339 A KR 20000066339A
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- gate electrode
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- silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 23
- 229910021332 silicide Inorganic materials 0.000 title abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 4
- 238000010405 reoxidation reaction Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 게이트 저항을 줄이는데 적당한 반도체 소자의 실리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a method for forming silicide of a semiconductor device suitable for reducing gate resistance.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 실리사이드 형성방법을 설명하면 다음과 같다.Hereinafter, a silicide forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
종래 기술의 반도체 소자의 실리사이드 형성방법은 R. W. Mann, G. L. Miles, T. A. Knotts, D. W. Rakowski, L. A. Clevenger, J. M. Harper, F. M. D'Heure, and C. Cabral, Jr., "Reduction of the C54-TiSi2 phase transformation temperature using refractory metal ion implantation," Appl. Phys. Lett., vol.67, No.25, p3729, 18Dec. 1995.The silicide formation method of the semiconductor device of the prior art is RW Mann, GL Miles, TA Knotts, DW Rakowski, LA Clevenger, JM Harper, FM D'Heure, and C. Cabral, Jr., "Reduction of the C54-TiSi2 phase transformation temperature using refractory metal ion implantation, "Appl. Phys. Lett., Vol. 67, No. 25, p3729, 18 Dec. 1995.
즉, 도 1a 내지 도 1b는 종래의 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of forming silicide of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 게이트 절연막(12) 및 게이트 전극용 폴리 실리콘을 형성하고, 사진석판술 및 식각공정으로 상기 폴리 실리콘 및 게이트 절연막(12)을 선택적으로 제거하여 게이트 전극(13)을 형성한다.As shown in FIG. 1A, the gate insulating layer 12 and the polysilicon for the gate electrode are formed on the semiconductor substrate 11, and the polysilicon and the gate insulating layer 12 are selectively removed by photolithography and etching. The gate electrode 13 is formed.
이어, 상기 게이트 전극(13)을 포함한 반도체 기판(11)의 전면에 절연막을 형성한 후 에치백 공정을 실시하여 상기 게이트 전극(13)의 양측면에 측벽 스페이서(14)를 형성한다.Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 13, and then an etch back process is performed to form sidewall spacers 14 on both sides of the gate electrode 13.
도 1b에 도시한 바와 같이, 상기 게이트 전극(13) 및 측벽 스페이서(14)를 포함한 반도체 기판(11)의 전면에 티타늄(Ti)을 형성한 후 열처리하여 게이트 전극(13)과 반도체 기판(11)의 계면에 티타늄 실리사이드(Ti silicide)(15)를 형성한다.As shown in FIG. 1B, titanium (Ti) is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 13 and the sidewall spacers 14, and then heat treated to form the titanium electrode Ti and the semiconductor substrate 11. Titanium silicide (Ti silicide) 15 is formed at the interface.
이어, 상기 게이트 전극(13) 및 반도체 기판(11)과 반응하지 않는 티타늄을 제거한다.Next, titanium which does not react with the gate electrode 13 and the semiconductor substrate 11 is removed.
한편, 상기 티타늄 실리사이드(15)는 도면에는 도시하지 않았지만 게이트 전극(13) 양측의 반도체 기판(11) 표면내에 소오스/드레인 불순물 영역을 형성한 후 형성한다.Although not shown in the drawing, the titanium silicide 15 is formed after the source / drain impurity regions are formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode 13.
그러나 상기와 같은 종래의 반도체 소자의 실리사이드 형성방법은 다음과 같은 문제점이 있었다.However, the silicide formation method of the conventional semiconductor device as described above has the following problems.
즉, 게이트상에 티타늄 실리사이드를 형성할 때 게이트 폭이 감소함에 따라 게이트 에지(Edge)에서의 2-D 효과(2-Dimensional effect)로 인하여 실리사이드가 컨케이브(concave)한 모양으로 형성되어 폭이 감소됨에 따라서 저항의 급격한 증가와 웨이퍼상에서 요동(fluctuation)을 발생한다.That is, when forming the titanium silicide on the gate, as the gate width decreases, the silicide is formed into a concave shape due to the 2-Dimensional effect at the gate edge. As it decreases, a sharp increase in resistance and fluctuations occur on the wafer.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 게이트 저항의 증가 및 웨이퍼의 요동을 방지하도록 한 반도체 소자의 실리사이드 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a method of forming silicide of a semiconductor device to prevent an increase in gate resistance and fluctuation of a wafer.
도 1a 내지 도 1b는 종래의 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도1A to 1B are cross-sectional views illustrating a method of forming silicide of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도2A through 2D are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트 절연막21 semiconductor substrate 22 gate insulating film
23 : 게이트 전극 24 : 산화막23 gate electrode 24 oxide film
25 : 측벽 스페이서 26 : 티타늄 실리사이드25 side wall spacer 26 titanium silicide
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 실리사이드 형성방법은 반도체 기판상에 게이트 절연막을 개재하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 표면에 산화막을 형성하는 단계와, 상기 게이트 전극의 양측면에 측벽 스페이서를 형성하는 단계와, 상기 게이트 전극과 측벽 스페이서 사이의 양측면의 산화막을 선택적으로 제거하는 단계와, 상기 노출된 게이트 전극 및 반도체 기판의 표면에 티타늄 실리사이드를 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a silicide of a semiconductor device, the method including forming a gate electrode on a semiconductor substrate through a gate insulating film, forming an oxide film on a surface of the gate electrode, and Forming sidewall spacers on both sides of the gate electrode, selectively removing oxide films on both sides of the gate electrode and the sidewall spacers, and forming titanium silicide on the exposed gate electrode and the surface of the semiconductor substrate. It is characterized by including the formation.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 실리사이드 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a silicide forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 게이트 절연막(22) 및 게이트 전극용 폴리 실리콘을 형성하고, 사진석판술 및 식각공정으로 상기 폴리 실리콘 및 게이트 절연막(22)을 선택적으로 제거하여 게이트 전극(23)을 형성한다.As shown in FIG. 2A, the gate insulating film 22 and the polysilicon for the gate electrode are formed on the semiconductor substrate 21, and the polysilicon and the gate insulating film 22 are selectively removed by photolithography and etching. The gate electrode 23 is formed.
이어, 상기 게이트 전극(23)에 재산화(Re-oxidation)공정을 실시하여 게이트 전극(23)의 표면에 약 10~30nm 두께를 갖는 산화막(24)을 형성한다.Subsequently, a reoxidation process is performed on the gate electrode 23 to form an oxide film 24 having a thickness of about 10 to 30 nm on the surface of the gate electrode 23.
도 2b에 도시한 바와 같이, 상기 산화막(24)을 포함한 반도체 기판(21)의 전면에 질화막을 형성한 후, 전면에 에치백 공정을 실시하여 상기 게이트 전극(23)의 양측면에 측벽 스페이서(25)를 형성한다.As shown in FIG. 2B, after the nitride film is formed on the entire surface of the semiconductor substrate 21 including the oxide film 24, an etch back process is performed on the entire surface to form sidewall spacers 25 on both sides of the gate electrode 23. ).
도 2c에 도시한 바와 같이, 상기 측벽 스페이서(25) 및 게이트 전극(23)을 마스크로 이용하여 상기 게이트 전극(23)과 측벽 스페이서(25) 사이의 산화막(24)을 습식식각으로 선택적으로 제거한다.As shown in FIG. 2C, the oxide layer 24 between the gate electrode 23 and the sidewall spacers 25 is selectively removed by wet etching using the sidewall spacers 25 and the gate electrodes 23 as masks. do.
여기서 상기 산화막(24)의 식각량은 티타늄 갭 필(titanium gap fill)을 고려하여 표면으로부터 10~50nm로 조정하여 식각한다.The etching amount of the oxide layer 24 is etched by adjusting it to 10 to 50 nm from the surface in consideration of a titanium gap fill.
도 2d에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 티타늄을 형성한 후, 열처리 공정을 실시하여 상기 게이트 전극(23)과 반도체 기판(21)의 표면에 티타늄 실리사이드(26)를 형성한다.As shown in FIG. 2D, after forming titanium on the entire surface of the semiconductor substrate 21, a heat treatment process is performed to form titanium silicide 26 on the surfaces of the gate electrode 23 and the semiconductor substrate 21. do.
이어, 상기 게이트 전극(23) 및 반도체 기판(21)과 반응하지 않는 티타늄을 선택적으로 제거한다.Next, titanium that does not react with the gate electrode 23 and the semiconductor substrate 21 is selectively removed.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 실리사이드 형성방법에 있어서 게이트 측벽의 산화막을 일부 제거한 후 티타늄을 형성하고 열처리하여 티타늄 실리사이드를 형성함으로써 게이트 에지의 2D-효과를 제거하여 컨케이브 형태의 티타늄 실리사이드를 방지하여 저항 및 파동을 줄일 수 있는 효과가 있다.As described above, in the silicide formation method of the semiconductor device according to the present invention, after partially removing the oxide film on the sidewall of the gate, titanium is formed and heat treated to form titanium silicide to remove the 2D-effect of the gate edge, thereby eliminating titanium in a concave form. By preventing silicide, it is possible to reduce resistance and wave.
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| KR100562301B1 (en) | 2003-12-27 | 2006-03-22 | 동부아남반도체 주식회사 | Gate structure of transistor and manufacturing method therefor |
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| JPH10223889A (en) * | 1997-02-04 | 1998-08-21 | Mitsubishi Electric Corp | Mis transistor and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404231B1 (en) * | 2001-12-20 | 2003-11-05 | 주식회사 하이닉스반도체 | Method for Fabricating of Semiconductor Device |
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