KR20000062748A - Lcd panel and lcd device equipped therewith - Google Patents

Abstract

An LCD panel is provided that can optimize the timing of writing pixel data into an LC cell without the use of a timing controller. The panel comprises (a) a plurality of first signal lines extending along the rows of the matrix and aligned along the columns of the matrix, (b) a plurality of second signal lines extending along the columns and aligned along the rows; c) LC cells arranged in the array of matrices, (d) drive elements for driving each LC cell, and (e) a signal delay line for generating a temporary delay in the timing control signal, wherein the signal delay line comprises The signal delay line includes a first stage through which a timing control signal is input and a second stage through which a timing control signal including the delay is output. Each of the plurality of first signal lines is used to supply a selection signal to a drive element located in a corresponding one of the rows. Each of the plurality of second signal lines is used to supply a data signal to a drive element located in a corresponding one of the columns. The timing control signal including the delay is used for timing control of supplying the data signal to a driving element located in a corresponding column through a plurality of second signal lines.

Description

LCD panel and LCD apparatus having same {LCD PANEL AND LCD DEVICE EQUIPPED THEREWITH}

According to the present invention, there is a pair of transparent substrates, and a liquid crystal layer (LC) is inserted between the pair of transparent substrates, and a driving element such as a TFT and a metal-insulator-metal (MIM) element is provided. An LCD panel regularly aligned with one of the substrates, and an LCD device formed using the panel. More specifically, the present invention relates to a portable or non-portable display terminal as an active matrix address type that is applicable to a compact and lightweight display device having a relatively large display area and can display images in different resolution modes or aspects. The invention relates to LCD panels and LCD devices typically used in a variety of electronic devices.

1 and 2 are schematic diagrams respectively showing the configuration and operation of this type of conventional LCD device.

The conventional LCD device of FIG. 1 includes a TFT panel 120, which includes a plurality of LC cells 105 arranged in a matrix array of m rows and n columns (m and n are integers greater than 1). And a drain driver 107 for driving the panel, and a gate driver 108 for driving the panel. The first to mth rows of the matrix extend along the X axis of FIG. 1 at equal intervals and are aligned along the Y direction of FIG. 1. The first through nth columns of the matrix extend along the Y axis and aligned along the X direction at equal intervals.

The TFT 102 is formed in each of the plurality of LC cells 105. Each cell 105 serves as a capacitor with a display electrode (not shown) and a common electrode (not shown). Thus, this cell 105 is represented by the symbol of the capacitor in FIG. Each cell 105 corresponds to a pixel of an LCD device.

The display electrode is formed on the inner surface of the transparent glass substrate 101 together with the TFT 102, and the common electrode is formed on the inner surface of another transparent glass substrate (not shown) bonded to the substrate 101 to display the display electrode. Are placed opposite. Of course, the LC layer is formed in the space between the substrate 101 and the opposing substrate.

On the inner surface of the substrate 101, the first to mth gate lines 128-1, 128-2, ..., 128-m, the first to nth drain lines 127-1, 127-2 , ..., 127-n, and the TFT 102 are formed. m gate lines 128-1 through 128-m extend along the m row of the matrix, respectively. The n drain lines 127-1 to 127-n extend along the n columns of the matrix, respectively. The TFT 102 is located at each intersection of the gate lines 128-1 to 128-m and the drain lines 127-1 to 127-n. Therefore, the total number of TFTs 102 is (m × n).

Gate lines 128-1 to 128-m parallel to each other are electrically connected to the gate driver 108 located outside the substrate 101. Drain lines 127-1 to 127-n parallel to each other and perpendicular to the gate lines 128-1 to 128-m are electrically connected to the drain driver 107 located outside the substrate 101.

Each of the n drain lines 127-1 to 127-n is aligned with the corresponding drain lines 127-1, 127-2, ..., 127-n (ie, corresponding columns of the matrix). It is electrically connected to the drain electrode D of 102. Each of the m gate lines 128-1 to 128-m is TFTs aligned along corresponding gate lines 128-1, 128-2,..., 128-m (ie, corresponding rows of the matrix). It is electrically connected to the gate electrode G of 102.

The source S of each TFT 102 is electrically connected to one of two electrodes (ie, corresponding display electrodes) forming the corresponding LC cell 105 formed on the substrate 101. The other electrode (ie, common electrode) of cell 105 is electrically connected to a common voltage source, for example ground.

The vertical start signal VSP0 and the vertical shift clock signal VCK0 are applied to the gate driver 108. In response to the signals VSP0 and VCK0, the gate driver 108 generates select signals VG1, VG2,..., VGm to select the corresponding one of the rows of the matrix, and then select the corresponding gate line 128. -1, 128-2, ..., 128-m) respectively.

The drain driver 107 is supplied with an image signal DAT0, a horizontal start signal HSP0, a horizontal shift clock signal HCK0, and a latch signal LP0. In response to the signals DAT0, HSP0, HCK0, and LP0, the drain driver 107 generates the pixel data signals HD1, HD2, ..., HDn to form an image, and then forms the corresponding drain line ( 127-1 to 127-n). The supply or input of these pixel data signals HD1 to HDn is controlled by the latch signal LP0.

The conventional LCD device shown in Fig. 1 operates as follows.

When the horizontal start signal HSP0 is applied to the drain driver 107, the image signal DAT0 for one of the m rows of the matrix starts to be input to the driver 107. The input of the image signal DAT0 is performed to be synchronized with the application of the horizontal shift clock signal HCK0. Based on the applied image signal DAT0, the drain driver 107 generates the pixel data signals HD1 to HDn for one of the m rows of the matrix, and then simultaneously drains them to the drain line 127-1 at a specific timing. To 127-n).

On the other hand, when the vertical start signal VSP0 is applied to the gate driver 108, generation of the selection signals VG1 to VGm is started. Thereafter, the driver 108 supplies the selection signals VG1 to VGm simultaneously to the gate lines 128-1 to 128-m, respectively. As shown in Fig. 2, since each of the signals VG1 to VGm includes a pulse, the TFT 102 to which the signals VG1, VG2, ..., VGm are applied to the gate electrode is turned on. It becomes Through the TFT 102 thus turned on, the drain lines 127-1 to 127-n are electrically connected to the corresponding LCD cells 105, so that the cells 105 aligned along one of the m rows of the matrix. Select. Since the pulses of the signals VG1 to VGm are continuously shifted in phase with each other, the cells 105 aligned along each of the first to mth rows of the matrix are continuously selected.

After the pixel data signals HD1 to HDn are respectively supplied to the selected cells 105 located in the selected rows of the matrix, the pixel data included in the signals HD1 to HDn are written to the selected cells. Thus, the cell 105 is driven by the signals HD1 to HDn to display an image on the screen of the conventional LCD device corresponding to the pixel data thus written.

Typically, the selection signals VG1 to VGm each have waveforms A1 to Am indicated by solid lines in FIG. 2 at the input terminals 128-1A to 128-mA of the gate lines 128-1 to 128-m. On the other hand, the signals VG1 to VGm each have waveforms B1 to Bm indicated by broken lines in Fig. 2 at the output terminals 128-1B to 128-mB of the lines 128-1 to 128-m. It can be seen from FIG. 2 that each waveform B1 to Bm includes the rising and falling edges of the obtuse angle at the output terminals 128-1B to 128-mB. The rising and falling edges of the obtuse angle of the waveforms B1 to Bm will cause a temporary shift or phase delay Δt ₀ of the waveforms A1 to Am. The shift or delay Δt ₀ is known as the "gate line delay", which is induced by the resistance of the lines 128-1 to 128-m and parasitic capacitance near the lines 128-1 to 128-m.

Therefore, the application timing of the pixel data signals HD1 to HDn needs to be appropriately adjusted in consideration of the "gate line delay Δt ₀ ". Otherwise, the pixel data contained in the signals HD1 to HDn cannot be correctly written to all corresponding LC cells 105.

For example, as shown in Fig. 2, it is assumed that the pixel data writing operation from the signals HD1 to HDn for the first row of the matrix to the corresponding cell 105 is started at time TA1. At this time, the selection signal VG1 rises at the input terminal 128-1A of the gate line 128-1. Thereafter, the writing operation of the pixel data in the signals HD1 to HDn for the second row of the matrix into the corresponding cell 105 is started at time TA2. In this case, all the TFTs 102 connected to the gate line 128-1 are not turned off, and consequently the pixel data included in the signals HD1 to HDn for the second row are located in the first row. There is a problem of writing to the cell 105.

To prevent this, in the conventional LCD device of Fig. 1, there is a vertical shift clock signal (VCK0) supplied to the gate driver 108 so that the phase is forward shifted by a period △ t ₀ 'with respect to the latch signal (LP0), This period Δt ₀ ′ is _equal to the gate line delay Δt ₀ . That is, the gate line delay Δt ₀ is compensated by giving a time difference Δt ₀ '(= Δt ₀ ) between the signals VCK0 and LP0. Due to this compensation, the pixel data signals HD1 to HDn are supplied to the drain lines 127-1 to 127-n at the delayed times TB1 to TBm, respectively. As a result, pixel data included in the signals HD1 to HDn can be correctly written to all the cells 105.

The period or time difference Δt ₀ ′ between the signals VCK0 and LP0 is generated by a timing controller (not shown) that controls the drain driver 107 and the gate driver 108. The time difference Δt ₀ ′ is generated by counting the number of pulses of the horizontal shift clock signal HCK0 to a specific value.

In general, when the LCD device is designed to be applicable to several different resolution modes or aspects (i.e., different number of pixels used), the pulse length of the horizontal shift clock signal HCK0 needs to be changed according to the selected resolution mode or aspect. . From the above, the number of pulses of the signal HCK0 needs to have a different value according to the different pulse lengths required. Thus, a problem arises in that the configuration of the timing controller is complicated and its dimensions are expanded.

Another conventional LCD device of this kind is disclosed in Japanese Patent Laid-Open No. 63-261389 published in 1988. In this apparatus, the pixel data writing operation to the LC cell is delayed with respect to the vertical shift clock signal by using an analog delay circuit provided outside the TFT panel.

However, in the conventional LCD device disclosed in Publication No. 63-261389, an integrator circuit and Schmitt trigger amplifier formed of resistor (s) and capacitor (s) must be provided outside the TFT panel. Therefore, the configuration of the driver circuit of the TFT panel is complicated and it is difficult to reduce the number of necessary electronic components.

Accordingly, it is an object of the present invention to provide an LCD panel and an LCD device capable of optimizing the timing of writing pixel data into an LC cell without the use of a timing controller.

Another object of the present invention is to provide an LCD panel and an LCD device that simplify the configuration of a driver circuit.

These objects, together with other objects not specifically mentioned, will become apparent to those skilled in the art from the following description.

According to the first aspect of the present invention,

(a) a plurality of first signal lines extending along the rows of the matrix and aligned along the columns of the matrix,

(b) a plurality of second signal lines extending along the columns of the matrix and aligned along the rows of the matrix,

(c) LC cells aligned with the array of matrices,

(d) driving elements for driving the respective LC cells, and

(e) Signal delay line causing temporary delay in timing control signal

Including,

The signal delay line extends along the rows of the matrix and is formed so as not to be electrically connected to the drive element.

The signal delay line includes a first stage through which the timing control signal is input and a second stage through which the timing control signal including the delay is output.

An LCD panel is provided.

Each of the plurality of first signal lines is used to supply a selection signal to a drive element located in a corresponding one of the rows of the matrix. Each of the plurality of second signal lines is used to supply a data signal to a driving element located in a corresponding one of the columns of the matrix.

The timing control signal including the delay is used for timing control to supply the data signal to driving elements located in corresponding columns of the matrix via a plurality of second signal lines.

Using the LCD panel according to the first aspect of the present invention, a signal delay line extending along the rows of the matrix (ie, the plurality of first signal lines) is provided to generate the delay in the timing control signal. The timing control signal including the delay generated by the signal delay line is used for timing control of supplying the data signal to driving elements located in corresponding columns of the matrix.

Since the signal delay line crosses the plurality of second signal lines as in the case of the plurality of first signal lines, the delay amount of the timing control signal is approximately equal to the delay amount of the selection signal generated by the plurality of second signal lines. This means that the data signal is supplied to the driving device at an optimized timing corresponding to the delay amount of the selection signal.

Further, even if the delay amount of the selection signal changes due to the change of the resolution mode or the aspect, the delay amount of the timing control signal changes automatically in accordance with the change in the delay amount of the selection signal.

As a result, the timing of writing the image data into the LC cell can be optimized without using any timing controller even if the resolution mode changes.

In addition, since a complicated driving configuration is not necessary, the configuration of the driver circuit can be simplified.

In a preferred embodiment of the panel according to the first aspect of the invention, the signal delay line has approximately the same electrical characteristics as that of the plurality of first signal lines. In this embodiment, there is an additional advantage that the temporary delay in the timing control signal is substantially or exactly the same as the temporary delay of the selection signal, whereby the temporary delay in the selection signal is completely compensated.

The electrical characteristics of the signal delay line generally include the electrical resistance and parasitic capacitance of the signal delay line. However, it may also include other factors that affect the temporary delay in the timing control signal.

In another embodiment of the panel according to the first aspect of the present invention, the signal delay line is located on the input side of the data signal to the plurality of second signal lines. In this embodiment, there is an additional advantage that the temporary delay amount of the timing control signal can be substantially or completely the same as the temporary delay amount of the selection signal generated by the plurality of second signal lines. This is because the connection line of the signal delay line to the drain driver can be as short as possible.

In another embodiment of the panel according to the first aspect of the invention, the driving element is a TFT. Each of the plurality of first signal lines is electrically connected to the gate electrode of the TFT located in the corresponding one of the rows of the matrix. Each of the plurality of second signal lines is electrically connected to a source or drain electrode of a TFT located in a corresponding one of the columns of the matrix.

In another embodiment of the panel according to the first aspect of the invention, the timing control signal comprising a delay at the second end of the signal delay line is approximately equal to each of the selection signals at the corresponding rear end of the plurality of second signal lines. It has a waveform having rising and falling edges of an obtuse angle.

Preferably, each of the plurality of first signal lines is substantially perpendicular to the plurality of second signal lines. It is preferable that the TFT is a TFT because the TFT is used very much and provides a high picture quality.

According to a second aspect of the invention,

(a) a plurality of first signal lines (a-1) extending along the rows of the matrix and aligned along the columns of the matrix,

(a-2) a plurality of second signal lines extending along the columns of the matrix and aligned along the rows of the matrix,

(a-3) LC cells aligned to the array of matrices,

(a-4) a driving element for driving each LC cell, and

(a-5) a signal delay line for generating a temporary delay in the timing control signal,

The signal delay line extends along the rows of the matrix and is formed so as not to be electrically connected to the drive element.

The signal delay line includes a first stage through which a timing control signal is input and a second stage through which a timing control signal including the delay is output.

LCD panel,

(b) a selection signal source for respectively supplying a selection signal to the plurality of first signal lines, and

(c) data signal sources for supplying data signals to a plurality of second signal lines, respectively

Provided is an LCD device comprising a.

Each selection signal is supplied from a selection signal source to a driving element located in a corresponding one of the rows of the matrix via a corresponding one of the plurality of first signal lines.

Each data signal is supplied from a data signal source to a driving element located in a corresponding one of the columns of the matrix via a corresponding one of the plurality of second signal lines.

The timing control signal including the delay is applied to a data signal source to perform timing control of supplying a data signal to a driving element located in a corresponding column of a matrix via a plurality of second signal lines.

Using the LCD device according to the second aspect of the present invention, the LCD panel according to the first aspect of the present invention is combined with a selection signal source and a data signal source. Thus, for approximately the same reason as that of the panel according to the first aspect, the timing of writing image data into the LC cell can be optimized without using any timing controller even if the resolution mode is changed. Also, the configuration of the driver circuit can be simplified.

In a preferred embodiment of the device according to the second aspect of the invention, the signal delay line has approximately the same electrical characteristics as that of the plurality of first signal lines. In this embodiment, there is an additional advantage that the temporary delay in the timing control signal is substantially or exactly the same as the temporary delay of the selection signal, thereby completely compensating the temporary delay in the selection signal.

In another embodiment of the apparatus according to the second aspect of the present invention, the signal delay line is located on the input side of the data signal to the plurality of second signal lines. In this embodiment, there is an additional advantage that the temporary delay amount of the timing control signal can be substantially or exactly the same as that of the selection signal generated by the plurality of second signal lines. This is because the connection line of the signal delay line to the drain driver can be as short as possible.

In another embodiment of the device according to the second aspect of the invention, the drive element is a TFT. Each of the plurality of first signal lines is electrically connected to a gate electrode of a TFT located in a corresponding one of the rows of the matrix. Each of the plurality of second signal lines is electrically connected to a source or drain electrode of a TFT located in a corresponding one of the columns of the matrix. In this embodiment, there is an additional advantage that the advantages of the present invention are markedly realized.

In another embodiment of the apparatus according to the second aspect of the present invention, the selection signal is respectively supplied to the plurality of first signal lines so as to be synchronized with the timing control signal not including the delay.

In another embodiment of the apparatus according to the second aspect of the invention, a timing control signal comprising said delay has rising and falling edges of an obtuse angle approximately equal to that of each selection signal at corresponding rear ends of the plurality of second signal lines. Has a waveform.

1 is a schematic diagram showing the configuration of a conventional LCD device;

Fig. 2 is a timing diagram showing the operation of the conventional LCD device shown in Fig. 1;

3 is a schematic diagram of an LCD device according to a first embodiment of the present invention;

4 is a timing diagram showing an operation of the LCD device shown in FIG. 3;

5 is a schematic diagram of an LCD device according to a second embodiment of the present invention;

Brief description of symbols for the main parts of the drawings

1: glass substrate 2: TFT

5: LC cell 7: drain driver

8: gate driver 9: signal delay line

12: latch signal terminal 20: TFT panel

27-1, .., 27-n: drain line 28-1, .., 28-m: gate line

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described.

First embodiment

The LCD device according to the first embodiment takes the configuration shown in FIG.

As can be seen from FIG. 3, the LCD device is composed of a TFT panel 20, a drain driver 7 for driving the panel 20, and a gate driver for driving the panel 20. As shown in FIG.

Panel 20 includes a plurality of LC cells 5 arranged in a matrix array of m rows and n columns. The first to mth rows of the matrix extend along the X axis of FIG. 3 at equal intervals and are aligned along the Y direction of FIG. 3. The first through nth columns of the matrix extend along the Y axis of FIG. 3 at equal intervals and are aligned along the X direction of FIG. 3.

The TFT 2 is formed in each of the plurality of LC cells. For the same reasons as described above, each cell 5 is shown in FIG. 3 by a capacitor symbol. Each cell 5 corresponds to one pixel of the LCD device.

The TFT panel 20 includes a transparent glass substrate 1, another transparent glass substrate (not shown), and an LC layer (not shown) formed in the space between the substrate 101 and the opposing substrate.

On the inner surface of the substrate 1, the first to mth gate lines 28-1, 28-2, ..., 28-m, the first to nth drain lines 27-1, 27-2 , ..., 27-n), and TFT 2 are formed. The m gate lines 28-1 through 28-m each extend along the m rows of the matrix. The n drain lines 27-1 through 27-n extend along the n columns of the matrix, respectively. The TFT 2 is located at the intersection of the gate lines 28-1 to 28-m and the drain lines 27-1 to 27-n. Therefore, the total number of TFTs 2 is (m × n).

Gate lines 28-1 to 28-m parallel to each other are electrically connected to the gate driver 8 located outside the substrate 1 and the panel 20. The drain lines 27-1 to 27-n parallel to each other and perpendicular to the gate lines 28-1 to 28-m are electrically connected to the drain driver 7 located outside the substrate 1 and the panel 20. do.

Each of the n drain lines 27-1 to 27-n is arranged TFTs along corresponding drain lines 27-1, 27-2,..., 27-n (ie, corresponding columns of the matrix). It is electrically connected to the drain electrode D of (2). Each of the m gate lines 28-1 to 28-m is a TFT aligned along a corresponding line 28-1, 28-2,..., 28-m (ie, a corresponding row of the matrix) ( It is electrically connected to the gate electrode G of 2).

The source S of each TFT 2 is electrically connected to one of the two electrodes forming the corresponding LC cell 5, namely the corresponding display electrode (not shown) formed on the substrate 1. The other electrode of the cell 5 (ie the common electrode) is electrically connected to a common voltage source, for example ground.

The signal delay line 9 is formed on the inner surface of the substrate 1 so as to extend parallel to the gate lines 28-1 to 28-m between the first gate line 28-1 and the drain driver 7. . In other words, the line 9 is located on the drain driver side of the substrate 1. Line 9 is perpendicular (ie crosses) to drain lines 27-1 to 27-n. None of the TFTs 2 are electrically connected to the line 9. The vertical shift clock signal VCK is applied to the input terminal 9a of the line 9 located on the substrate 1 side near the gate driver 8 in order to determine the scanning timing of the gate driver 8. The output terminal 9b of the line 9 located on the substrate 1 on the opposite side of the gate driver 8 is electrically connected to the latch signal terminal 12 of the drain driver 7.

The vertical start signal VSP and the vertical shift clock signal VCK are applied to the gate driver 8. In response to the signals VSP and VCK, the gate driver 8 generates the selection signals VG1, VG2, ..., VGm to select the corresponding one of the rows of the matrix, and then select them from the corresponding gate lines 28. -1 to 28-m).

An image signal DAT, a horizontal start signal HSP, a horizontal shift clock signal HCK, and a latch signal LP are applied to the drain driver 7. The latch signal LP is applied to the driver 7 at the latch terminal 12 of the driver 7 via the signal delay line 9. In response to the signals DAT, HSP, HCK, LP, the drain driver 7 generates the pixel data signals HD1, HD2,..., HDn to form an image, and thereafter, the drain driver 7 -1 to 27-n). The supply or input of the pixel data signals HD1 to HDn is controlled by the latch signal LP.

The LCD device according to the first embodiment as shown in Fig. 1 operates as follows.

4 shows waveforms of the vertical start signal VSP, the selection signals VG1 to VGm, the latch signal LP, and the pixel data signals HD1 to HDn. In Fig. 4, solid lines A1, A2, ..., Am are input terminals 28-1A, 28-2A, ... of the gate lines 28-1, 28-2, ..., 28-m. , 28-mA), and the waveforms of the signals VG1, VG2, ..., VGm, respectively. The broken lines B1, B2, ..., Bm are the output terminals 28-1B, 28-2B, ..., 28-mB of the gate lines 28-1, 28-2, ..., 28-m. The waveforms of the same signals (VG1, VG2, ..., VGm) in Fig. 2) are shown.

When the horizontal start signal HSP is applied to the drain driver 7, the input of the image signal DAT for the first row of the matrix to the driver 7 is started. The input of the image signal DAT is performed to be synchronized with the application of the horizontal shift clock signal HCK. On the basis of the applied image signal DAT, the drain driver 7 generates the pixel data signals HD1 to HDn for one of the m rows of the matrix, and then applies them to the drain lines 27-1 to a specific timing. 27-n) at the same time.

On the other hand, when the vertical start signal VSP is applied to the gate driver 8, the generation of the first selection signal VG1 is started. Thereafter, the driver 8 supplies the selection signal VG1 thus generated to the first gate line 28-1. As shown in Fig. 4, since the signal VG1 includes a rectangular pulse, the TFT 2 to which the signal VG1 is applied at the gate electrode G is turned on. Through the TFTs 2 turned on in this way, the drain lines 27-1 to 27-n are electrically connected to the corresponding LCD cells 5, thereby aligning the cells 5 aligned along the first row of the matrix. Choose. Thus, the pixel data signals HD1 to HDn can be supplied to the cell 5 located in the first row of the matrix and the image data contained in the signals HD1 to HDn can be written there.

At this time, the first selection signal VG1 transmitted from the gate driver 8 includes the electrical resistance of the gate lines 28-1 to 28-m, the parasitic capacitance present (that is, the gate line 28-1 and the drain). Parasitic capacitance caused by crossing with lines 27-1 to 27-n) and the like. That is, as shown in FIG. 4, since the rising and falling edges of the waveform A1 of the signal VG1 at the output terminal 28-1B of the gate line 28-1 become obtuse angles, the signal VG1 is gated. It has a waveform B1 at the output terminal 28-1B of the line 28-1. This means that the signal VG1 at the output terminal 28-1B is delayed by a period or time difference of Δt ₀ relative to the signal VG1 at the input terminal 28-1A. As a result, a so-called gate line delay time [Delta] t appears between the turn-on time of the TFT 2 located in the first column of the matrix and the turn-on time of the TFT 2 located in the nth column.

Using the LCD device according to the first embodiment of FIG. 3, the latch terminal 12 of the drain driver 7 is electrically connected to the output terminal 9b of the signal delay line 9, and the line 9 is a drain line. (27-1 to 27-n). Therefore, the vertical shift clock signal VCK applied to the gate driver 8 and the input terminal 9a of the line 9 is delayed in the same manner as that of the first selection signal VG1, so that the output terminal 9b of the line 9 is delayed. Becomes a delayed vertical shift clock signal (VCK '). That is, the waveform of the delayed vertical shift clock signal VCK 'has an obtuse rising and falling edge as shown in Fig. 4, which is a selection signal at the input terminal 28-1A of the first gate line 28-1. A temporary delay of Δt 'is generated for (VG1). The delay Δt 'is substantially equal to the gate line delay time Δt. The delayed vertical shift clock signal VCK 'is applied to the drain driver 7 as the latch signal LP through the latch terminal 12.

In response to the delayed vertical shift clock signal VCK 'or latch signal LP, the drain driver 7 drains the pixel data signals HD1 to HDn at a timing TB1 synchronized with the signal VCK' or LP. It outputs simultaneously with the lines 27-1 to 27-n. Therefore, the image data in the signals HD1 to HDn are written into the cell 5 located in the first row of the matrix at time TB1 when all the TFTs 2 in the first row are turned on.

Next, similarly to that of the first row, the image signal DAT for the second row of the matrix is input to the drain driver 7 in synchronization with the application of the horizontal shift clock signal HCK. Based on the applied image signal DAT, the drain driver 7 generates the pixel data signals HD1 to HDn for the second row of the matrix, and then simultaneously displays them in the drain lines 27-1 to 27-n. To each supply.

The gate driver 8 generates the selection signal VG2 from the vertical shift clock signal VCK similarly to the signal VG1, and then supplies it to the second gate line 28-2.

As can be seen from Fig. 4, due to the rising and falling edges of the obtuse angle of the waveform A2 of the signal VG2 at the output terminal 28-2B of the gate line 28-2, the signal VG2 is output to the output terminal. It has a waveform B2 at 28-2B. This means that the signal VG2 at the output terminal 28-2B is delayed by a period or time difference of Δt relative to the same signal VG2 at the input terminal 28-2A. As a result, a so-called gate delay time Δt appears in the signal VG2. The signal VCK has a delay time DELTA t 'equal to DELTA t. Accordingly, the pixel data signals HD1 to HDn are applied to the drain lines 27-1 to 27-n by the drain driver 7 at the timing TB2 to be synchronized with the signal VCK 'or LP. Therefore, the signals HD1 to HDn are written into the cell 5 located in the second row of the matrix at time TB2 when all the TFTs 2 in the second row are turned on.

At time TB2, all the TFTs 2 connected to the first gate line 28-1 are turned off. Therefore, the image data written into the cell 5 located in the first row from the pixel data signals HD1 to HDn is invariant. Further, the signals HD1 to HDn for the second row of the matrix are drain lines 27-1 at time TB2 when all the TFTs 2 connected to the second gate line 28-2 are turned off. To 27-n), the data in the signals HD1 to HDn for the second row are not written into the cell 5 located in the first row.

The above process is repeated for the third to mth rows of the matrix. The pixel data signals HD1 to HDn for the m th row are drain lines 27-1 to 27 at a time TBm when all the TFTs 2 connected to the m th gate line 28-2 are turned off. -n). As a result, the image data in the signals HD1 to HDn for the first to mth rows are written into all the cells 5 to display the frame of the desired image.

Using the LCD device according to the first embodiment of Fig. 3, a signal delay line 9 extending along the first to mth rows of the matrix is provided, which is connected to the gate lines 28-1 to 28-m. It is parallel and perpendicular to the drain lines 27-1 to 27-n. The timing control clock signal VCK is applied not only to the gate driver 8 but also to the input terminal 9a of the line 9, so that the timing control clock signal VCK '(i.e., latch) is output from the output terminal 9b of the line 9. Signal LP). The delayed timing control clock signal VCK 'thus generated is used to control or adjust the timing of supplying the data signals HD1 to HDn to the TFTs 2 located in each column of the matrix.

Since the signal delay line 9 intersects the first to nth drain lines 27-1 to 27-n similarly to the first to mth gate lines 28-1 to 28-m, the initial timing control clock The temporary delay amount of the delayed timing control clock signal VCK 'relative to the signal VCK is approximately or substantially the same as that of the selection signals VG1 to VGm generated by the gate lines 28-1 to 28-m. This means that the data signals HD1 to HDn are supplied to the TFT 2 at an optimum timing corresponding to the delay amount of the selection signals VG1 to VGm.

Further, even if the delay amount of the selection signals VG1 to VGm is changed by the resolution mode or the change of the aspect, the delay amount of the delayed timing control clock signal VCK 'or the latch signal LP is determined by the selection signals VG1 to VGm. It changes automatically with the change in delay amount.

As a result, the timing of writing the image data contained in the signals HD1 to HDn into the LC cell 5 can be optimized without using any timing controller even if the resolution mode changes.

In addition, since no complicated driving configuration is necessary, the configuration of the driver circuits 7 and 8 can be simplified.

Second embodiment

FIG. 5 shows the configuration of the LCD device according to the second embodiment, except that the drain driver 7 and the signal delay line 9 are in different positions from the first embodiment. It has the same configuration as that of the LCD device according to the first embodiment. Therefore, for the sake of simplicity, the description of the same configuration is omitted by attaching the same member number as used in the first embodiment in FIG.

As can be seen in FIG. 5, the LCD device is composed of a TFT panel 20A, a drain driver 7 for driving the panel 20A, and a gate driver 8 for driving the panel 20A.

Unlike in the first embodiment, the drain driver 7 is located below the substrate 1 outside the panel 20A in FIG. That is, the driver 7 is located on the opposite side to the driver in the first embodiment. In response to the position of the driver 7, the signal delay line 9 is located below the substrate 1 so as to be adjacent to the driver 7. The line 9 is orthogonal to the drain lines 27-1 to 27-n and parallel to the gate lines 28-1 to 28-m.

In general, the drain driver 7 can be located above or below the substrate 1 depending on the design of the LCD device. In consideration of this, the signal delay line 9 is located on the same side as that of the driver 7. In this case, there is an additional advantage that the wiring connected to the line 9 to the outside of the TFT panel 20A can be as short as possible.

If the wiring length with respect to the signal delay line 9 is too long, the delay period DELTA t 'of the delayed vertical shift clock signal VCK' or latch signal LP is larger than the gate line delay time DELTA t, This prevents the compensation from being optimized. In contrast, because of the shortest possible wiring connected to the line 9, optimum compensation is ensured in the LCD device according to the second embodiment.

Of course, the LCD device according to the second embodiment has the same advantages as that of the LCD device according to the first embodiment.

In the above first and second embodiments, a TFT (i.e., a three-dimensional element) is used as the driving element for the LC cell 5. However, the present invention is not limited to this. A MIM element (ie a two-terminal element) serving as a diode can be used for this purpose, where the waveform of the signal is appropriately adjusted according to the known art.

Further, a drive element of a type different from the TFT and MIM elements, which can be applied to the driving of the so-called active matrix address LCD panel, may be used for this purpose.

While the preferred form of the invention has been described above, it will be apparent to those skilled in the art that various modifications are possible without departing from the spirit of the invention. Accordingly, the scope of the invention should be determined only by the following claims.

As described above, according to the present invention, even if the delay amount of the selection signal is changed by the resolution mode or the aspect change, the delay amount of the timing control signal is automatically changed in accordance with the change in the delay amount of the selection signal. Timing of writing data into LC cells can optimize the timing of writing pixel data into LC cells without using any timing controller even when the resolution mode changes, and can also simplify the configuration of driver circuits. Can be provided.

Claims (13)

(a) a plurality of first signal lines extending along the rows of the matrix and aligned along the columns of the matrix, (b) a plurality of second signal lines extending along the columns of the matrix and aligned along the rows of the matrix, (c) LC cells aligned with the array of matrices, (d) driving elements for driving the respective LC cells, and (e) Signal delay line causing temporary delay in timing control signal Including, The signal delay line extends along a row of the matrix and is not electrically connected to the driving element, The signal delay line includes a first stage to which a timing control signal is input and a second stage to output a timing control signal including the delay, Each of the plurality of first signal lines is used to supply a selection signal to the drive element located in a corresponding one of the rows of the matrix, Each of the plurality of second signal lines is used to supply a data signal to the driving element located in a corresponding one of the columns of the matrix, The timing control signal including the delay is used for timing control to supply the data signal to the driving element located in a corresponding column of the matrix via a plurality of second signal lines. LCD panel, characterized in that. The method of claim 1, And said signal delay line has substantially the same electrical characteristics as those of the plurality of first signal lines. The method of claim 1, And the signal delay line is located at an input side of the data signal to a plurality of second signal lines. The method of claim 1, The driving device is a TFT, Each of the plurality of first signal lines is electrically connected to a gate electrode of the TFT located in a corresponding one of the rows of the matrix, Each of the plurality of second signal lines is electrically connected to a source or drain electrode of the TFT located in a corresponding one of the columns of the matrix. LCD panel, characterized in that. The method of claim 1, The timing control signal comprising the delay at the second end of the signal delay line has a waveform having rising and falling edges of an obtuse angle approximately equal to that of each of the selection signals at corresponding rear ends of the plurality of second signal lines. LCD panel. (a) a plurality of first signal lines (a-1) extending along the rows of the matrix and aligned along the columns of the matrix, (a-2) a plurality of second signal lines extending along the columns of the matrix and aligned along the rows of the matrix, (a-3) LC cells aligned to the array of matrices, (a-4) a driving element for driving each LC cell, and (a-5) Signal delay line causing temporary delay in timing control signal Including; The signal delay line extends along a row of the matrix and is not electrically connected to the driving element, The signal delay line includes a first stage through which a timing control signal is input and a second stage through which a timing control signal including the delay is output. LCD panel, (b) a selection signal source for supplying a selection signal to the plurality of first signal lines, respectively; (c) data signal sources for supplying data signals to a plurality of second signal lines, respectively An LCD device comprising: Each selection signal is supplied from the selection signal source to the driving element located in a corresponding one of the rows of the matrix via a corresponding one of a plurality of first signal lines, Each data signal is supplied from the data signal source to a corresponding one of the columns of the matrix via a corresponding one of a plurality of second signal lines, The timing control signal including the delay is applied to the data signal source, thereby performing timing control to supply the data signal to the drive element located in the corresponding column of the matrix via a plurality of second signal lines. LCD device, characterized in that. The method of claim 6, And said signal delay line has substantially the same electrical characteristics as those of the plurality of first signal lines. The method of claim 6, And the signal delay line is located at an input side of the data signal to a plurality of second signal lines. The method of claim 6, The driving device is a TFT, Each of the plurality of first signal lines is electrically connected to a gate electrode of the TFT located in a corresponding one of the rows of the matrix, Each of the plurality of second signal lines is electrically connected to a source or drain electrode of the TFT located in a corresponding one of the columns of the matrix. LCD device, characterized in that. The method of claim 6, Each of the plurality of first signal lines is electrically connected to a gate electrode of the transistor located at a corresponding one of the rows of the matrix, and each of the plurality of second signal lines is a source or drain of the transistor located at a corresponding one of the columns of the matrix And an LCD electrically connected to the electrode. The method of claim 6, And the selection signal is supplied to a plurality of first signal lines, respectively, so as to be synchronized with a timing control signal not including the delay. The method of claim 6, And said timing control signal comprising said delay has a waveform having rising and falling edges of an obtuse angle approximately equal to that of each selection signal at corresponding rear ends of the plurality of second signal lines. The method of claim 6, And the signal delay line is located on a panel on the same side as that of the data signal source.