KR20000061599A - Device isolation layer having conductor therein and method for forming the same - Google Patents

Abstract

PURPOSE: A method for forming an isolation layer composed of a conductor is provided to stabilize an electrical characteristic by restraining a change of an electric potential in a channel. CONSTITUTION: In a method for forming an isolation layer, an oxide layer and a nitride layer are sequentially formed on a substrate. After defining a region for isolation on the nitride layer by forming an etching mask, a trench is obtained by etching the nitride layer, the oxide layer and the substrate in order, and then a first insulating layer(43) and a conductive layer(44) is formed. The first insulating layer(43) and the conductive layer(44) are left in a part of trench by CMP(Chemical Mechanical Polishing) or etch-back, and a second insulating layer(45) is formed inside the trench. After etching the nitride layer and the oxide layer, a gate insulating layer(46), a gate electrode(47) and a junction region(48) is formed.

Description

A device isolation film including a conductor therein and a method of forming the same {DEVICE ISOLATION LAYER HAVING CONDUCTOR THEREIN AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to an isolation region of a semiconductor device and a method of forming the same.

As semiconductor devices are highly integrated and their sizes become smaller, various means have been taken to integrate more devices more easily. In forming the device isolation region, a conventional LOCOS (LOCal Oxidation of Silicon) process is being replaced by a shallow trench isolation (STI) process. The STI process solves the problem of separation between devices, improving the problem of thinning the oxide film in a narrow region and the problem of thickening the oxide film at the edge of the device active region. However, as the size of the device becomes smaller, it is reported that not only separation between adjacent devices, but design considering the characteristic change of the device caused by the influence of the adjacent devices is required. That is, as the size of the device decreases, the width of the device isolation region also decreases, and the threshold voltage of the device changes according to the electric field and potential change in the device according to the voltage of the adjacent device.

Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.

FIG. 1A is a plan view of a dynamic random access memory (DRAM) cell showing a word line W and an active region A, and FIGS. 1B and 1C are cross-sectional views of transistors corresponding to lines AA and BB of FIG. 1A. to be. 1B and 1C, reference numeral 10 denotes a semiconductor substrate, 11 denotes an isolation layer, 14 denotes a gate oxide layer, 15 denotes a gate electrode, and 16 denotes a junction region.

A process of manufacturing the semiconductor device shown in FIG. 1B will be described in more detail with reference to FIGS. 2A through 2D.

First, as shown in FIG. 2A, the oxide film 11 and the nitride film 12 are sequentially formed on the semiconductor substrate 10, the device isolation region is defined, and the nitride film 12 and the oxide film 11 are sequentially etched to form a semiconductor. A portion of the substrate 10 is etched to form trenches.

Next, as shown in FIG. 2B, the device isolation insulating layer 13 is formed, and a chemical mechanical polishing (CMP) or etch-back process is performed to form the device only within the trench of the device isolation region. The isolation insulating film 13 is left.

Next, as shown in FIG. 2C, the nitride film 12 and the oxide film 11 are sequentially etched to complete the device isolation region.

2D is a cross-sectional view showing a state in which the gate insulating film 14, the gate electrode 15, and the junction region 16 are formed after the device isolation region is completed.

When the device isolation region is formed according to the related art as described above, since the device isolation insulating layer 13 is a non-conductor, the electric field is transmitted as it is and serves as an insulating film of a capacitor formed between the channel region and the adjacent junction region of the device. Therefore, there is a problem that the potential of the channel region under the gate electrode is changed by the voltage of the adjacent junction region.

For example, the channel-type N-type metal oxide transistor (NhFET) having a structure as shown in FIGS. 1B and 2D may be formed under the gate electrode 15 when the potential of the junction region 16 is higher than that of the semiconductor substrate 10. The potential of the channel region (element active region in which the junction region is not formed) rises above the potential of the semiconductor substrate 10. In other words, the potential of the channel region of the element, particularly the region adjacent to the element isolation region, rises above the potential of the semiconductor substrate due to the potential of the adjacent junction region.

Based on the formation of the depletion region in the device active region, the carrier 35 of the region adjacent to the isolation region is depleted by the potential change of the junction region 16, and the gate 35 of the depletion region necessary for the channel is formed. ) Will be reduced, and the threshold voltage of the device will decrease. This is due to the influence of the electric field generated by the potential difference between the device active region under the gate and the adjacent junction region.

Figure 3 shows the equipotential line distribution when the junction region adjacent to the channel is at a higher potential than the substrate as described above.

The present invention devised to solve the above problems, the device comprising a conductor therein, which can stabilize the electrical characteristics of the device by suppressing the potential of the channel is changed by the potential of the adjacent device or junction region It is an object to provide an isolation region and a method of forming the same.

1A is a plan view of a DRAM cell showing a word line and an active region,

1B and 1C are cross-sectional views of transistors corresponding to lines A-A and B-B of FIG. 1A;

2A to 2D are cross-sectional views of a semiconductor device manufacturing process according to the prior art;

3 is an equipotential line distribution diagram of a semiconductor device formed according to the prior art;

4A to 4D are cross-sectional views of a device isolation film forming process of a semiconductor device according to one embodiment of the present invention;

5A to 5E are cross-sectional views of a device isolation film forming process of a semiconductor device according to another embodiment of the present invention;

6 is an equipotential line distribution diagram of a semiconductor device formed in accordance with the present invention.

* Explanation of reference numerals for the main parts of the drawings

40, 50: semiconductor substrate 41, 51: oxide film

42, 52: nitride films 43, 45, 53, 55: device isolation insulating film

44, 54: conductive films 46, 56: gate insulating film

47, 57: gate electrode 48, 58: junction region

The present invention for achieving the above object is provided on a semiconductor substrate, and provides a semiconductor device including a device isolation film having a conductor therein to reduce the electric field of the surroundings. In particular, a trench formed in the semiconductor substrate of the device isolation region; A first insulating film formed on the trench sidewalls; A conductive film in contact with the first insulating film and filling a portion of the trench; And a device isolation film formed on the conductive film and formed of a second insulating film filling the trench.

In addition, the present invention for achieving the above object is a first step of forming an anti-oxidation film pattern for exposing the semiconductor substrate of the device isolation region; A second step of forming a trench in the semiconductor substrate by etching the semiconductor substrate exposed in the first step; A third step of sequentially forming a first insulating film and a conductive film on the entire structure of the second step; A fourth step of removing the first insulating film and the conductive film until the anti-oxidation film pattern is exposed to leave the first insulating film and the conductive film in a portion of the trench; A fifth step of forming a second insulating film in the trench on the conductive film; And a sixth step of removing the anti-oxidation film pattern.

In addition, the present invention for achieving the above object is a first step of forming an anti-oxidation film pattern for exposing the semiconductor substrate of the device isolation region; A second step of forming a trench in the semiconductor substrate by etching the semiconductor substrate exposed in the first step; A third step of forming a first insulating film on the entire structure in which the second step is completed, and anisotropically etching the first insulating film to leave the first insulating film on the sidewall of the trench; Forming a conductive film on the entire structure in which the third step is completed, and removing the conductive film until the anti-oxidation film pattern is exposed, thereby leaving the conductive film in a portion of the trench; A fifth step of forming a second insulating film in the trench on the conductive film; And a sixth step of removing the anti-oxidation film pattern.

A method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4A to 4D.

First, as shown in FIG. 4A, an oxide film 41 and a nitride film 42 are sequentially formed on the semiconductor substrate 40, and an etching mask (not shown) defining an isolation region on the nitride film 42 is formed. After the formation, the nitride film 42 and the oxide film 41 are sequentially etched, a portion of the semiconductor substrate 40 is etched to form a trench, the etch mask is removed, and the first device isolation insulating film 43 and the conductive film are removed. Form 44. In this case, the first device isolation insulating film 43 may be formed as shown in FIG. 4A by performing a deposition process or the like, or by contacting the semiconductor substrate by reaction with the semiconductor substrate 40 by performing an oxidation process or the like. It may be formed only in the part. In addition, the first device isolation insulating film 43 may also be formed of a nitride film. In this case, the first device isolation film made of a nitride film serves as an anti-oxidation film in an oxidation process to be performed later. In addition, the conductive film 44 may be formed of single crystal silicon, polycrystalline silicon, or amorphous silicon, and may have a stacked structure by combining single crystal silicon, polycrystalline silicon, or amorphous silicon. As described above, when the conductive film 44 is formed of silicon, the doping process may be performed during or immediately after the conductive film is formed, or may be doped into the silicon in the doping process for forming the active region.

Next, as shown in FIG. 4B, the conductive film 44 and the first device isolation insulating film 43 are chemically mechanically polished or etched back, and the conductive film 44 and the first device isolation insulating film 43 are formed on a portion of the trench. Let this remain.

Next, as shown in FIG. 4C, a second device isolation insulating film 45 is formed in the trench. In this case, the second device isolation insulating layer 45 may be formed by an oxidation process, or may be formed through a deposition process and then polished or etched back to remain only in the trench of the device isolation region.

Next, as shown in FIG. 4D, the nitride film 42 and the oxide film 41 are etched sequentially, and the gate insulating film 46, the gate electrode 47, and the junction region 48 are sequentially formed.

Hereinafter, a device isolation film forming method of a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS. 5A to 5E.

First, as shown in FIG. 5A, an oxide film 51 and a nitride film 52 are sequentially formed on the semiconductor substrate 50, the device isolation region is defined, and the nitride film 52 and the oxide film 51 are sequentially etched and then semiconductor A portion of the substrate 50 is etched to form a trench, and then a first device isolation insulating layer 53 is formed. In this case, the first device isolation insulating film 53 may be formed as shown in FIG. 5A by performing a deposition process or the like, or may be formed by a reaction process with the semiconductor substrate 50 by performing an oxidation process or the like. It can also be formed only in the part which contacts. In addition, the first device isolation insulating film 53 may also be formed of a nitride film. In this case, the first device isolation film made of a nitride film serves as an anti-oxidation film in an oxidation process to be performed later.

Next, as shown in FIG. 5B, the first device isolation insulating film 53 is anisotropically etched, leaving only the side surface of the trench, thereby forming a conductive film 54. The conductive film 54 is formed of single crystal silicon, polycrystalline silicon, or amorphous silicon as in the embodiment of the present invention described above, and may be formed by combining single crystal silicon, polycrystalline silicon, or amorphous silicon. As described above, when the conductive film 54 is formed of silicon, a doping process may be performed during or immediately after the conductive film is formed, or may be doped into the silicon in a doping process for forming an active region.

Next, as shown in Fig. 5C, the conductive film 54 is left only inside the trench of the element isolation region by polishing, etch back, or a combination thereof.

Next, as shown in FIG. 5D, a second device isolation insulating film 55 is formed in the trench. In this case, the second device isolation insulating layer 55 may be formed by an oxidation process, or may be formed through a deposition process and then remain in the trench of the device isolation region by performing a polishing process or an etch back process.

Next, as shown in FIG. 5E, the nitride film 52 and the oxide film 51 are sequentially etched, and the gate insulating film 56, the gate electrode 57, and the junction region 58 are sequentially formed.

In the conventional device isolation region structure in which the trench portion for device isolation is filled with only an insulating film, the electric field generated by the potential difference between the junction region and the semiconductor substrate is transferred to the channel region, whereas the device isolation region formed according to the present invention has a Since the conductor is filled, the electric field generated by the potential difference is canceled by the carrier movement in the conductor and then transferred to the channel region so that the potential increase or depletion region of the channel region adjacent to the element isolation region is significantly reduced.

FIG. 6 shows an equipotential line distribution when a junction region adjacent to a channel is at a higher potential than a substrate in a semiconductor device having an isolation region according to the present invention, and has a more stable potential than a semiconductor device having a isolation region according to the related art. Is showing. That is, by forming the device isolation region structure having a conductor therein, it is possible to suppress the device characteristics such as the threshold voltage of the device from being changed by the potential variation of the adjacent device or the junction region.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, it is possible to suppress the deterioration of device characteristics due to the interference between adjacent devices as the distance between the devices approaches. In addition, it is a technology that reduces the difficulty of the development of high value-added devices by easing the obstacles to increasing the integration of devices, facilitating the development of high-integration processes and high-integration devices, and reducing the difficulty of developing high value-added devices. It can be used as a base technology of semiconductor device manufacturing.

Claims (10)

A device isolation layer formed on the semiconductor substrate and having a conductor in the semiconductor substrate to reduce an electric field in the periphery Semiconductor device comprising a. The method of claim 1, Trenches formed in the semiconductor substrate in an isolation region; A first insulating film formed on the trench sidewalls; A conductive film in contact with the first insulating film and filling a portion of the trench; And A second insulating film formed on the conductive film to fill the trench A semiconductor device comprising a device isolation film consisting of. The method of claim 2, And a third insulating film formed on the bottom of the trench and in contact with the first insulating film and the conductive film. The method of claim 2 or 3, The conductive film is a semiconductor device, characterized in that the silicon film. In the device isolation film forming method of a semiconductor device, A first step of forming an anti-oxidation film pattern exposing the semiconductor substrate in the device isolation region; A second step of forming a trench in the semiconductor substrate by etching the semiconductor substrate exposed in the first step; A third step of sequentially forming a first insulating film and a conductive film on the entire structure of the second step; A fourth step of removing the first insulating film and the conductive film until the anti-oxidation film pattern is exposed to leave the first insulating film and the conductive film in a portion of the trench; A fifth step of forming a second insulating film in the trench on the conductive film; And A sixth step of removing the antioxidant layer pattern Device isolation film forming method of a semiconductor device comprising a. The method of claim 5, And forming the conductive film from silicon. The method according to claim 5 or 6, The first insulating film is formed of an oxide film or a nitride film, And forming the second insulating film as an oxide film. In the device isolation film forming method of a semiconductor device, A first step of forming an anti-oxidation film pattern exposing the semiconductor substrate in the device isolation region; A second step of forming a trench in the semiconductor substrate by etching the semiconductor substrate exposed in the first step; A third step of forming a first insulating film on the entire structure in which the second step is completed, and anisotropically etching the first insulating film to leave the first insulating film on the sidewall of the trench; Forming a conductive film on the entire structure in which the third step is completed, and removing the conductive film until the anti-oxidation film pattern is exposed, thereby leaving the conductive film in a portion of the trench; A fifth step of forming a second insulating film in the trench on the conductive film; And A sixth step of removing the antioxidant layer pattern Device isolation film forming method of a semiconductor device comprising a. The method of claim 8, And forming the conductive film from silicon. The method according to claim 8 or 9, The first insulating film is formed of an oxide film or a nitride film, And forming the second insulating film as an oxide film.