KR20000056840A - Speed detecting system and method thereof - Google Patents

Abstract

PURPOSE: A speed detecting system is provided to detect a revolution speed with a high accuracy by adding an algorithm capable of correcting a variation in data for detecting a speed. CONSTITUTION: A speed detecting system comprises an encoder pulse counter(11), a clock counter(14), an operation part(20) and a memory(21). The encoder pulse counter(11) counts the number of pulses generated by an encoder and stores an encoder pulse counted value on the basis of a predetermine signal. The clock counter(14) has a clock pulse counter(15), an interrupt buffer(16) storing a predetermined interrupt generation cycle, a first buffer(18) storing a clock count value of the clock pulse counter, and a second buffer(19) storing the clock count value of the first buffer. The clock counter(14) generates a speed detection interrupt to the operation part at a predetermined cycle. Upon generation of the speed detection interrupt, the operation part executes the interrupt for calculating a speed on the basis of the interrupt generation cycle, an encoder pulse count value stored in the encoder pulse counter and a value stored in the first buffer, and calculates the speed using a clock count value stored in the second buffer instead of the clock count value stored in the first buffer when a new encoder pulse is generated by the encoder during an execution time starting from the point of time of generation of the speed detection interrupt to a point of time of actual execution of the interruption.

Description

Speed detecting system and method

The present invention relates to a speed detection system and a method thereof, and more particularly, to a speed detection system having an encoder as a speed detection sensor and a method thereof.

In the high performance control system of a motor with an encoder such as a conventional servo motor driver or a vector control inverter, an ASIC (application-specific) is provided as a separate hardware chip outside the computation unit (CPU) for high precision rotational speed detection. An additional integrated circuit is dedicated to the speed detection function. The ASIC is a kind of chip designed for a special purpose and corresponds to a general purpose chip which has a certain function and is mass produced and widely used.

1 is a control block diagram of a speed detection system for detecting a rotational speed of a motor using a conventional ASIC. As shown, the conventional speed detection system includes an encoder 1 coaxially coupled to a rotation axis of a motor, an ASIC unit for receiving clock pulses from external clocks and pulses A and B generated from the encoder 1. (3) and an arithmetic unit (CPU) 5 for receiving data required for interrupt request and speed detection from the ASIC unit 3.

The encoder 1 is widely used to detect the rotational speed of a motor and generates a number of pulses A and B proportional to the rotational speed of the motor. In order to detect the rotational speed of the motor, a method of counting the number of pulses generated from the encoder or measuring the interval of pulse generation for a predetermined time is commonly used. The ASIC 3 receives an external clock signal and receives a predetermined time ( During t), the number of pulses A and B generated from the encoder 1 is counted, or the intervals between the pulses A and B are measured, and time t, which is data necessary for detecting the rotational speed of the motor, The number of pulses m generated from the encoder 3 during the time t, and the interrupt request for speed detection are sent to the calculation unit. Receiving an interrupt request for speed detection from the ASIC 3, the calculation unit 5 suspends the current work in progress and branches from the interrupt to the designated place to execute the speed detection interrupt.

However, the above speed detection method has the following problems.

First, in the method of detecting the speed by counting the number of pulses for a predetermined time, since the number of pulses input from the encoder is small when the speed of the motor is low, the accuracy of speed detection is low and reliability cannot be guaranteed. If the counting time is increased to overcome this, the speed detection interval becomes wider, and the control response of the motor is slowed, especially during high speed operation. The number of pulses generated per one revolution of the encoder is determined when the encoder is manufactured. The higher the number of pulses generated, the higher the price, and the increase thereof has a limitation due to the characteristics of the encoder.

In addition, in the pulse interval measuring method, the spacing of pulses generated during high speed rotation of the motor becomes very narrow, so that the interval of the counted clock pulses becomes relatively wide, whereby the pulse interval measured and counted is large in error and thus detected. The precision of the speed is lowered.

As one of the methods to solve this problem, U.S. Patent No. 4,584,528 shows a pulse count time value for speed detection by adding or subtracting a predetermined time from the speed detection interrupt generation period (for example, rising). A speed detection method is disclosed which increases the accuracy of speed detection by using the time value from the edge) to the time of the last pulse generation and by allowing the set interrupt generation period to be changed according to the rotational speed of the motor.

However, the above-described method is also implemented using the ASIC, so that the design, manufacture, and management of the ASIC chip is expensive. In addition, the additional mounting of the ASIC chip requires considerable space, which limits the miniaturization of hardware.

In addition, the pulse interval generated from the encoder is counted and measured by an external clock pulse input to the ASIC. Since this clock frequency is proportional to the precision of data, an additional high frequency external clock of about 1 MHz is required. However, as the clock frequency increases, the counter implementation cost increases because the number of bits of the counter to be counted increases simultaneously.

On the other hand, to solve the problems as described above by using the ASIC to implement the rotational speed detection system of the motor, using a one-chip controller sold in mass production without a separate ASIC mounted Has been proposed to process encoder pulses directly in arithmetic unit.

However, another pulse may be generated from the encoder during the transition time until the speed detection interrupt occurs at a constant cycle until the speed detection interrupt is actually executed by the calculation unit, thereby causing an error in data for speed calculation of the calculation unit. When the motor rotates at a high speed, the frequency of the pulses generated from the encoder is increased, thus increasing the possibility that pulses are generated from the encoder within the transition time. When the motor rotates at a low speed, the possibility of generating a pulse from the encoder within the transition time is low, but the frequency of the pulse is low, so that the error of the data for speed detection becomes larger.

However, such a case is not taken into consideration, i.e., it is impossible to obtain an accurate speed value by using it as it is without compensating for errors in the data, and thus there is a problem that control of the motor based thereon becomes unstable and inaccurate.

Accordingly, an object of the present invention is to provide a high-precision rotational speed by adding an algorithm that can correct a change in data for speed detection by inputting a pulse from an encoder between a speed detection interrupt occurrence and an actual execution time. It is to provide a speed detection system capable of detecting.

Another object of the present invention is to provide a speed detection system that can be implemented in a one-chip controller to reduce costs, simplify circuit design, and thereby volume, and easily change specifications as necessary.

1 is a control block diagram of a speed detection system for detecting a rotation speed using a conventional ASIC,

2 is a main part of a speed detection system implemented in a one-chip controller according to the present invention;

3 is a time block diagram of an encoder pulse generated from an encoder, an encoder pulse counter, and a clock pulse counter.

4 is a flow chart showing a speed calculation process of the calculation unit 20,

5 is a time block diagram of the encoder pulse counter 12 and the clock pulse counter 15 when a new encoder pulse is received within the transition time [Delta] t.

<Explanation of symbols for main parts of drawing>

1: Encoder 3: ASIC

5: calculation unit 10: edge detection circuit

12: encoder pulse counter 13: encoder pulse buffer

15: Clock pulse counter 16: Interrupt buffer

18: first buffer 19: second buffer

20: calculator 21: memory

According to the present invention, there is provided a speed detection system having an encoder, comprising: an encoder pulse counter for counting the number of encoder pulses generated from the encoder; An encoder pulse buffer that stores the coefficient value of the encoder pulse counter at the time when a speed detection interrupt occurs at a predetermined period; A clock pulse counter for counting clock pulses from a predetermined clock generator; A first buffer for storing a clock coefficient value of the clock pulse counter at the time when an encoder pulse generation signal is received from the encoder; A second buffer for receiving and storing the clock coefficient value stored in the first buffer at the time when the encoder pulse generation signal is received; When the speed detection interrupt occurs, the interrupt for calculating the speed is executed based on the interrupt generation period, the encoder pulse coefficient value stored in the encoder counter buffer, and the value stored in the first buffer, and the speed detection interrupt is executed. When a new encoder pulse is generated from the encoder within the transition time from the occurrence time to the execution time of the speed detection interrupt, the speed is stored using the clock coefficient value stored in the second buffer instead of the clock coefficient value stored in the first buffer. It is achieved by the speed detection system, characterized in that it comprises a calculation unit for calculating the.

Here, the clock pulse counter operates according to the operation clock generator, or further comprising a clock generator for the clock pulse counter to operate according to the clock generator, the encoder pulse generated from the encoder edge detection circuit It is effective to detect and count the rising edge through.

And, the calculating unit calculates the speed (V) by the following equation.

Here, T _c is the interrupt generation period, T _k-1 is the time from the last pulse input generated from the encoder to the k-th interrupt occurrence before the k-1 th interrupt occurs, and T _k is the k th interrupt generated The time from the last pulse input point previously generated from the encoder to the k + 1th interrupt occurrence point, m is the number of pulses generated from the encoder during the interrupt generation period, and k is a proportional constant. Hereinafter, the same symbols have the same meanings, and thus redundant descriptions are omitted.

In addition, the above object, according to the present invention, in the speed detection method by a speed detection system having an encoder, comprising the steps of: counting the number of encoder pulses generated from the encoder; Generating a speed detection interrupt at a predetermined period; Storing the encoder pulse coefficient value at the time of occurrence of the speed detection interrupt; Counting clock pulses from a predetermined clock generator; Storing the clock coefficient value at that time when an encoder pulse generation signal is received from the encoder; Receiving and storing the stored clock coefficient value when the encoder pulse generation signal is received; When the speed detection interrupt occurs, the interrupt for calculating the speed is executed based on the interrupt generation period, the encoder pulse coefficient value stored in the encoder counter buffer, and the value stored in the first buffer, and the speed detection interrupt is executed. When a new encoder pulse is generated from the encoder within the transition time from the occurrence time to the execution time of the speed detection interrupt, the speed is stored using the clock coefficient value stored in the second buffer instead of the clock coefficient value stored in the first buffer. It is also achieved by a speed detection method comprising the step of calculating a.

Here, the clock generator is any one of a clock generator for the calculator and a clock generator for the clock pulse counter.

In the counting of encoder pulses generated from the encoder, it is preferable to detect and count a rising edge through a predetermined edge detection circuit.

And, the step of calculating the speed (V) is by the following equation (1).

V = k * m / (T _c + T _k-1 -T _k )

In order to implement the speed detection system according to the present invention, a one-chip controller equipped with a timer and a counter unit as a peripheral device is required. Most recently used one-chip controllers satisfy these specifications. In this embodiment, a speed detection system was implemented using a one-chip controller of Hitachi's SH704X model.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is an essential part of a speed detection system implemented in a one-chip controller according to the present invention, and FIG. 3 is a time block diagram of an encoder pulse, an encoder pulse counter, and a clock pulse counter generated from an encoder.

The speed detection system according to the present invention includes an encoder pulse counter unit 11 for counting pulses A and B generated from an encoder and storing an encoder pulse coefficient value m based on a predetermined signal, and a predetermined clock pulse. A clock counter unit 14 for counting and storing the encoder pulse (A, B) input points based on the input signals of the encoder pulses (A, B) and generating a speed detection interrupt at a predetermined period in the calculation unit (CPU) 20, It includes a calculation unit 20 for calculating the rotational speed of the motor based on the predetermined data and a memory 21 for storing the predetermined data.

The encoder pulse counter unit 11 receives the pulses A and B generated from the encoder and detects an edge to detect an input time point, and a pulse input signal from the edge detection circuit 10. The encoder pulse counter 12 for counting the number of pulses A and B on the basis of the encoder, and the encoder pulse buffer 13 for storing the pulse coefficient value of the encoder pulse counter 12 at that moment in accordance with a predetermined command. Include.

The clock counter unit 14 further includes a clock pulse counter 15 that counts a predetermined clock pulse, an interrupt buffer 16 that stores a predetermined interrupt generation period, and a clock based on a signal from the edge detection circuit 10. A first buffer 18 for storing the clock coefficient value of the pulse counter 15, and a second buffer 19 for storing the clock coefficient value of the first buffer 18 based on a signal from the edge detection circuit 10; ).

With the above configuration, when the motor rotates, pulses A and B are generated in proportion to the rotational speed of the motor from an encoder (not shown) coaxially coupled to the rotational axis of the motor. Normally, the encoder generates pulses A and B having two different phases, one of which detects the absolute value of the speed, and detects the rotation direction through the phase difference of both pulses. Pulses A and B generated from the encoder are input to the edge detection circuit 10. The edge detection circuit 10 detects the rising edge of the pulse to detect the pulse input time point a. Of course, the edge detection circuit 10 may detect the falling edge of the pulse to detect the point of pulse input.

The edge detection circuit 10 transmits a signal informing the pulse input time a to the encoder pulse counter 12, the first buffer 18, and the second buffer 19. When a signal informing the pulse input time a is input, the encoder pulse counter 12 counts the number of pulse inputs. At this time, since the number of pulse inputs is proportional to the rotational speed of the motor, the number of pulse inputs increases when the motor rotates at high speed, and decreases when rotated at low speed.

Meanwhile, the encoder pulse counter 12 counts the internal clock embedded in the one chip controller in synchronization with the rotation of the motor. Hitachi's one-chip controller SH704X used in this example contains a system clock of 28,636 MHz. However, an appropriate external clock may be used depending on the motor speed range instead of the internal clock.

When the pulse input signal generated by the encoder is received from the edge detection circuit 10, the clock coefficient value counted by the clock pulse counter 15 at the pulse input time a is stored in the first buffer 18. When the next pulse input signal is received from the edge detection circuit 10, the clock coefficient value of the clock pulse counter 15 at the pulse input time point (b) is newly stored in the first buffer 18, and the first buffer 18 The clock value that was stored in is shifted to the second buffer 19 and stored in the second buffer 19. Similarly, when the next pulse input signal is received from the edge detection circuit 10, the clock coefficient value of the clock pulse counter 15 at the pulse input time point c is stored in the first buffer 18 again and stored in the first buffer. The previously stored clock value is repeated the process of shifting to the second buffer (19).

On the other hand, the interrupt buffer 16 stores a predetermined speed detection interrupt generation period T _c . Therefore, when the clock coefficient value of the clock pulse counter 15 reaches the speed detection interrupt generation period T _c stored in the interrupt buffer 16, the clock pulse counter 15 is reset and pulses of the encoder pulse counter 12 are applied to the encoder pulse buffer 13. A signal for storing the count value m is transmitted, and a speed detection interrupt is generated in the calculation unit 20.

The encoder pulse buffer 13 that receives the signal for commanding the count of the encoder pulse counter stores the pulse coefficient value m of the encoder pulse counter 12 at that time, and receives an operation unit that receives the speed detection interrupt ( 20) shows the time required from the rising edge of the encoder pulse to the rising edge (T _c -T _k + T _k-1 ) and the number of pulses counted during this time (m, Perform speed calculation based on The data necessary for this are the number of pulses (m) generated from the encoder during the speed detection interrupt generation period T _c stored in the encoder pulse buffer 13 and the speed stored in the first buffer 18. The clock coefficient value cpo of the input point e of the encoder pulse last generated before the detection interrupt occurrence time, and the speed detection interrupt generation period T _c stored in the interrupt buffer 16.

However, in order to execute the speed detection interrupt, that is, speed calculation according to the speed detection interrupt occurrence, the operation unit 20 interrupts the current work, branches to the point designated by the speed detection interrupt, and reads out the necessary data based on this. Speed detection interrupt must be executed. Therefore, a transition time [Delta] t of several μsec is required from the time of the speed detection interrupt occurrence to the execution time.

However, when a new encoder pulse is received within the transition time [Delta] t, the input point of the pulse is stored in the first buffer 18, and the value previously stored in the first buffer 18 is stored in the second buffer 19. In this case, the position of data to be read by the calculator 20 is different from the case where a new encoder pulse is not received within the transition time Δt.

Therefore, the calculation unit 20 must first determine whether or not the encoder pulse is input within the transition time Δt before performing the speed calculation.

4 is a flowchart illustrating a speed calculating process of the calculating unit 20.

The calculation unit 20 accesses the encoder pulse counter 12 to check whether the encoder pulse counter 12 is input within the transition time Δt (100). As discussed above, whether or not a new encoder pulse has been received can be seen from the fact that the encoder pulse counter 12 is reset at the same time as the speed detection interrupt is generated. That is, if the encoder pulse is not received within the transition time, the encoder pulse coefficient value is 0 since the reset state is maintained. However, when the encoder pulse is received, the encoder pulse counter 12 counts it and thus the encoder pulse coefficient value is 1 do.

Therefore, when the encoder pulse coefficient value is 0, the encoder pulse coefficient value m stored in the encoder pulse buffer 13 and the clock coefficient value cpo of the encoder pulse stored in the first buffer are read (101).

Subsequently, the calculation unit 20 calculates the T _k value by subtracting the clock coefficient value cpo from the interrupt generation period T _c (104), and then calculates the speed in the immediately preceding interrupt generation period stored in the memory 21. Read the T _k-1 value used in step 107.

Next, the calculating unit 20 calculates the speed V of the motor by using Equation 1 below (108).

Where k is a proportionality constant and varies depending on the dynamic, static and response characteristics of the motor.

The speed calculating end operation unit 20 stores the T _k value in the memory for speed calculation in the next interrupt cycle of the next step (109).

When a new encoder pulse is received within the transition time [Delta] t, that is, when the pulse coefficient value of the encoder pulse counter is 1, the speed calculation of the calculation unit is as follows.

5 is a time block diagram of the encoder pulse counter 12 and the clock pulse counter 15 when a new encoder pulse is received within the transition time [Delta] t. As shown, when a new encoder pulse is received within the transition time [Delta] t, the first buffer 18 stores the clock coefficient value cpo of the clock pulse counter 15 at the encoder input point e 'and stores it in advance. The clock coefficient value cp1 that has been set is shifted to the second buffer 19. However, if a new encoder pulse is not received within the transition time Δt to obtain T _k , the value stored in the first buffer 18 causes errors in the data and can calculate the exact speed of the motor. none. Therefore, in order to obtain T _k , the value stored in the second buffer 19 should be used. Accordingly, the calculation unit 20 reads out the encoder pulse coefficient value m stored in the encoder pulse buffer 13 and the clock coefficient value cp1 of the encoder pulse stored in the second buffer (103). Subsequently, the clock coefficient value cp1 stored in the second buffer 19 is subtracted from the interrupt generation period T _c to obtain a T _k value (105).

Again, the calculation unit 20 reads out the T _k-1 value stored in the memory 21 (107), and divides the encoder pulse coefficient value m by the required time T _c T _k + T _k-1 to a predetermined proportional constant. Multiply by to calculate the rotational speed (V) of the motor (108).

[Equation 1]

The speed calculating operation unit 20 stores the T _k value in the memory 21 for speed calculation in an interrupt cycle of a subsequent step (109). In the present embodiment, the T _k value is stored in a memory provided in the one chip controller, but may be stored using a buffer.

According to another embodiment of the present invention, the calculation unit 20 determines the encoder pulse counter 12 according to the encoder pulse coefficient value m in order to determine whether a new encoder pulse is input within the transition time Δt. Checking the values may be used in combination with comparing the values of the first buffer 18 and the second buffer 19.

When the encoder pulse coefficient value m stored in the encoder pulse buffer is 0 or 1, the same method as in the first embodiment is taken.

However, when defining the case where the encoder pulse coefficient value m is greater than or equal to 2, when the new encoder pulse is received within the transition time Δt, the pulse input signal is output from the edge detection circuit 10. The first buffer 18 received in the buffer 18 and receiving the pulse input signal stores the clock coefficient value cpo of the clock pulse counter 15 at the pulse input time e '. Therefore, the clock coefficient value cp1 stored in the first buffer becomes the coefficient value cpo until the input point of the first input encoder pulse after the clock pulse counter 15 is reset, and thus the clock coefficient value stored in the second buffer. It becomes smaller than (cp1).

However, if a new encoder pulse is not received within the transition time [Delta] t, the clock coefficient value at encoder pulse input time d is stored in the first buffer 18, and the encoder pulse input time c is stored in the second buffer 19. The clock coefficient value stored in the first buffer 18 is larger than the clock coefficient value stored in the second buffer 19 because the clock coefficient value in E is stored.

Accordingly, by comparing the value stored in the first buffer 18 with the value stored in the second buffer 19, it is possible to determine whether a new encoder pulse is received within the transition time Δt.

In the above two embodiments, the speed detection system is constructed on the assumption that only one encoder pulse is input within the transition time Δt from the time of occurrence of the speed detection interrupt to the execution time. In practice, encoders commonly used generate pulses of 600ppr (pulse per revolution), 1024ppr, and 2048ppr, and the transition time required for interrupt execution is about several microseconds. Therefore, even if the motor is rotated at high speed, two or more encoder pulses are input. Is hardly present at the normal level of technology at this time. However, if the rotational speed of the motor becomes larger and the number of encoder pulses can be inputted so that two or more encoder pulses can be input, the number of buffers storing the encoder pulse input time is increased by the expected number of inputs. The stored value can be used to correct errors in the data.

If the hardware configuration is complicated by increasing the number of buffers storing the encoder pulse input time, the speed detection system uses only one buffer to store the input time of the encoder pulse last input just before the speed interrupt execution. It can also be configured. In this case, the clock count value of the clock pulse counter stored in the buffer indicates the time required from the point of interrupt occurrence to the point of time of the last encoder pulse input. Therefore, the value obtained by adding the interrupt generation period (T _c ) to this value is obtained. The speed is calculated using the total encoder pulse value by reading the encoder pulse coefficient value stored in the encoder pulse buffer and the pulse coefficient value of the encoder pulse counter when the interrupt is executed. Here, the pulse count value of the encoder pulse counter at the time of interrupt execution represents the number of encoder pulses input within the transition time.

As described above, according to the present invention, it can be implemented in a one-chip controller to reduce costs, simplify circuit design, and reduce volume, and to easily change specifications as necessary, and from the time of occurrence of a speed detection interrupt When a pulse is input from the encoder between actual execution points and an error occurs in the data for speed detection, an algorithm is provided to compensate for this, thereby providing a speed detection system capable of detecting a high speed rotation speed.

Claims (10)

In a speed detection system with an encoder, An encoder pulse counter for counting the number of encoder pulses generated from the encoder; An encoder pulse buffer that stores the coefficient value of the encoder pulse counter at the time when a speed detection interrupt occurs at a predetermined period; A clock pulse counter for counting clock pulses from a predetermined clock pulse generator; A first buffer for storing a clock coefficient value of the clock pulse counter at the time when an encoder pulse generation signal is received from the encoder; A second buffer for receiving and storing the clock coefficient value stored in the first buffer at the time when the encoder pulse generation signal is received; When the speed detection interrupt occurs, the interrupt for calculating the speed is executed based on the interrupt generation period, the encoder pulse coefficient value stored in the encoder counter buffer, and the value stored in the first buffer, and the speed detection interrupt is executed. When a new encoder pulse is generated from the encoder within the transition time from the occurrence time to the execution time of the speed detection interrupt, the speed is stored using the clock coefficient value stored in the second buffer instead of the clock coefficient value stored in the first buffer. Speed detection system comprising a calculation unit for calculating the. The method of claim 1, The clock pulse counter operates in accordance with the operation clock generator. The method of claim 1, Speed detection system further comprises a clock generator for the operation of the clock pulse counter. The method according to any one of claims 1 to 3, The encoder pulse generated from the encoder detects and counts a rising edge through an edge detection circuit. The method according to any one of claims 1 to 3, The calculating unit calculates the speed (V) by the following equation. V = k * m / (T _c + T _k-1 -T _k ) Here, T _c is the interrupt generation period, T _k-1 is the time from the last pulse input generated from the encoder to the k-th interrupt occurrence before the k-1 th interrupt occurs, and T _k is the k th interrupt generated The time from the last pulse input point previously generated from the encoder to the k + 1th interrupt occurrence point, m is the number of pulses generated from the encoder during the interrupt generation period, and k is a proportional constant. In the speed detection method by the speed detection system provided with an encoder, Counting the number of encoder pulses generated from the encoder; Generating a speed detection interrupt at a predetermined period; Storing the encoder pulse coefficient value at the time of occurrence of the speed detection interrupt; Counting a predetermined clock pulse; Storing the clock coefficient value at that time when an encoder pulse generation signal is received from the encoder; Receiving and storing the stored clock coefficient value when the encoder pulse generation signal is received; When the speed detection interrupt occurs, the interrupt for calculating the speed is executed based on the interrupt generation period, the encoder pulse coefficient value stored in the encoder counter buffer, and the value stored in the first buffer, and the speed detection interrupt is executed. When a new encoder pulse is generated from the encoder within the transition time from the occurrence time to the execution time of the speed detection interrupt, the speed is stored using the clock coefficient value stored in the second buffer instead of the clock coefficient value stored in the first buffer. Speed detection method comprising the step of calculating the. The method of claim 6, And counting the clock pulses according to the operation unit clock. The method of claim 6, And counting the clock pulses according to a predetermined external clock. The method according to any one of claims 6 to 8, And counting the encoder pulses generated from the encoder comprises detecting and counting rising edges through a predetermined edge sensing circuit. The method according to any one of claims 6 to 8, Computing the speed (V) is based on the following equation. V = k * m / (T _c + T _k-1 -T _k ) Here, T _c is the interrupt generation period, T _k-1 is the time from the last pulse input generated from the encoder to the k-th interrupt occurrence before the k-1 th interrupt occurs, and T _k is the k th interrupt generated The time from the last pulse input point previously generated from the encoder to the k + 1th interrupt occurrence point, m is the number of pulses generated from the encoder during the interrupt generation period, and k is a proportional constant.