JPH04344466A - Detecting device for velocity of elevator - Google Patents

Abstract

PURPOSE:To enable more accurate velocity detection in a low velocity area to be conducted by using the newest latch data obtained when a CPU reads counted values in the low velocity area. CONSTITUTION:A pulse generator 10 generates pulses of two phases A, B different from each other by a predetermined angle as a motor 7 rotates, and trigger signals are generated by a pulse processing circuit 20 correspondingly to the rise and fall of each pulse. Values counted by a timer counter are sequentially latched by a latch means 22-26 in response to the trigger signals. In a low velocity area, the newest latch data obtained when a CPU 18 reads data, and data earlier than the latch data by one cycle are used to calculate the velocity of an elevator. Therefore, the velocity of the elevator in the low velocity area can be accurately detected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elevator speed detection device.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional elevator speed detection device. In FIG. 3, reference numeral 1 denotes an elevator control device, which includes a CPU 2, ROM 3, R
AM4, interface circuit 5 for external signal input/output
and a speed detection circuit 6. 7 is the motor, 8
9 is an elevator car, 9 is a counterweight, and 10 is a pulse generator that outputs two phase pulses, A and B, which are 90° out of phase with each other in accordance with the rotation of the motor 7. FIG. 4 is a detailed circuit diagram of the speed detection circuit 6. In FIG. 4, 10a, 1
0b is the A-phase and B-phase pulse, respectively, 11 is the A-phase pulse 1
Up/down counter that counts the rise of 0a,
12 is a direction discrimination circuit that detects the running direction of the elevator using the A-phase and B-phase pulses 10a and 10b, 13 is a timer counter for measuring time that counts an external clock, and 14 and 15 are the outputs of the timer counter 13. Latch circuits 16 and 17 are provided on the output side of the up/down counter 11 and latch circuit 15, respectively, and 18 is a data bus for the CPU 2.

Next, regarding the operation of FIGS. 3 and 4, FIGS. 5 and 6 will be described.
This will be explained with reference to. When the elevator car 8 starts running, that is, when the motor 7 starts moving, the pulse generator 10 outputs two-phase A and B pulses 10a and 10b, which are 90 degrees out of phase with each other, in accordance with the rotation of the elevator car 8. Each of these pulses is input to a speed detection circuit 6 within the elevator control device 1. The CPU 2 receives data from the speed detection circuit 6 and calculates the running speed of the elevator car 8 according to a predetermined program. The two-phase pulses 10a and 10b input to the speed detection circuit 6 are first input to the direction discrimination circuit 12, where the running direction of the elevator is detected, and a running direction signal (UP/DOWN) is sent to the output side. 12a is output. The up/down counter 11 for position detection is activated by this traveling direction signal and the rise of the A-phase pulse 10a. The timer counter 13 uses a predetermined clock CLK.
Therefore, it is constantly counted up, and this value is also latched in the latch circuit 14 every time the A-phase pulse 10a rises. As an example, FIG. 5 shows this operation in terms of timing. The A-phase and B-phase pulses are output from the pulse generator 10 in accordance with the rotation of the motor 7,
The amount of movement l of the elevator car 8 per pulse is defined. The up/down counter 11 receives pulse 10 of A phase.
The count is counted up or down at each point a, b, and c at the rising edge of a. If the count value at point a in the upward direction is m, the count values at points b and c will be m+1 and m+2, respectively. It is assumed that the timer counter 13 is also latched by the latch circuit 14 at the same timing points a, b, and c, and the count values at that time are x, y, and z, respectively.

[0004] Here, the speed calculation process of the CPU 2 will be described. The CPU 2 normally executes processing in a predetermined calculation cycle. Therefore, if the cycle for reading the count value of the up/down counter 11 and the timer counter 13 mentioned above is indicated by d-e in FIG. 6, this period is approximately constant. As shown in FIG. 5, if the CPU 2 reads data at points d and e, the count value of the up/down counter 11 at point d is m, and the count value at point e is m+2. Become. Therefore, the amount of movement X of the elevator car 8 during this period is expressed by the following equation.

[0005]

[Math 1]

[0006] Also, the elapsed time T for this movement amount X is:

[0007]

[Math 2]

It is expressed as: However, t is clock CL
This is the period of K. Therefore, the speed of the elevator car 8 at this time, that is, the speed V of the elevator is

[0009]

[Math 3]

[0010] If the speed increases more than this, the A-phase pulse 10a between d and e in FIG. 5 increases, but the speed can be calculated by the same process. The count value of the timer counter 13 is determined by reading the data of the up/down counter 11 (RD
This is to hold the count value of the timer counter 13 at the time of reading. Therefore, for example, when reading is performed at point d in FIG. 5, the count value x of the timer counter 13 can be reliably read with respect to the count value m of the up/down counter 11.

[0011]

[Problems to be Solved by the Invention] Since the conventional elevator speed detection device is configured as described above, when the speed of the elevator becomes low, the A-phase pulse within a predetermined CPU data read cycle section is detected. The number of rising points gradually decreases, and eventually a state occurs where there are no changing points. In such a low speed region, for example, as shown in FIG.
If the rising edge of the A-phase pulse occurs immediately after the CPU data is read, the detection will be delayed by the data read cycle time. Moreover, as shown in FIG. 6(b),
If the A-phase pulse does not rise even once, there is no change at all during the data read cycle, and there is a problem that accurate speed changes cannot be detected during this period. Ta.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an elevator speed detection device that can more accurately detect speed in a low speed region.

[0013]

[Means for Solving the Problems] An elevator speed detection device according to the present invention includes a pulse generator that generates two-phase pulses shifted by a predetermined angle according to the rotation of a motor;
a pulse processing circuit that generates a trigger signal in response to the rising and falling edges of pulses of a phase; a timer counter for time measurement; a latch means that sequentially latches the output of the timer counter using the trigger signal; The latch output is used to detect speed in the low speed region.

[0014]

[Operation] In this invention, among the count values of the timer counter sequentially latched at the rising edge and falling edge of each of the two phase A and B pulses, between each rising edge of the A phase pulse, and between each rising edge of the B phase pulse, The speed is detected by a change in the count value for each same phase between each falling edge of the A-phase pulse and between each falling edge of the B-phase pulse. In this case, since the latest latch data at the time when the CPU reads the count value is used, low speed detection can be performed more accurately.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 10, 11, 13-18 are similar to the conventional device. 20 is a pulse processing circuit provided on the output side of the pulse generator 10 and includes a direction discrimination function; 21 is connected to the pulse processing circuit 20, and is connected to the pulse processing circuit 20 to detect the rising edge of each pulse of A phase and B phase and each pulse of A phase and B phase. A gate circuit, for example, an OR circuit, into which a trigger signal corresponding to the falling edge of the pulse is input, 22
~27 are connected in cascade to the output side of the timer counter 13,
A latch circuit that sequentially latches the output of the timer counter 13 by the output (trigger signal) of the OR circuit 21; 28 is a gate circuit connected between the latch circuit 22 and the data bus 18 of the CPU 2 (FIG. 3); 29 is a latch circuit 29 and CPU
This is a gate circuit connected between two data buses 18.

Next, the operation will be explained. The A-phase and B-phase pulses 10a and 10b, which are output from the pulse generator 10 and are out of phase by 90 degrees, are input to a pulse processing circuit 20. Signal 20a output from this pulse processing circuit 20
is the same as the A-phase pulse 10a, and 20b is,
UP/DOW from each pulse 10a, 10b of A phase and B phase
This is a traveling direction signal that discriminates the direction of N. In the following circuit, as in the conventional example, the up/down counter 11 is operated by the signals 20a and 20b, and the output 13a of the timer counter 13 is With the rise of the pulse 10a, that is, the rise of the signal 20a, the latch circuit 14
latched to. Here, the signals 20c, 20d, 20e, and 20f output from the pulse processing circuit 20 are generated and output by sampling the rising and falling edges of the A-phase and B-phase pulses 10a and 10b, respectively, using the clock CLK input. It's a signal. Each of these signals is input to the OR circuit 21. Therefore, the output signal 21a of the OR circuit 21 is
As shown in FIG. 2, each pulse 10a, 10b of A phase and B phase
It is output at the rising and falling points of . In other words, output signal 2
1a serves as a trigger signal for the latch circuits 22 to 26, respectively. The output 13a of the timer counter 13 is first sent to the latch circuit 2.
2 and generated at the rising and falling edges of the A-phase and B-phase pulses 10a and 10b, the latch circuits sequentially proceed in the order of latch circuits 23→24→25→26. Here, the output 22a of the latch circuit 22 and the latch circuit 26
The output 26a is always latched data generated by a trigger signal of the same phase. That is, the rising edge of the A-phase pulse 10a -
The current latched data is latched at each timing: falling, rising and falling of the B-phase pulse 10b, rising and falling of the A-phase pulse 10a, and rising and falling of the B-phase pulse 10b. is 22a, the previous latch data of the same phase is 26a.

FIG. 2 shows this situation in terms of timing. Here, the speed detection process will be explained with reference to FIG. If the amount of movement of elevator car 8 (Fig. 3) per pulse of A phase and B phase is l, pulse 1 of A phase
Between each rising edge of 0a, between each rising edge of B-phase pulse 10b,
Between each falling edge of the A-phase pulse 10a, the B-phase pulse 10b
Since the phases between each falling edge are the same, it can be captured as a relatively stable waveform. (The influence of variations in characteristics of input circuit elements, etc. is reduced). Therefore, the amount of movement in one cycle is l
Calculate the speed as . In Figure 2, CPU2 (Figure 3
) reads data in cycles d-e,
With only the conventional configuration, since there is no rising point of the A-phase pulse 10a, the count value of the up/down counter 11 and the count value of the timer counter 13 read at points d and e are the same and do not change. It turns out. Therefore, when the speed of the elevator is decreasing, the method of calculating the speed using the circuit in this embodiment is effective. That is, if the CPU 2 goes to read data at point e, the count value y of the timer counter 13 at that point is the latest one latched at the falling edge of the B-phase pulse 10b, and the latch circuit 22 becomes the output 22a. At this time, the value of the output 26a of the latch circuit 26 becomes the latch data x at the falling edge of the B-phase pulse 10b one cycle before. The count value of timer counter 13 is from x to y
The amount of movement of the elevator car 8 while proceeding to
Therefore, if the period of the clock CLK is t, the speed of the elevator car 8 at this point, that is, the speed of the elevator V is

[0018]

[Math 4]

It is determined by: In this way, the moving distance l is always constant, and the CPU 2 calculates the time using the latest counter latch data of the rising and falling edges of the A-phase and B-phase pulses at the time of counter reading. , more accurate speed can be detected. Furthermore, C
When PU2 reads data, as in the conventional example, when reading the latest latch data (when outputting RDOL), 1
Latch the data before the cycle.

[0020]

As described above, according to the present invention, there is provided a pulse generator that generates two-phase pulses shifted by a predetermined angle according to the rotation of a motor, and a It is equipped with a pulse processing circuit that generates a corresponding trigger signal, a timer counter for time measurement, and a latch means that sequentially latches the output of the timer counter using the trigger signal, and uses latch outputs for each same phase. Since the speed is detected in the low speed region, it is possible to detect the elevator speed with higher accuracy in the low speed region.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing waveform diagram for explaining the operation of FIG. 1;

FIG. 3 is a configuration diagram showing a conventional elevator speed detection device.

FIG. 4 is a configuration diagram showing a conventional speed detection circuit.

5 is a timing waveform diagram for explaining the operation of FIGS. 3 and 4; FIG.

6 is a timing waveform diagram for explaining the operation of FIGS. 3 and 4. FIG.

[Explanation of symbols]

10 Pulse generator 13 Timer counter 20 Pulse processing circuit 22-26 Latch circuit

Claims (1)

[Claims] 1. A pulse generator that generates two-phase pulses shifted by a predetermined angle according to the rotation of a motor, and a pulse processing circuit that generates a trigger signal in response to the rise and fall of the two-phase pulses. and a timer counter for time measurement, and a latch means for sequentially latching the output of the timer counter using the trigger signal, and detecting speed in a low speed region using the latch output for each same phase. Elevator speed detection device.