KR20000046075A - Method for forming copper metal interconnect of semiconductor device - Google Patents
Method for forming copper metal interconnect of semiconductor device Download PDFInfo
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- KR20000046075A KR20000046075A KR1019980062751A KR19980062751A KR20000046075A KR 20000046075 A KR20000046075 A KR 20000046075A KR 1019980062751 A KR1019980062751 A KR 1019980062751A KR 19980062751 A KR19980062751 A KR 19980062751A KR 20000046075 A KR20000046075 A KR 20000046075A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000010949 copper Substances 0.000 title claims abstract description 53
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000010410 layer Substances 0.000 claims abstract description 37
- 238000004140 cleaning Methods 0.000 claims abstract description 36
- 239000000126 substance Substances 0.000 claims abstract description 25
- 238000007517 polishing process Methods 0.000 claims abstract description 17
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000002245 particle Substances 0.000 claims abstract description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011259 mixed solution Substances 0.000 claims abstract description 7
- 238000001035 drying Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000000243 solution Substances 0.000 claims description 2
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 3
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 abstract 2
- 239000012964 benzotriazole Substances 0.000 abstract 1
- 239000008367 deionised water Substances 0.000 abstract 1
- 229910021641 deionized water Inorganic materials 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 3
- 238000005201 scrubbing Methods 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 반도체 소자의 구리 금속 배선 형성 방법에 관한 것으로, 특히 다마신(damascene) 공정이 도입된 구리 금속 배선 형성시 화학 기계적 폴리싱(CMP) 공정 후에 실시하는 세정(cleaning) 공정을 개선하여, 구리층에 손상을 주지 않으면서 파티클(particle)과 금속 이온을 효과적으로 제거할 수 있는 반도체 소자의 구리 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper metal wiring of a semiconductor device, and in particular, to improve the cleaning process performed after a chemical mechanical polishing (CMP) process when forming a copper metal wiring in which a damascene process is introduced. The present invention relates to a method for forming a copper metal wiring of a semiconductor device capable of effectively removing particles and metal ions without damaging the layer.
최근 반도체 소자가 고집적화 및 축소화되고 고속 동작을 요구함에 따라 배선 재료로 구리(Cu)가 널리 사용되고, 구리의 사용으로 다마신(damascene) 공정이 도입되어 화학 기계적 폴리싱(CMP) 공정이 요구되고 있으며, 화학 기계적 폴리싱 공정 후에 잔존하는 파티클(particle)과 금속 이온을 제거하기 위한 세정(cleaning) 공정이 실시되고 있다.Recently, as semiconductor devices are highly integrated and reduced in size, and high speed operation is required, copper (Cu) is widely used as a wiring material, and a damascene process is introduced by using copper, thereby requiring a chemical mechanical polishing (CMP) process. After the chemical mechanical polishing process, a cleaning process for removing particles and metal ions remaining is performed.
일반적으로, 화학 기계적 폴리싱 공정 후에 실시되는 구리층의 세정 공정은 산화막이나 텅스텐층의 평탄화를 위한 화학 기계적 폴리싱 공정 후에 실시하는 기존의 세정 공정을 그대로 적용하고 있는 실정이다. 산화막이나 텅스텐층의 화학 기계적 폴리싱 공정 후에 실시하는 세정 공정은 파티클(particle) 제거용으로 암모니아 혹은 SC-1을 사용하고, 금속 이온 제거용으로 희석된 HF 혹은 BOE (100:1∼200:1) 등의 강산을 사용하고 있다. 이러한 화학제를 사용하여 구리층을 세정할 경우, 암모니아 혹은 SC-1은 구리층을 손상(attack)시켜 구리층의 표면을 매우 거칠게 만들고, 희석된 HF 혹은 BOE는 구리층이 표면을 산화시켜 저항을 증가시키는 문제점이 있다.In general, the copper layer cleaning process performed after the chemical mechanical polishing process is a situation in which an existing cleaning process performed after the chemical mechanical polishing process for planarization of the oxide film or tungsten layer is applied as it is. The cleaning process performed after the chemical mechanical polishing process of the oxide film or tungsten layer uses HF or BOE (100: 1 to 200: 1) diluted with ammonia or SC-1 for removing particles and for removing metal ions. Strong acid such as is used. When using these chemicals to clean the copper layer, ammonia or SC-1 damages the copper layer, making the surface of the copper layer very rough, and diluted HF or BOE resists the copper layer by oxidizing the surface. There is a problem to increase.
따라서, 본 발명은 다마신 공정이 도입된 구리 금속 배선 형성시 화학 기계적 폴리싱 공정 후에 실시하는 세정 공정을 개선하여, 구리층에 손상을 주지 않으면서 파티클과 금속 이온을 효과적으로 제거하므로써, 구리 금속 배선의 공정 안정성과 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention improves the cleaning process performed after the chemical mechanical polishing process when forming a copper metal wiring in which the damascene process is introduced, and effectively removes particles and metal ions without damaging the copper layer, thereby reducing the copper metal wiring. It is an object of the present invention to provide a method for forming a copper metal wiring of a semiconductor device capable of improving process stability and device reliability.
이러한 목적을 달성하기 위한 본 발명의 구리 금속 배선 형성 방법은 반도체 기판 상에 형성된 층간 절연막의 다마신 패턴을 구리층으로 매립한 후, 화학 기계적 폴리싱 공정으로 상기 구리층이 연마된 웨이퍼가 제공되는 단계; 상기 웨이퍼에 희석된 HF와 BTA 혼합 용액을 흘려 1차 세정하는 단계; 상기 웨이퍼에 희석된 초산을 흘려 2차 세정하는 단계; 및 상기 웨이퍼를 건조시키는 단계를 포함하여 이루어지는 것을 특징으로 하며, 상기 희석된 HF와 BTA 혼합 용액을 사용하는 1차 세정 전후와, 상기 희석된 초산을 사용하는 2차 세정 전후에 헹굼 과정이 추가된다.In order to achieve the above object, a method of forming a copper metal wiring according to the present invention includes filling a damascene pattern of an interlayer insulating film formed on a semiconductor substrate with a copper layer, and then providing a wafer with the copper layer polished by a chemical mechanical polishing process. ; Primary cleaning by flowing a diluted HF and BTA solution onto the wafer; Secondary cleaning by flowing diluted acetic acid on the wafer; And drying the wafer, wherein a rinsing process is added before and after the first cleaning using the diluted HF and BTA mixed solution and before and after the second cleaning using the diluted acetic acid. .
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2는 염기성 또는 강산성에서의 Al2O3와 SiO2의 제타 포텐셜을 나타낸 그래프.Figure 2 is a graph showing the zeta potential of the Al 2 O 3 and SiO 2 in a basic or acidic.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11: 반도체 기판 12: 층간 절연막11: semiconductor substrate 12: interlayer insulating film
13: 다마신 패턴 14: 구리층13: damascene pattern 14: copper layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method of forming copper metal wires in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 층간 절연막(12)에 형성된 다마신 패턴(13)에 구리층(14)을 매립시킨 후, 화학 기계적 폴리싱 공정으로 구리층(14)을 연마하여 다마신 패턴(13) 내에 구리층(14)이 형성된 반도체 기판(11)이 제공된다. 화학 기계적 폴리싱 공정 후에 웨이퍼의 구리층(14)과 층간 절연막(12)의 표면에는 많은 파티클(particle)과 금속 이온이 존재하게 된다.Referring to FIG. 1A, after the copper layer 14 is embedded in the damascene pattern 13 formed on the interlayer insulating layer 12, the copper layer 14 is polished by a chemical mechanical polishing process to form the damascene pattern 13. There is provided a semiconductor substrate 11 on which a copper layer 14 is formed. After the chemical mechanical polishing process, many particles and metal ions are present on the surface of the copper layer 14 and the interlayer insulating layer 12 of the wafer.
상기에서, 층간 절연막(12)은 주로 산화물 예를 들어, USG, SOG, O3-TEOS, Si-rich Oxide, HDP-USG 등으로 단층 또는 다층 구조로 형성된다. 다마신 패턴(13)은 싱글-다마신(single- damascene) 공정이나 듀얼-다마신(dual-damascene) 공정으로 형성된다. 구리층(14)은 장벽 금속층(barrier metal layer)으로 타이타늄(Ti), 타이타늄나이트라이드(TiN), 텅스텐나이트라이드(WN), 탄탈륨나이트라이드(TaN), 타이타늄/타이타늄나이트라이드(Ti/TiN), 타이타늄/텅스텐나이트라이트(Ti/WN), 타이타늄/탄탈륨나이트라이드(Ti/TaN) 등을 사용하며, 이러한 장벽 금속층은 물리적 기상 증착(PVD)법이나 화학적 기상 증착(CVD)법을 적용하여 형성된다.In the above, the interlayer insulating film 12 is mainly formed of a single layer or a multilayer structure of an oxide, for example, USG, SOG, O 3 -TEOS, Si-rich Oxide, HDP-USG, or the like. The damascene pattern 13 is formed by a single-damascene process or a dual-damascene process. The copper layer 14 is a barrier metal layer, which is titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium / titanium nitride (Ti / TiN) , Titanium / tungsten nitride (Ti / WN), titanium / tantalum nitride (Ti / TaN), and the like, and the barrier metal layer is formed by applying physical vapor deposition (PVD) or chemical vapor deposition (CVD). do.
도 1b를 참조하면, 구리층(14)의 화학 기계적 폴리싱 공정 후에 잔존하는 파티클(particle)과 금속 이온을 제거하기 위하여, 브러시 스크러빙(brush scrubbing)에서 세정(cleaning) 공정이 실시하는데, 제 1 브러시 스테이션(brush station)에서, 화학제 사용에 따른 급속한 표면 손상(attack)을 방지하기 위해 이온이 제거된 순수(DIW)를 흘려 1차 헹굼(rinse) 과정을 거치고, 희석된(diluted) HF와 BTA 혼합 용액을 흘려 세정(cleaning) 과정을 거치며, HF와 BTA(benezotriazloe)를 제거하기 위해 다시 이온이 제거된 순수(DIW)를 흘려 2차 헹굼 과정을 거쳐 화학 기계적 폴리싱 공정 후에 잔존하는 파티클과 금속 이온을 제거한다.Referring to FIG. 1B, in order to remove particles and metal ions remaining after the chemical mechanical polishing process of the copper layer 14, a cleaning process is performed in brush scrubbing. At the brush station, a primary rinse is run through the deionized pure water (DIW) to prevent rapid surface damage from chemical use, and diluted HF and BTA Particles and metal ions that remain after the chemical mechanical polishing process are run through a mixed solution, followed by a cleaning process, and a second rinsing process with a deionized pure water (DIW) to remove HF and BTA (benezotriazloe). Remove it.
상기에서, 1차 헹굼 과정은 HF와 BTA의 화학제(chemical)에 의한 구리층(14)의 표면 손상을 방지하기 위한 과정으로 이온이 제거된 순수(DIW)를 900 ∼ 1000ml/min의 유량비(flow rate)로 10 ∼ 15초 동안 흘려준다. 세정 과정은 250:1 ∼ 300:1로 희석된 HF를 600 ∼ 800ml/min의 유량비로 30 ∼ 40초 동안 흘려주며, HF에 의한 구리층(14)의 표면 산화를 방지하기 위하여 0.1 ∼ 0.2wt%의 BTA를 300 ∼ 400ml/min의 유량비로 희석된 HF와 함께 흘려준다. 2차 헹굼 과정은 이후의 공정에서 HF와 BTA의 영향을 없애주기 위하여 약 1500ml/min의 유량비로 약 10초 동안 흘려준다.In the above, the first rinsing process is to prevent the surface damage of the copper layer 14 by the chemicals of HF and BTA to the flow rate ratio of 900 ~ 1000ml / min flow rate for 10-15 seconds. The cleaning process flows HF diluted from 250: 1 to 300: 1 at a flow rate of 600 to 800 ml / min for 30 to 40 seconds, and 0.1 to 0.2 wt% to prevent surface oxidation of the copper layer 14 by HF. % BTA is flowed with dilute HF at a flow rate of 300-400 ml / min. The second rinsing process is flowed for about 10 seconds at a flow rate of about 1500 ml / min to eliminate the effects of HF and BTA in subsequent processes.
한편, 구리층(14)의 화학 기계적 폴리싱 공정은 연마제로 Al2O3를 주로 사용하는데, 도 2의 그래프에서 알 수 있듯이, Al2O3는 층간 절연막(12)을 이루는 SiO2와 제타 포텐셜(Zeta Potential)이 염기성 또는 강산성에서 동일한 극성을 나타내기 때문에 Al2O3를 SiO2표면에서 효과적으로 제거하기 위해서는 염기성 또는 산성의 화학제를 사용하여야 한다. 암모니아와 같은 염기성 화학제는 구리층(14) 표면을 손상시키는 성질이 있어 본 발명의 세정 과정에 부적합하며, 희석된 산성이 적합하여 본 발명에서는 희석된 HF를 사용한다. 또한, 본 발명에서는 아무리 희석된 HF라 할지라도 구리층(14) 표면을 산화시킬 수 있기 때문에 산에 대한 구리의 부식을 억제하는 성질을 갖는 화학제인 BTA를 희석된 HF와 함께 사용한다.Meanwhile, the chemical mechanical polishing process of the copper layer 14 mainly uses Al 2 O 3 as an abrasive. As can be seen from the graph of FIG. 2, Al 2 O 3 is a SiO 2 and zeta potential forming the interlayer insulating film 12. Since (Zeta Potential) has the same polarity in basic or strong acidity, basic or acidic chemicals should be used to effectively remove Al 2 O 3 from SiO 2 surface. Basic chemicals, such as ammonia, have the property of damaging the surface of the copper layer 14, which makes them unsuitable for the cleaning process of the present invention. Dilute acidity is suitable for use with diluted HF in the present invention. In the present invention, since even the diluted HF can oxidize the surface of the copper layer 14, BTA, which is a chemical agent having a property of suppressing corrosion of copper to acids, is used together with the diluted HF.
도 1c를 참조하면, 제 2 브러시 스테이션에서, 제 1 브러시 스테이션으로부터 넘어온 웨이퍼에 존재할 지 모르는 희석된 HF와 BTA를 제거하기 위해 이온이 제거된 순수(DIW)를 흘려 1차 헹굼(rinse) 과정을 거치고, 희석된 초산(acetic acid; CH3COOH)을 흘려 세정(cleaning) 과정을 거치며, 초산을 제거하기 위해 다시 이온이 제거된 순수(DIW)를 흘려 2차 헹굼 과정을 거쳐 층간 절연막(12) 위에 잔존하는 금속 이온을 제거한다.Referring to FIG. 1C, in a second brush station, a first rinse process is performed by flowing deionized pure water (DIW) to remove diluted HF and BTA that may be present on the wafer from the first brush station. After passing through a dilute acetic acid (CH 3 COOH), a cleaning process is performed, and pure water (DIW) deionized again is removed to remove acetic acid, followed by a second rinsing process to remove the interlayer insulating film 12. Remove metal ions remaining on the stomach.
상기에서, 1차 헹굼 과정은 제 1 브러시 스테이션으로부터 넘어온 웨이퍼에 존재할 지 모르는 HF와 BTA의 영향을 완전히 없애주기 위한 과정으로 이온이 제거된 순수(DIW)를 약 1500ml/min의 유량비로 약 10초 동안 흘려준다. 세정 과정은 희석된 초산을 이용하는데, 초산은 유기산으로서 50wt% 농도에서는 구리층(14)을 부식시키지 않으며 층간 절연막(12)을 용이하게 제거할 수 있어, 20:1 ∼ 30:1 정도로 희석된 초산을 400 ∼ 500ml/min의 유량비로 50 ∼ 60초 동안 흘려준다. 2차 헹굼 과정은 초산을 없애주기 위하여 900 ∼ 1000ml/min의 유량비로 20 ∼ 30초 동안 흘려준다.In the above, the first rinsing process is a process for completely eliminating the effects of HF and BTA that may be present on the wafer from the first brush station to remove the deionized pure water (DIW) at a flow rate of about 1500 ml / min for about 10 seconds. Shed for a while. The cleaning process uses diluted acetic acid. Acetic acid is an organic acid, which does not corrode the copper layer 14 at a concentration of 50 wt%, and can easily remove the interlayer insulating film 12, and thus diluted acetic acid of 20: 1 to 30: 1. Is flowed for 50 to 60 seconds at a flow rate of 400 to 500 ml / min. The second rinsing process is flowed for 20 to 30 seconds at a flow rate of 900 to 1000ml / min to remove acetic acid.
이후, 건조 장비(spin rinse dry; SRD)에서 자외선(UV) 및 이온이 제거된 순수(DIW)를 사용하여 웨이퍼를 건조시켜 세정 공정을 완료한다.The wafer is then dried using ultraviolet (UV) and deionized pure water (DIW) in a spin rinse dry (SRD) to complete the cleaning process.
상기한 본 발명의 기술적 원리는 제 1 브러시 스테이션에서 희석된 HF와 희석된 BTA 혼합 용액으로 구리층 및 층간 절연막 표면에 잔존하는 파티클과 금속 이온을 1차 제거하고, 제 2 브러시 스테이션에서 희석된 초산(CH3COOH)으로 층간 절연막 표면에 잔존하는 금속 이온을 제거하는 것이다.The technical principle of the present invention described above is to first remove particles and metal ions remaining on the surface of the copper layer and the interlayer insulating film with HF and dilute BTA mixed solution diluted in the first brush station, and dilute acetic acid in the second brush station. (CH 3 COOH) removes metal ions remaining on the interlayer insulating film surface.
한편, 본 발명의 실시예는 세정 공정을 브러시 스크러빙(brush scrubbing)에 적용하여 설명하였지만, 기존의 웨트 딥핑(wet dipping)이나 스프레이 클리닝(spray cleaning) 등에도 응용 가능하다.On the other hand, the embodiment of the present invention has been described by applying the cleaning process to brush scrubbing (brush scrubbing), it can be applied to the existing wet dipping (spray cleaning) and the like.
상술한 바와 같이, 본 발명은 다마신 공정이 도입된 구리 금속 배선 형성시 화학 기계적 폴리싱 공정 후에 실시하는 세정 공정을 희석된 HF와 BTA 혼합 용액으로 1차 세정하고, 희석된 초산(CH3COOH)으로 2차 세정하므로써, 화학 기계적 폴리싱 공정 후에 잔존하는 파티클 및 금속 이온을 구리층에 손상을 주지 않으면서 효과적으로 제거할 수 있어, 구리 금속 배선의 공정 안정성과 소자의 신뢰성을 향상시킬 수 있다.As described above, in the present invention, the cleaning process performed after the chemical mechanical polishing process when forming a copper metal wire to which the damascene process is introduced is first washed with a diluted HF and BTA mixed solution, and diluted acetic acid (CH 3 COOH) By second cleaning, the particles and metal ions remaining after the chemical mechanical polishing process can be effectively removed without damaging the copper layer, thereby improving the process stability of the copper metal wiring and the reliability of the device.
Claims (9)
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| KR100467495B1 (en) * | 2002-06-18 | 2005-01-24 | 동부전자 주식회사 | Method for forming metal line of semiconductor device |
| KR100702802B1 (en) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | Method for forming metal wiring layer of semiconductor device |
| KR100847835B1 (en) * | 2006-12-29 | 2008-07-23 | 동부일렉트로닉스 주식회사 | Method for Removing Foreign Matter from Low-k Dielectric Film in Chemical Mechanical Polishing Process |
| KR101044379B1 (en) * | 2003-12-23 | 2011-06-27 | 매그나칩 반도체 유한회사 | Method for forming dual damascene pattern of semiconductor device |
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| FI97920C (en) * | 1991-02-27 | 1997-03-10 | Okmetic Oy | Ways to clean a semiconductor product |
| JP3282239B2 (en) * | 1992-10-26 | 2002-05-13 | ソニー株式会社 | Method for manufacturing semiconductor device |
| KR0171953B1 (en) * | 1995-12-29 | 1999-03-30 | 김주용 | Layer insulation film forming method of semiconductor device |
| JPH09249980A (en) * | 1996-03-13 | 1997-09-22 | Sumitomo Metal Ind Ltd | Wet etching method of metal material |
| KR980012027A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Cleaning fluid for etching residue removal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100467495B1 (en) * | 2002-06-18 | 2005-01-24 | 동부전자 주식회사 | Method for forming metal line of semiconductor device |
| KR101044379B1 (en) * | 2003-12-23 | 2011-06-27 | 매그나칩 반도체 유한회사 | Method for forming dual damascene pattern of semiconductor device |
| KR100702802B1 (en) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | Method for forming metal wiring layer of semiconductor device |
| KR100847835B1 (en) * | 2006-12-29 | 2008-07-23 | 동부일렉트로닉스 주식회사 | Method for Removing Foreign Matter from Low-k Dielectric Film in Chemical Mechanical Polishing Process |
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