KR20000045474A - Method for manufacturing decoupling capacitor of semiconductor device - Google Patents
Method for manufacturing decoupling capacitor of semiconductor device Download PDFInfo
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- KR20000045474A KR20000045474A KR1019980062032A KR19980062032A KR20000045474A KR 20000045474 A KR20000045474 A KR 20000045474A KR 1019980062032 A KR1019980062032 A KR 1019980062032A KR 19980062032 A KR19980062032 A KR 19980062032A KR 20000045474 A KR20000045474 A KR 20000045474A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
Description
본 발명은 반도체소자의 디커플링 캐패시터 형성방법에 관한 것으로, 특히 워드라인의 디커플링 현상을 최대한 억제하기 위하여 디커플링 캐패시터의 정전용량을 증가시키는 기술에 관한 것이다.The present invention relates to a method of forming a decoupling capacitor of a semiconductor device, and more particularly, to a technique of increasing the capacitance of a decoupling capacitor in order to minimize the decoupling of a word line.
모든 반도체소자는 외부에서 공급되는 전압외에도 내부에서 전압을 발생시키는 많은 회로들이 있으며 여기서 나오는 전압으로 내부 회로들이 동작하게 된다. 이러한, 현상은 반도체소자가 고집적화되어 도전배선 간의 간격이 가까워 질수록 많이 발생되는 현상이다.All semiconductor devices have many circuits that generate internal voltages in addition to externally supplied voltages, and internal circuits operate with the voltages from the semiconductor devices. Such a phenomenon is a phenomenon in which semiconductor devices are highly integrated, and as the distance between conductive wirings increases, the number of times occurs.
일반적으로 반도체소자는 소자분리막, 워드라인을 형성하고 평탄화절연막을 형성한 다음, 비트라인을 형성하고 후속공정을 실시하여 반도체소자를 형성하는 경우에 있어서, 절연막으로 사용되는 상기 평탄화절연막을 유전체로 하는 워드라인과 비트라인을 캐패시터로 생각할 수 있다.In general, in the case of forming a semiconductor device by forming a device isolation film and a word line, forming a planarization insulating film, and then forming a bit line and performing a subsequent process, the semiconductor device is a dielectric material. Word lines and bit lines can be thought of as capacitors.
실제 메모리 셀에 데이터를 읽거나 쓰는 동작을 함에 따라 선택된 셀의 워드라인에는 승압전압인 Vpp 가 인가되고 셀 트랜지스터가 온 ( on ) 됨에 따라 비트라인은 센스앰프의 작동에 의해 비트라인 프리챠지전압인 Vblp 에서 그라운드 ( 0 V ) 또는 외부인가전압 ( 3.3 V ) 로 변하게 된다. 이때, 선택되지않은 셀의 워드라인은 그라운드 전압으로 셀 트랜지스터를 오프 ( off ) 시키고 있어야 하나 비트라인의 전압 변화에 따라 워드라인이 디커플링 되어 셀 트랜지스터를 통한 누설전류, 즉 워드라인 잡음이 발생한다.As a result of reading or writing data to an actual memory cell, a boosted voltage Vpp is applied to a word line of a selected cell, and as the cell transistor is turned on, the bit line becomes a bit line precharge voltage by an operation of a sense amplifier. It changes from Vblp to ground (0 V) or externally applied voltage (3.3 V). At this time, the word line of the unselected cell should be turned off (off) the cell transistor to the ground voltage, but the word line is decoupled according to the voltage change of the bit line to generate leakage current, that is, word line noise through the cell transistor.
그리고, 이에 따른 셀 캐패시터의 데이터 손실로 불량이 발생하게 되어 반도체소자의 특성 및 신뢰성이 저하되고 그에 따른 반도체소자의 고집적화가 어렵게 되는 문제점이 있다.In addition, defects may occur due to data loss of the cell capacitor, thereby deteriorating characteristics and reliability of the semiconductor device and consequently, high integration of the semiconductor device becomes difficult.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 디커플링 캐패시터 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a decoupling capacitor of a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 패드산화막(13)과 패드질화막(15)을 각각 일정두께 형성한다.First, the pad oxide film 13 and the pad nitride film 15 are formed to have a predetermined thickness on the semiconductor substrate 11.
그리고, 상기 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 패드산화막(13)과 패드질화막(15) 적층구조를 식각하여 소자분리영역을 노출시킨다. 이때, 디커플링 캐패시터 영역(100)은 상기 적층구조가 남게 된다. (도 1a)In addition, the device isolation region is exposed by etching the pad oxide layer 13 and the pad nitride layer 15 by the etching process using the device isolation mask (not shown). At this time, the stacking structure of the decoupling capacitor region 100 remains. (FIG. 1A)
그리고, 상기 패드산화막(13)과 패드질화막(15) 적층구조 측벽에 질화막 스페이서(17)를 형성한다. (도 1b)The nitride film spacers 17 are formed on sidewalls of the pad oxide film 13 and the pad nitride film 15. (FIG. 1B)
그 다음, 상기 반도체기판(11)을 열산화시켜 상기 노출된 반도체기판(11) 표면에 소자분리막(19)을 형성한다. (도 1c)Thereafter, the semiconductor substrate 11 is thermally oxidized to form an isolation layer 19 on the exposed surface of the semiconductor substrate 11. (FIG. 1C)
그리고, 상기 패드산화막(13)과 패드질화막(15)을 제거하고, 전체표면상부에 게이트산화막(21)과 게이트전극용 도전체(23) 적층구조를 형성한다.Then, the pad oxide film 13 and the pad nitride film 15 are removed, and a stacked structure of the gate oxide film 21 and the conductor for gate electrode 23 is formed on the entire surface.
그리고, 게이트전극 마스크(도시안됨)를 이용하여 상기 게이트산화막(21)과 게이트전극용 도전체(23)의 적층구조를 식각함으로써 게이트전극을 형성한다.A gate electrode is formed by etching the stacked structure of the gate oxide film 21 and the conductor 23 for a gate electrode using a gate electrode mask (not shown).
여기서, 디커플링 캐패시터 형성 영역(100)은 상기 반도체기판(11)의 활성영역에 형성되는 게이트전극과 같은 구조로 형성된다. (도 1d)Here, the decoupling capacitor formation region 100 is formed in the same structure as the gate electrode formed in the active region of the semiconductor substrate 11. (FIG. 1D)
상기한 바와같이 종래기술에 따른 반도체소자의 디커플링 캐패시터 형성방법은, 반도체기판의 바깥쪽에 워드라인과 접속시켜 워드라인의 디커플링 현상을 방지하는 디커플링 캐패시터가 상기 워드라인과 같은 형상으로 형성되지만 고집적화에 따른 반도체소자의 디커플링 현상을 방지하기는 역부족이어서 반도체소자의 특성 신뢰성이 저하되는 문제점이 있다.As described above, in the method of forming a decoupling capacitor of a semiconductor device according to the related art, a decoupling capacitor is formed in the same shape as that of the word line by connecting the word line to the outside of the semiconductor substrate to prevent the decoupling of the word line. There is a problem in that the decoupling phenomenon of the semiconductor device is inversely insufficient, which deteriorates the characteristic reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 디커플링 현상을 방지하기 위하여 디커플링 캐패시터 영역에 트렌치를 형성하여 캐패시터의 정전용량을 증가시킴으로써 워드라인의 디커플링 현상을 충분히 방지할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 디커플링 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the prior art, in order to prevent the decoupling phenomenon by forming a trench in the decoupling capacitor region to increase the capacitance of the capacitor to sufficiently prevent the decoupling of the word line of the semiconductor device An object of the present invention is to provide a method of forming a decoupling capacitor of a semiconductor device capable of improving characteristics and reliability.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 디커플링 캐패시터 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a decoupling capacitor of a semiconductor device according to the prior art.
도 2a 내지 도 2h 는 본 발명의 실시예에 따른 반도체소자의 디커플링 캐패시터 형성방법을 도시한 단면도.2A to 2H are cross-sectional views illustrating a method of forming a decoupling capacitor of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 패드산화막11,31: semiconductor substrate 13,33: pad oxide film
15,35 : 패드질화막 17,37 : 질화막15,35: pad nitride film 17,37: nitride film
19,39 : 소자분리막 21,43 : 게이트산화막19,39 Device isolation film 21,43 Gate oxide film
23,45 : 게이트전극용 도전체 41 : 트렌치23,45: conductor for gate electrode 41: trench
100,200 : 디커플링 캐패시터 형성영역100,200: decoupling capacitor formation area
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 디커플링 캐패시터 형성방법은,In order to achieve the above object, a method of forming a decoupling capacitor of a semiconductor device according to the present invention,
반도체기판 상부에 패드산화막과 패드질화막을 패터닝하여 소자분리영역과 디커플링 캐패시터 형성영역을 정의하되, 디커플링 캐패시터 형성영역의 패드산화막과 패드질화막 적층구조를 다수의 패턴으로 형성하는 공정과,Defining a device isolation region and a decoupling capacitor formation region by patterning the pad oxide layer and the pad nitride layer on the semiconductor substrate, wherein forming the pad oxide layer and the pad nitride layer stacked structure of the decoupling capacitor formation region in a plurality of patterns;
상기 패드산화막과 패드질화막 적층구조의 측벽에 질화막 스페이서를 형성하는 공정과,Forming a nitride film spacer on sidewalls of the pad oxide film and the pad nitride film stack structure;
상기 소자분리영역에 소자분리막을 형성하는 공정과,Forming an isolation layer in the isolation region;
상기 질화막 스페이서와 패드질화막을 전면식각하여 상기 디커플링 캐패시터 형성영역의 반도체기판 표면을 다수 노출시키는 공정과,Exposing the surface of the semiconductor substrate of the decoupling capacitor formation region by etching the entire surface of the nitride film spacer and the pad nitride film;
상기 질화막 스페이서와 패드질화막 및 소자분리막을 마스크로하여 상기 디커플링 캐패시터 형성영역의 반도체기판에 다수의 트렌치를 형성하는 공정과,Forming a plurality of trenches in the semiconductor substrate in the decoupling capacitor formation region using the nitride spacers, the pad nitride layers, and the isolation layers as masks;
상기 질화막 스페이서와 패드질화막을 제거하는 공정과,Removing the nitride film spacer and the pad nitride film;
상기 반도체기판 표면에 게이트산화막과 게이트전극용 도전체를 형성하고 이를 패터닝함으로써 게이트전극과 디커플링 캐패시터를 형성하는 공정을 포함하는 것을 특징으로한다.Forming a gate electrode and a decoupling capacitor by forming a gate oxide film and a conductor for the gate electrode on the surface of the semiconductor substrate.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h 는 본 발명의 실시예에 따른 반도체소자의 디커플링 캐패시터 형성방법을 도시한 단면도로서, 불순물 임플란트 공정은 생략하고 도시하지 않은 것이다.2A to 2H are cross-sectional views illustrating a method of forming a decoupling capacitor of a semiconductor device in accordance with an embodiment of the present invention, and do not show an impurity implant process.
먼저, 반도체기판(31) 상부에 패드산화막(33)과 패드질화막(35)을 각각 일정두께 형성한다. 이때, 상기 패드산화막(33)은 50 ∼ 100 Å 두께로 형성하고 상기 패드질화막(35)은 900 ∼ 2000 Å 두께로 형성한다.First, a pad oxide film 33 and a pad nitride film 35 are formed on the semiconductor substrate 31 at a predetermined thickness. In this case, the pad oxide film 33 is formed to a thickness of 50 ~ 100 GPa and the pad nitride film 35 is formed to a thickness of 900 ~ 2000 GPa.
그리고, 소자분리막마스크(도시안됨)를 이용한 식각공정으로 상기 패드산화막(33)과 패드질화막(35) 적층구조를 식각하여 소자분리영역을 노출시키되, 디커플링 캐패시터 형성영역의 상기 적층구조를 일정간격을 갖는 다수의 패턴으로 형성한다. 이때, 상기 디커플링 캐패시터 형성영역에 형성되는 적층구조가 갖는 일정간격은 300 ∼ 1000 Å 정도이다. (도 2a)In addition, the device isolation region is exposed by etching the pad oxide layer 33 and the pad nitride layer 35 by an etching process using an element isolation layer mask (not shown), and the layer structure of the decoupling capacitor formation region is spaced at a predetermined interval. To form a plurality of patterns having. At this time, a predetermined interval of the laminated structure formed in the decoupling capacitor formation region is about 300 to 1000 Å. (FIG. 2A)
그 다음, 전체표면상부에 질화막(37)을 200 ∼ 500 Å 두께로 형성하고 이를 이방성식각하여 상기 패드산화막(33)과 패드질화막(35) 적층구조 측벽에 질화막(37) 스페이서를 형성한다. (도 2b, 도 2c)Next, a nitride film 37 is formed on the entire surface to a thickness of 200 to 500 Å and anisotropically etched to form a nitride film 37 spacer on the sidewalls of the pad oxide film 33 and the pad nitride film 35. (FIG. 2B, FIG. 2C)
그리고, 상기 반도체기판(31)을 열산화시켜 소자분리영역에 소자분리막(39)을 형성한다. (도 2d)The semiconductor substrate 31 is thermally oxidized to form an isolation layer 39 in the isolation region. (FIG. 2D)
그 다음, 상기 소자분리막(39)과 패드질화막(35) 및 질화막(37) 스페이서의 식각선택비 차이를 이용하여 상기 패드질화막(35)과 질화막(37) 스페이서를 전면식각하여 상기 디커플링 캐패시터 형성 영역(200)의 적층구조 사이 사이에 상기 반도체기판(31)을 일정간격으로 노출시키되, 300 ∼ 700 Å 간격으로 한다. (도 2e)Subsequently, the pad nitride layer 35 and the nitride layer 37 spacers are etched by using the difference in the etch selectivity between the device isolation layer 39, the pad nitride layer 35, and the nitride layer 37 spacers to form the decoupling capacitor formation region. The semiconductor substrate 31 is exposed at regular intervals between the stacked structures of 200, with a spacing of 300 to 700 Å. (FIG. 2E)
그리고, 상기 패드산화막(33)과 패드질화막(35) 적층구조를 마스크로 하여 상기 반도체기판(31)을 식각함으로써 상기 디커플링 캐패시터 형성영역(200)에 다수의 트렌치(41)를 형성한다. 이때, 상기 트렌치(41)는 300 ∼ 2000 Å 깊이로 형성한다. (도 2f)The semiconductor substrate 31 is etched using the pad oxide layer 33 and the pad nitride layer 35 as a mask to form a plurality of trenches 41 in the decoupling capacitor formation region 200. At this time, the trench 41 is formed to a depth of 300 ~ 2000Å. (FIG. 2F)
그 다음, 상기 패드산화막(33)과 패드질화막(35) 적층구조 및 질화막(37) 스페이서를 제거하고 상기 트렌치(41)를 포함한 반도체기판(31) 표면에 게이트산화막(43)과 게이트전극용 도전체(45)를 형성한 다음, 게이트전극 마스크(도시안됨)를 이용한 식각공정으로 상기 게이트전극용 도전체(45)를 패터닝하여 게이트전극 및 디커플링 캐패시터를 형성한다. (도 2g, 도 2h)Next, the pad oxide film 33 and the pad nitride film 35 stacked structure and the nitride film 37 spacer are removed, and the gate oxide film 43 and the gate electrode conductive on the surface of the semiconductor substrate 31 including the trench 41 are removed. After the sieve 45 is formed, the gate electrode conductor 45 is patterned by an etching process using a gate electrode mask (not shown) to form a gate electrode and a decoupling capacitor. (FIG. 2G, FIG. 2H)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 디커플링 캐패시터 형성방법은, 디커플링 캐패시터의 정전용량을 증가시켜 게이트전극, 즉 워드라인의 디커플링 현상을 방지함으로써 노이즈를 제거하고 누설전류를 감소시켜 반도체소자의특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of forming a decoupling capacitor of a semiconductor device according to the present invention increases the capacitance of the decoupling capacitor to prevent decoupling of the gate electrode, that is, the word line, thereby removing noise and reducing leakage current, thereby reducing the leakage current of the semiconductor device. There is an effect that can improve the characteristics and reliability.
Claims (7)
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KR20040001962A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Method of manufacture merged trench dram logic device |
US7485911B2 (en) | 2005-09-05 | 2009-02-03 | Samsung Electronics Co., Ltd. | Semiconductor device having decoupling capacitor and method of fabricating the same |
CN110655033A (en) * | 2018-06-29 | 2020-01-07 | 英飞凌科技德累斯顿公司 | Improved stress decoupling MEMS sensor |
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KR100261210B1 (en) * | 1992-06-20 | 2000-07-01 | 윤종용 | Method for manufacturing decoupling capacitor |
JP3071627B2 (en) * | 1993-12-28 | 2000-07-31 | 京セラ株式会社 | Semiconductor device |
US5770875A (en) * | 1996-09-16 | 1998-06-23 | International Business Machines Corporation | Large value capacitor for SOI |
JPH10256489A (en) * | 1997-03-14 | 1998-09-25 | Mitsubishi Electric Corp | Semiconductor device |
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KR20040001962A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Method of manufacture merged trench dram logic device |
US7485911B2 (en) | 2005-09-05 | 2009-02-03 | Samsung Electronics Co., Ltd. | Semiconductor device having decoupling capacitor and method of fabricating the same |
US7883970B2 (en) | 2005-09-05 | 2011-02-08 | Samsung Electronics Co., Ltd. | Semiconductor device having decoupling capacitor and method of fabricating the same |
CN110655033A (en) * | 2018-06-29 | 2020-01-07 | 英飞凌科技德累斯顿公司 | Improved stress decoupling MEMS sensor |
CN110655033B (en) * | 2018-06-29 | 2023-04-28 | 英飞凌科技德累斯顿公司 | Improved stress decoupling MEMS sensor |
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