JPH10256489A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To elongate the life of decoupling capacity made in a high-voltage input path, and raise the reliability on an element, by applying voltage smaller than the voltage between an internal power source and GND to first and second MOS capacitors. SOLUTION: They show the potential Vpp6n of the internal power source connected to the gate electrode 4a of a MOS capacitor 9, and the potential 7 of GND connected to one N<+> region 5d of a MOS capacitor 10, and one N<+> region 5b of the MOS capacitor 9 is connected electrically to the gate electrode 4b of the MOS capacitor 10. The decoupling capacitor is of such constitution that the MOS capacitors 9 and 10 are arranged in series between the potential Vpp6 of the internal power source and the potential 7 of GND. Hereby, the voltage applied to the gate insulating films 3a and 3b constituting the MOS capacitors 9 and 10 can be made half the conventional one. Then, the life of the gate insulating films 3a and 3b can be increased tenfold or over.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly, to a decoupling capacitor which is disposed on a high voltage input path such as a power input path and suppresses fluctuations in power supply potential and internal power supply potential. It is related to the structure of.

[0002]

2. Description of the Related Art Generally, a decoupling capacitor is arranged between a wiring electrically connected to an internal power supply and a GND (ground), and plays a role of suppressing fluctuation of the power supply.
The internal power supply may generate a voltage lower than the externally applied voltage or may generate a voltage higher than the externally applied voltage.
It is called p (internal power supply potential). The decoupling capacitance usually has a small area, so a large capacitance can be obtained.
An S capacitor is used.

FIG. 7 shows a conventional decoupling capacitance M
FIG. 2 is a schematic cross-sectional view of an OS capacitor, in which reference numeral 101 denotes a P-well region formed in the semiconductor substrate, and 102 denotes an element formed on the surface of the semiconductor substrate so as to surround the P-well region 101. An isolation region 103 is a gate insulating film formed on a region to be a channel region.
04 is a gate electrode laminated on the gate insulating film 103,
Reference numeral 105 denotes a P well region 1 with a channel region interposed therebetween.
01 is a source / drain region (impurity diffusion region) composed of an n-type high-concentration impurity region, and 106 is an internal power supply potential Vpp electrically connected to the gate electrode 104.
107, a GND potential electrically connected to the source / drain region 105, respectively; and 108, a back gate potential Vbb electrically connected to the P well region 101, respectively.

Using the above decoupling capacitance,
When the internal power supply potential Vpp 106 is connected to the gate electrode 104 and the GND potential 107 is connected to the source / drain region 105, noise enters the internal power supply potential Vpp 106, causing a reduction in Vpp due to an abnormal voltage or power consumption. Even so, it works to keep the normal voltage between Vpp and GND constant, and it is possible to reduce the influence of noise.

FIG. 8 shows a power supply capacitance circuit disclosed in Japanese Patent Application Laid-Open No. 2-58275. In this power supply capacitance circuit, a MOS transistor (MOS N ₁ ) connected in series with a MOS capacitor (MOS D ₁ ) connected in series between an internal power supply potential Vpp 106 and a GND potential 107 is provided. MOS capacitor (MOS D ₁ ) and MOS
There is an example in which another MOS capacitor (MOS D ₂ ) connected in series and another MOS transistor (MOS P ₁ ) that is always conducting are arranged in parallel with the transistor (MOS N ₁ ).

[0006]

The decoupling capacitance according to the prior art is such that the internal power supply potential Vpp 106 is always applied when a power supply voltage is applied to the semiconductor device from the outside, so that the MOS of other circuits constituting the semiconductor device is reduced. An insulating film (gate insulating film 10) having a MOS structure rather than a transistor portion
The deterioration of 3) is remarkable. Since the life of the gate insulating film 103 determines the life of the entire semiconductor device, the gate insulating film 10 is used to improve the reliability of elements constituting the semiconductor device.
It has become important to extend the life of No.3.

Furthermore, the same applies to the decoupling capacitor using the technique disclosed in JP-A-2-58275, MOS capacitors (MOS D ₁ and MOS D ₂₎ and the MOS transistor of the normally conductive state (MOS P ₁ And a voltage between Vpp and GVD is applied to the MOS N ₁ ), the voltage applied to both ends of the MOS capacitor is not reduced, and the lifetime of the entire semiconductor device is shortened due to deterioration of the gate insulating film. In order to solve the problem, it is necessary to extend the life of the gate insulating film.

SUMMARY OF THE INVENTION It is an object of the present invention to extend the life of a decoupling capacitor formed on a high-voltage input path such as a power supply input path of a semiconductor device and improve the reliability of elements.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device including a decoupling capacitor including first and second MOS capacitors connected in series between an internal power supply and GND. , A voltage smaller than the voltage between the internal power supply and the GND is applied to the second MOS capacitor.

According to a second aspect of the present invention, there is provided a semiconductor device comprising:
First and second M connected in series between the internal power supply and GND
A potential of the internal power supply is supplied to a first gate electrode forming the first MOS capacitor, the first impurity diffusion region forming the first MOS capacitor, and a second MOS transistor including an OS capacitor. The second gate electrode forming the capacitor is electrically connected to the second gate electrode.
The second impurity diffusion region constituting the OS capacitor has a decoupling capacitance for supplying the GND potential.

Further, according to a third aspect of the present invention, there is provided a semiconductor device, comprising: a first conductivity type well region formed on a semiconductor substrate; a first MOS capacitor and a second MOS transistor formed on the well region. A first M
The OS capacitor has a first gate electrode formed on a region serving as a first channel on the surface of the well region via a first gate insulating film, and a first gate electrode formed in contact with the first channel region. The second MOS capacitor includes a first impurity diffusion region of a second conductivity type, and the second MOS capacitor is formed on a region serving as a second channel region on the surface of the well region via a second gate insulating film. A second gate electrode and a second impurity diffusion region of a second conductivity type formed in contact with the second channel region, and the first gate electrode is supplied with a potential of an internal power supply; By electrically connecting a first impurity diffusion region to the second gate electrode and supplying a potential of GND to the second impurity diffusion region, the first and second MOS capacitors are connected to the internal region. In series between the power supply and the GND And has a decoupling capacitance that location.

In a semiconductor device according to a fourth aspect of the present invention, in the decoupling capacitance including a MOS capacitor and a junction capacitor connected in series between an internal power supply and GND, the MOS capacitor includes the internal power supply and the GN
A voltage smaller than the voltage between D is applied.

Further, in a semiconductor device according to a fifth aspect of the present invention, there is provided a well region formed in a semiconductor substrate, a gate formed on the well region via a gate insulating film, and supplied with a potential of an internal power supply. By supplying a potential of the internal power supply to the electrode and the gate electrode, a channel region in which a depletion layer is formed in the well region is formed in the well region in contact with the channel region, and has the same conductivity as the well region. A first capacitor formed of the gate electrode and a second capacitor formed of the depletion layer between the internal power supply and the GND. It has a decoupling capacitance characterized by being arranged in series.

According to a sixth aspect of the present invention, in addition to the structure of the semiconductor device according to any one of the first, second and third aspects, a first MOS capacitor and a second MOS capacitor are provided. A plurality of first gate electrodes and second gate electrodes are arranged side by side in the gate length direction, and the first gate electrode and the second gate electrode are alternately comb-shaped. It has a decoupling capacitance to be arranged.

According to a seventh aspect of the present invention, in addition to the structure of the semiconductor device according to any one of the second and third aspects, the impurity diffusion region is formed in a gate length direction of one gate electrode. In contrast, a decoupling capacitor in which one is disposed at one end of the gate electrode.

According to an eighth aspect of the present invention, in addition to the structure of the semiconductor device according to any one of the second, third and sixth aspects, the first and second gate electrodes have one end. Are disposed on the element isolation region formed on the surface of the semiconductor substrate and have a decoupling capacitance in which an impurity diffusion region is formed near the other end of the gate electrode.

Further, according to a ninth aspect of the present invention, there is provided a semiconductor device, wherein a first conductivity type well region formed in a semiconductor substrate and a region serving as a channel region of the well region are interposed via a gate insulating film. The formed floating gate, a gate electrode formed on the floating gate through an interpoly insulating film having a thickness equal to or less than the thickness of the gate insulating film, and the channel region in the well region. The semiconductor device includes a second conductive type impurity diffusion region formed in contact therewith, and has a decoupling capacitor for supplying a potential of an internal power supply to the gate electrode and supplying a GND potential to the impurity diffusion region. .

According to a tenth aspect of the present invention, there is provided a semiconductor device comprising: a MOS capacitor formed on a semiconductor substrate;
A stack capacitor formed on the MOS capacitor via an interlayer insulating film, wherein one of the opposite electrodes forming the stack capacitor is electrically connected to a gate electrode forming the MOS capacitor; The potential of the internal power supply is supplied to the other electrode constituting the MOS capacitor, the potential of GND is supplied to the impurity diffusion region constituting the MOS capacitor, and the insulating film interposed between the opposed electrodes is a gate constituting the MOS capacitor. It has a decoupling capacitance to be a thickness corresponding to a film thickness of one half or less of the insulating film.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Embodiment 1 of the present invention will be described. FIG. 1A shows a cross-sectional view of the decoupling capacitance of the semiconductor device of the present invention, and FIG.
Shows a circuit diagram equivalent to FIG. In the figure, 1 is a P well region formed in a semiconductor substrate, 2 is an element isolation region formed on the surface of the P well region 1, 3
a, 3b and 4a and 4b denote gate insulating films and gate electrodes constituting the MOS capacitors 9 and 10 formed on the P well region 1, respectively, and 5a, 5b and 5c and 5d denote P
This is an impurity diffusion region in which an impurity of the opposite conductivity type to the well region 1 is implanted or diffused.
An N-type high-concentration impurity region (hereinafter, referred to as an N ⁺ region) 6 corresponding to the source / drain region 0 is an internal power supply potential Vp connected to the gate electrode 4a of the MOS capacitor 9.
p and 7 indicate the GND potential connected to one N ⁺ region 5d of the MOS capacitor 10, 8 indicates the back gate potential Vbb supplied to the well region 1, and one N ⁺ region 5b of the MOS capacitor 9 indicates , Is electrically connected to the gate electrode 4b of the MOS capacitor 10.

As can be seen from FIG. 1B, the decoupling capacitance has a structure in which MOS capacitors 9 (C1) and 10 (C2) are arranged in series between the internal power supply potential Vpp6 and the GND potential 7. ing. Therefore, the voltage applied to the gate insulating films 3a, 3b constituting the MOS capacitors 9, 10 can be reduced to one half of the conventional voltage.
The electric field applied to the MOS capacitors 9 and 10 is 1 MV / cm
By lowering, the life of the gate insulating films 3a and 3b can be made 10 times or more. Therefore, assuming that the electric field applied to the MOS capacitor having the conventional decoupling capacitance is about 4 MV / cm, the present invention is applied. Thereby, the life of the gate insulating films 3a and 3b can be made 100 times or more of the conventional life. Therefore, the life of the decoupling capacitor can be significantly extended, and a more reliable semiconductor device can be obtained.

The decoupling capacity is about 0.1 to 1 mm ² in one chip, and several hundred μm.
It is divided into m-squares and connected to a portion where a high-voltage power supply line runs and arranged and formed.

Further, in the example shown in FIG. 1, an example in which MOS capacitors 9 and 10 are arranged on P well region 1 has been described, but similarly, on the N well region of the opposite conductivity type, It is also possible to form a P-type high-concentration impurity region (P ⁺ region) as an impurity diffusion region and supply a GND potential to the gate electrode of one MOS capacitor and an internal power supply potential to the impurity diffusion region of the other MOS capacitor. It is possible to obtain a semiconductor device having high decoupling capacitance, and the same can be said for other embodiments described later.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described. The difference between the second embodiment and the first embodiment of the present invention is that, in the first embodiment, the decoupling capacitance is composed of two MOS capacitors connected in series between the internal power supply and GND. The decoupling capacitance of the second embodiment has a configuration in which one MOS capacitor and one junction capacitance are connected in series between the internal power supply and GND, and the decoupling capacitance is composed of one element.

FIG. 2A shows a cross-sectional view of the decoupling capacitance according to the second embodiment, and FIG.
(B). In FIG. 2A, reference numeral 3 denotes a gate insulating film, and 4 denotes a gate insulating film.
The gate electrode 11 is connected to the gate insulating film 3 by applying the internal power supply potential Vpp6 to the gate electrode 4.
A depletion layer 12 is formed underneath, 12 is a MOS capacitor including the above-mentioned components, and 50a and 50b are P ⁺ regions (impurity diffusion regions) composed of P-type high-concentration impurity regions. In addition, the same reference numerals as those already described indicate the same or corresponding parts. Among them, the back gate potential (potential of the well electrode) 8 is set to the same potential as the GND potential 7. Back gate potential (potential of well electrode) 8 is set to V
In the case of bb, the potential of the portion indicated by reference numeral 7 is Vbb.

FIG. 2B is a circuit diagram equivalent to the decoupling capacitance having the configuration shown in FIG. 2A. The gate electrode 4 is provided between the internal power supply potential Vpp 6 and the GND potential 7. Depletion layer 11 and gate electrode 4 formed below gate insulating film 3 by applying internal power supply potential Vpp6 to
And a MOS capacitor 12 in which a capacitor (junction capacitance) 12b including a depletion layer 11 and a P-type diffusion region 50b is connected in series.

In the decoupling capacitor configured as described above, the voltage applied to the MOS capacitor 12 is reduced by the capacitor 12a and the capacitor 1a as compared with the conventional case.
2b, the voltage applied to both ends of the gate insulating film 3 constituting the MOS transistor 12 can be suppressed small, and the life of the gate insulating film 3 can be extended. Becomes

Since the extent of the depletion layer 11 is determined by the dopant concentration of the semiconductor substrate (channel region) immediately below the gate insulating film 4, the impurity is a doping impurity (in this case, an acceptor impurity such as boron). When formed as a reverse conductivity type, the magnitude of the junction capacitance is adjusted by the concentration of donor impurities such as arsenic,
At the same time, the electric field applied to the gate insulating film 3 of the MOS capacitor 12 can be adjusted.

Embodiment 3 Next, a third embodiment of the present invention will be described. The decoupling capacitance shown in the first embodiment is an example in which two MOS capacitors are arranged in series between the internal power supply potential Vpp and the GND potential. However, the decoupling capacitance according to the third embodiment is different from that of the first embodiment. The width occupied by the MOS capacitor of mode 1 is 10
.About.30 .mu.m to form a plurality of electrodes, and the other MO is placed between the gate electrodes of one MOS capacitor arranged at equal intervals.
In this state, the divided gate electrodes of the S capacitor are arranged.

FIG. 3A is a sectional configuration diagram of a decoupling capacitor included in the semiconductor device of the third embodiment, FIG. 3B is an equivalent circuit diagram thereof, and FIG.
It is shown in (c). FIG. 3C is a cross-sectional configuration diagram of FIG.
5 corresponds to a sectional view taken along line aa in FIG. In the drawing, the same reference numerals have been used for the description to denote the same or corresponding parts, and reference numerals 9a and 10a are arranged in series between the internal power supply potential Vpp6 and the GND potential 7, respectively. MOS capacitors 41a and 41b are gate electrodes 51a, which constitute MOS capacitors 9a and 10a.
Reference numerals 51b, 51c and 51d denote impurity diffusion regions constituting MOS capacitors, respectively, and 61 denotes a plurality of gate electrodes 4
A Vpp line electrically connected to 1a and supplying the internal power supply potential Vpp6 is shown.

As shown in FIG. 3C, one of the MOs
The gate electrode 41a of the S capacitor 9a and the gate electrode 41b of the other MOS capacitor 10a are alternately arranged,
The gate electrode 41a is arranged such that the end thereof is connected to the Vpp line 61. Thus, the MO with a small gate length
The S-capacitors 9a and 10a are alternately arranged in one direction so as to be in a comb shape, whereby the gate electrodes 41a and 41b are also arranged in a comb shape, so that the additional resistance (connected to each capacitor) is reduced. (Eg, the resistance of the gate electrode from the contact to the center of the capacitor, the channel resistance of the MOS capacitor, etc.) can be reduced, and the decoupling capacitance with good electrical characteristics can be obtained.

As shown in FIG. 3B, the decoupling capacitance of the third embodiment can be basically represented by a circuit diagram equivalent to the decoupling capacitance of the first embodiment. As in the first embodiment, since two capacitors having substantially the same capacitance are arranged in series between internal power supply potential Vpp6 and GND potential 7, the MO
The voltage applied to both ends of the gate insulating films 3a and 3b of the S capacitor can be suppressed to about half, and the life of the MOS capacitor can be made 100 times or more as compared with the conventional one.

Embodiment 4 FIG. Next, the decoupling capacitance included in the semiconductor device of the fourth embodiment will be described. In the structure of the third embodiment described above, the MOS capacitors 9a and 10a have two impurity diffusion regions 51a, 51b or 51c, 51d as constituent elements, respectively. The formed capacitor has only one impurity diffusion region 52a or 52b for one capacitor, and the ends of the gate electrodes 42a and 42b on which the impurity diffusion region 52a or 52b is not formed are separated by an element. It is characterized in that it is arranged so as to partially ride on the area 2.

FIG. 4A is a cross-sectional view of a decoupling capacitor according to the fourth embodiment, FIG. 4B is an equivalent circuit diagram thereof, and FIG. 4C is a schematic plan view thereof. FIG.
The cross-sectional configuration diagram of FIG. 4A corresponds to the cross-sectional view taken along line aa in FIG.

In the figure, the same reference numerals as those already used for the description indicate the same or corresponding parts, and the reference numerals 9b and 10b denote the internal power supply potential V, respectively.
MOS arranged in series between pp6 and GND potential 7
The capacitors 42a and 42b are MOS capacitors 9b,
10b, and the gate electrode 4b.
One end in the gate length direction of 2a, 42b is connected to the element isolation region 2
It is arranged and formed in a state of riding on top. In addition, 5
Reference numerals 2a and 52b denote impurity diffusion regions formed on the surface of the P well region 1 near the other ends of the gate electrodes 42a and 42b, respectively.

In the semiconductor device of the fourth embodiment, only one impurity diffusion region is formed for one MOS capacitor, and internal power supply potential Vpp6 and GND
MOS capacitor 9 arranged in series with potential 7
A plurality of b and 10b are alternately arranged in the gate length direction (comb arrangement), and the end portions of the gate electrodes 42a and 42b on the side opposite to the side where the respective impurity diffusion regions 52a and 52b are formed. Is characterized in that a part of the element is mounted on the element isolation region 2.

Therefore, this semiconductor device has a structure in which only one impurity diffusion region is formed for one capacitor, and a part of the gate electrode runs on the element isolation region, thereby improving the area efficiency. It is possible. further,
The width of each of the MOS capacitors 9b and 10b is set to about 10 to 30 μm, and the gate electrodes 42a and 42b are divided into a plurality of parts and are alternately arranged in a comb shape.
Variations in the distance between the connection position between the gate electrode 42a and the other wiring and all the positions in the gate electrodes 42a and 42b can be reduced, and a decoupling capacitor having good electric characteristics can be obtained.

As in the semiconductor devices of the other embodiments already described, internal power supply potential Vpp 6 and GND potential 7
By forming two MOS capacitors 9b and 10b arranged in series with each other, the voltage applied to both ends of one MOS capacitor can be reduced, and the dielectric breakdown of the gate insulating films 3a and 3b can be suppressed. It is possible to
It goes without saying that the life of the decoupling capacitor can be extended.

Embodiment 5 Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG. 5A showing a cross-sectional configuration diagram of a decoupling capacitor, and FIG. 5B showing an equivalent circuit diagram.

5 (a) and 5 (b), the same reference numerals as those already used for the description denote the same or corresponding parts, and 31a is supplied with the internal power supply potential Vpp6. Interpoly insulating film 31b formed between the gate electrode 43a and the floating gate 43b formed thereunder, in a state sandwiched between the floating gate 43b and the P well region 1 in the semiconductor substrate. The gate insulating films 53a and 53b are arranged in the P-well region 1 with the channel region below the gate electrode 43a interposed therebetween, and are N ⁺ regions (impurity diffusion regions) formed of N-type high-concentration impurity regions supplied with the GND potential 7. region)
9c is a capacitor having the gate electrode 43a and the floating gate 43b as counter electrodes, and 10c is a capacitor having the floating gate 43b and the N ⁺ regions 53a and 53a.
b respectively represent the capacitors constituted by.

The decoupling capacitance of the semiconductor device according to the fifth embodiment is formed by the combination of the gate electrode 43a of one MOS capacitor and the gate insulating film 31b, as shown in the sectional view of FIG. An interpoly insulating film 31a and a floating gate 43a are formed therebetween, and the internal power supply potential 6 is applied to the gate electrode 43a, and the N ⁺ region 53a,
It is characterized in that the GND potential 7 is supplied to 53b.

By forming one MOS capacitor having the floating gate 43b formed as shown in FIG. 5A, the two capacitors 9c and 10c are electrically connected as shown in FIG. 5B. It can be made equivalent to the case where they are arranged in series.

The thickness of the interpoly insulating film 31a in terms of an oxide film is adjusted so as to be equal to or less than the thickness of the gate insulating film 31b formed of a silicon oxide film. Further, this decoupling capacitance is equal to internal power supply potential Vpp6 with respect to gate electrode 31b.
And the source / drain regions 53a and 53b are
By supplying power to the D potential 7, the internal power supply potential Vpp6 and G
The same effect as the decoupling capacitance of the first embodiment in which two capacitors are arranged in series between the ND potential 7 can be obtained, and the life of the decoupling capacitance can be extended.

Further, the decoupling capacitance of the fifth embodiment is such that the floating gate 43b and the interpoly insulating film 31a are connected to the gate electrode 43a and the gate insulating film 31b.
Since it can be formed by arranging between them, the dimension in the horizontal direction is small, the element formation area can be used effectively, and it can be said that the structure is suitable for high integration of elements.

Embodiment 6 FIG. Next, FIG. 6A is a sectional configuration diagram of a decoupling capacitance of the semiconductor device according to the fifth embodiment of the present invention, FIG. 6B is an equivalent circuit diagram thereof, and FIG. MOS capacitor 13 shown in FIG.
FIG. 6 (c) is a cross-sectional view of the gate electrode 4 of FIG.

In the reference numerals shown in the figure, the reference numerals already used for the description are the same or corresponding parts, and the reference numeral 14 designates a stack capacitor 17 formed on the MOS capacitor 13. A storage node, 15 is a cell plate which is a counter electrode of the storage node 14, 16 is a capacitor insulating film sandwiched between the storage node 14 and the cell plate 15, and 18 is an electric connection between the gate electrode 3 and the storage node 14. Contacts 54a and 54b are MOS capacitors 1
3 shows N ⁺ regions (impurity diffusion regions).

The decoupling capacitance according to the sixth embodiment has a structure in which a stack capacitor 17 is arranged on a normal structure MOS capacitor 13 with an interlayer insulating film interposed therebetween. The thickness of the gate insulating film 3 is not more than half the thickness of the gate insulating film 3 of the MOS capacitor 13 (the gate insulating film 3).
(The value when converted to the substance constituting the above). Further, the N ⁺ region 54 of the MOS capacitor 13
a and 54b have a GND potential 7 and a stack capacitor 1
By connecting the internal power supply potential Vpp6 to the cell plate 15 of FIG. 7, electrically the same as the decoupling capacitance shown in the first embodiment as shown in the circuit diagram of FIG.
Two capacitors are arranged in series between the internal power supply and GND.

Thus, on the MOS capacitor 13,
A stack capacitor 17 having approximately twice the capacity of the MOS capacitor 13 is arranged, and the N ⁺
GND is provided in at least one of the regions 54a and 54b.
By connecting the potential 7 and the internal power supply potential Vpp6 to the cell plate 15 of the stack capacitor 17, the MOS capacitor 13 and the stack capacitor 17 are connected.
It is possible to reduce the voltage applied to the gate insulating film 3 constituting the MOS capacitor 13 to about two thirds of the conventional voltage. As a result, when the electric field applied to the conventional MOS capacitor is about 4 MV / cm, the life can be at least ten times the conventional life, and the reliability of the decoupling capacitance can be improved. Become.

Further, since the stacked capacitor 17 is arranged on the MOS capacitor 13 with an interlayer insulating film interposed therebetween, the element formation area can be effectively utilized, and the structure suitable for high integration of the element can be obtained. can do.

In the sixth embodiment, the contact 18 connecting the gate electrode 4 and the storage node 14 is arranged at both ends in the gate width direction of the gate electrode 4 as shown in FIG. Although they are formed at two places so as to be arranged, for example, different numbers of contacts 18 may be formed at different positions.

Further, in addition to the state where the stack capacitor 17 completely overlaps the MOS capacitor 13,
It is needless to say that the effect of extending the life of the decoupling capacitor can be obtained even when at least a part of them is superimposed as in the case described above.

[0051]

The effects of each claim of the present invention will be described below. According to the semiconductor device of the first aspect of the present invention, by arranging two MOS capacitors in series between the internal power supply and GND, the voltage applied to each MOS capacitor is suppressed to a small value, and the life of the gate insulating film is reduced. It is possible to extend the life of the decoupling capacitance by extending the length.

According to the semiconductor device of the second aspect of the present invention, two MOS capacitors are arranged in series between the internal power supply and GND as a decoupling capacitance formed on the power supply input path, so that one MOS capacitor can be used. It is possible to extend the life of the decoupling capacitor by reducing the applied voltage, suppressing the dielectric breakdown of the gate insulating film, and extending the life.

According to the semiconductor device of the third aspect of the present invention, two MOS capacitors are arranged in series between the internal power supply and the GND as a decoupling capacitance formed in the power supply input path, so that the gate insulation of the MOS capacitor is achieved. It is possible to extend the life of the decoupling capacitor by reducing the voltage applied to the film, suppressing the dielectric breakdown of the gate insulating film, and extending the life.

Further, according to the semiconductor device of the fourth aspect of the present invention, by arranging the MOS capacitor and the junction capacitance in series between the internal power supply and GND, the voltage applied to the MOS capacitor can be suppressed small, and the gate voltage can be reduced. By extending the life of the insulating film, the life of the decoupling capacitor can be extended.

Further, according to the semiconductor device of the fifth aspect of the present invention, the internal power supply potential is supplied to the gate electrode of one MOS capacitor, the GND potential is supplied to the impurity diffusion region, and the depletion layer is provided in the channel region of the MOS capacitor. By forming the MOS capacitor, it is possible to electrically arrange two capacitors in series in the formation area of one MOS capacitor, reduce the voltage applied to the gate insulating film of the MOS capacitor, and reduce the decoupling. It is possible to extend the life of the capacity.

According to the semiconductor device of the sixth aspect of the present invention, in addition to the effects of the first, second and third aspects, M
By dividing the gate electrode of the OS capacitor into a plurality of parts and arranging them in a comb shape, it is possible to reduce the distance from the end of the gate electrode to the wiring connected to the gate electrode. A semiconductor device having a decoupling capacitance can be obtained.

Further, according to the semiconductor device of the seventh aspect of the present invention, in addition to the effects of the second and third aspects, one MOS capacitor is further formed to constitute one MOS capacitor.
It is also possible to configure a capacitor, and it is possible to reduce the formation area of the element in the horizontal direction.

According to the semiconductor device of the eighth aspect of the present invention, in addition to the effects of the second, third, and sixth aspects, the gate electrode is partially formed on the element isolation region, so that the lateral The size in the direction can be miniaturized, and there is an effect that the element formation area can be used effectively.

Further, according to the semiconductor device of the ninth aspect of the present invention, a MOS capacitor having a floating gate is formed, and the internal power supply potential is supplied to the gate electrode and the GND potential is supplied to the impurity diffusion region.
It is possible to place two capacitors between D,
Thus, the voltage applied to the gate insulating film can be reduced, and the life of the decoupling capacitor can be extended by extending the life of the gate insulating film. In addition, the element formation area for forming one decoupling capacitor is small, and the structure is suitable for high integration.

According to the semiconductor device of the tenth aspect of the present invention, the stacked capacitor is stacked on the MOS capacitor, and the thickness of the insulating film interposed between the opposing electrodes of the stacked capacitor is reduced by the gate insulation of the MOS capacitor. When the thickness of the film is equal to or less than half the thickness of the film, the voltage applied to the gate insulating film can be reduced, and the life of the decoupling capacitor can be extended by extending the life of the gate insulating film. It can be extended. In addition, the element formation area for forming one decoupling capacitor is small, and the structure is suitable for high integration.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a semiconductor device according to a second embodiment of the present invention.

FIG. 3 shows a semiconductor device according to a third embodiment of the present invention.

FIG. 4 shows a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 shows a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a conventional technique.

FIG. 8 is a diagram showing a conventional technique.

[Explanation of symbols]

1. 1. P well region Element isolation regions 3, 3a, 3b, 31b. Gate insulating film 4, 4a, 4b, 41a, 41b, 42a, 42b, 4
3a. Gate electrodes 5a, 5b, 5c, 5d, 53a, 53b, 54a, 5
4b. N ⁺ region 6. 6. Internal power supply potential Vpp 7. GND potential Back gate potential Vbb 9, 9a, 9b, 10, 10a, 10b, 12, 13.
MOS capacitors 9c, 10c, 12a, 12b. Capacitor 11. Depletion layer 14. Storage node 15. Cell plate 16. Capacitor insulating film 17. Stack capacitor 18. Contact 31a. Interpoly insulating film 43b. Floating gates 50a, 50b. P ⁺ regions 51a, 51b, 51c, 51d, 52a, 52b. Impurity diffusion region 61. Vpp line

Claims (10)

[Claims] In a decoupling capacitor including first and second MOS capacitors connected in series between an internal power supply and GND, the first and second MOS capacitors are connected between the internal power supply and the GND. A semiconductor device to which a voltage lower than a voltage is applied. A first MOS capacitor connected in series between an internal power supply and GND;
The potential of the internal power supply is supplied to the first gate electrode forming the S capacitor, the first impurity diffusion region forming the first MOS capacitor, and the second gate electrode forming the second MOS capacitor And a semiconductor device having a decoupling capacitance, wherein the potential of the GND is supplied to a second impurity diffusion region constituting the second MOS capacitor. 3. A well region of a first conductivity type formed on a semiconductor substrate, and a first MO formed on the well region.
A first MOS capacitor including an S capacitor and a second MOS capacitor, wherein the first MOS capacitor is formed on a region to be a first channel region on the surface of the well region via a first gate insulating film; An electrode and a first impurity diffusion region of a second conductivity type formed in contact with the first channel region, and the second MOS capacitor becomes a second channel region on the surface of the well region A second gate electrode formed on the region via a second gate insulating film, and a second impurity diffusion region of a second conductivity type formed in contact with the second channel region; An electric potential of an internal power supply is supplied to the first gate electrode, the first impurity diffusion region is electrically connected to the second gate electrode, and a GND potential is supplied to the second impurity diffusion region. By doing the first Second MOS capacitor to said internal power supply - a semiconductor device having a decoupling capacitor, characterized in that arranged in series between the GND. 4. A MOS capacitor connected in series between an internal power supply and GND and a decoupling capacitance including a junction capacitance, a voltage smaller than a voltage between the internal power supply and the GND is applied to the MOS capacitor. A semiconductor device characterized by the above-mentioned. 5. A well region formed in a semiconductor substrate,
A gate electrode formed on the well region via a gate insulating film and supplied with a potential of an internal power supply; a depletion layer is formed in the well region by supplying a potential of the internal power supply to the gate electrode; A channel region, formed in the well region in contact with the channel region, including an impurity diffusion region of the same conductivity type as the well region and supplied with a potential of GND, between the internal power supply and the GND;
A first capacitor constituted by the gate electrode,
A semiconductor device having a decoupling capacitance, wherein a second capacitor constituted by the depletion layer is arranged in series. 6. A first MOS capacitor and a second MO capacitor.
A plurality of first gate electrodes and second gate electrodes constituting the S capacitor are respectively arranged side by side in the gate length direction, and the first gate electrode and the second gate electrode are alternately combed. 4. The semiconductor device according to claim 1, wherein the semiconductor device is arranged in a shape. 7. The semiconductor device according to claim 2, wherein one of the impurity diffusion regions is arranged at one end of the gate electrode in the gate length direction of one gate electrode. 13. The semiconductor device according to claim 1. 8. The first and second gate electrodes are disposed such that one end thereof is mounted on an element isolation region formed on the surface of the semiconductor substrate, and an impurity diffusion region is formed near the other end of the gate electrode. 3. The method according to claim 2, wherein
7. The semiconductor device according to claim 3. 9. A well region of a first conductivity type formed in a semiconductor substrate, a floating gate formed on a region to be a channel region of the well region via a gate insulating film, and a floating gate formed on the floating gate. A gate electrode formed through an interpoly insulating film having a thickness equal to or less than the thickness of the gate insulating film; and a second conductivity type impurity formed in contact with the channel region in the well region. A semiconductor device having a decoupling capacitance, including a diffusion region, wherein a potential of an internal power supply is supplied to the gate electrode, and a potential of GND is supplied to the impurity diffusion region. 10. A MOS capacitor formed on a semiconductor substrate, a stack capacitor formed on the MOS capacitor via an interlayer insulating film, and one electrode of a counter electrode forming the stack capacitor and the MOS capacitor
The gate electrode forming the capacitor is electrically connected, the potential of the internal power supply is supplied to the other electrode forming the stack capacitor, and the potential of GND is supplied to the impurity diffusion region forming the MOS capacitor. A semiconductor device having a decoupling capacitance, characterized in that an insulating film interposed between the electrodes has a thickness corresponding to a half or less of a thickness of a gate insulating film forming the MOS capacitor.