KR20000045457A - Repair device using latch - Google Patents

Abstract

PURPOSE: A repair device using a latch is provided to perform a repair operation by using an anti-fuse and a latch circuit. CONSTITUTION: A repair device using a latch comprises an anti-fuse block(1), a repair controller(3), and a normal column decoder(4). The anti-fuse block generates an anti-fuse output signal according to an anti-fuse control signal. The repair controller determines a normal operation and a repair operation by comparing the anti-fuse output signal with a pre-decoding address. The normal column decoder operates a normal column line in an active status according to a repair control signal. The repair device further comprises a data latch portion(6) for latching input data or outputting the latched data according to the repair control signal, a read enable signal, and a write enable signal.

Description

Repair device using latch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair apparatus for a semiconductor memory device, and more particularly, to a repair operation using an antifuse and a latch circuit, thereby improving repair efficiency, reducing waste of repair cells, and minimizing chip design area. It relates to a repair device of the device.

A repair apparatus using an antifuse which is generally used now is shown in FIG. 1.

This antifuse repair device is used to repair one-bit failures that often occur after a burn-in test on a package.

As shown in FIG. 1, the antifuse block 1 corresponding to a failing address is operated by antifuse control signals (high voltage, address, etc.), whereby the failing address is generated. The signal corresponding to is maintained as an anti-fuse output signal (anti-out) which is an output of the antifuse block 1.

During the operation of the chip, the repair control signal 3 outputs a repair control signal by comparing the anti-fuse output signal anti-out and the predecoding address predec-add, which is the output of the address predecoder 2, with the repair control unit 3. do.

If the normal address signal is input and the anti-fuse output signal anti-out and the predecoding address predec-add do not coincide, the repair control unit 3 generates a high level repair control signal fuse-out. The output is enabled to enable the normal column decoder 4, and the spare column decoder 5 is disabled to raise the normal column line and prevent the spare column line.

On the other hand, when the repair address is input and the anti-fuse output signal anti-out and the predecoding address predec-add coincide with each other, the repair controller 3 outputs a repair control signal having a low level repair-out. The normal column decoder 4 is disabled and the spare column decoder 5 is enabled to block the normal column line and to open the spare column line to write / read data to a repair cell connected to the spare column line.

However, in the above-described conventional repair apparatus, the repair control unit 3 which distinguishes the normal operation from the repair operation by comparing the anti-fuse output signal anti-out and the predecoding address prepred-add has a normal column line and a spare. There is a restriction that the layout should be as close as possible to the normal column decoder 4 and the spare column decoder 5 in order to match the enable and disable timing of the column line.

In addition, only one repair cell needs to be used to repair the One Bit Fail. In the existing Repair Scheme, a redundant column line or a redundant word line has to be floated, which wastes a lot of repair cells, thus reducing the number of repair cells that can be used on the wafer. have.

In addition, in such a scheme, if the repair cell itself becomes unstable, repair is not useful.

The present invention has been made to solve the above problems of the prior art, a repair device for a semiconductor memory device to increase the repair efficiency and minimize the repair area by repairing a cell in which a fail is generated by using a latch circuit rather than a repair cell The purpose is to provide.

The repair apparatus of the present invention for achieving the above object is an anti-fuse block for operating the anti-fuse control signal to generate an anti-fuse output signal;

An address predecoder for decoding the input address and outputting a predecoding address;

A repair controller which compares the anti-fuse output signal and a pre-decoding address to be input and outputs a repair control signal for determining a normal operation and a repair operation;

A repair apparatus for a semiconductor memory device including a normal column decoder configured to activate a normal column line in response to the repair control signal during a normal operation.

And a data latch means for latching input data during repair write and outputting the latched input data during repair read in response to the repair control signal, the read enable signal, and the write enable signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a repair relationship using the anti-fuse and the repair cell according to the prior art.

2 is a block diagram showing a repair relationship using an antifuse and a latch circuit according to an embodiment of the present invention.

3 is a detailed circuit diagram illustrating the data latch unit of FIG. 2.

<Description of the symbols for the main parts of the drawings>

1: Antifuse block 2: Address predecoder

3: repair control unit 4: normal column decoder

5: Spare column decoder 6: Data latch unit

6-1: Light / Lead Control Unit 6-2: Latch Unit

6-2-1: First switch section 6-2-2: Data storage section

6-2-3: 2nd switch part

Antifuse Control: Anti-fuse control signal anti-out: Anti-fuse output signal

fuse-out: Repair control signal

predec-add: predecoding address

r-en: Lead enable signal w-en: Write enable signal

repair-rd: Repair lead signal

repair-wrt: Repair light signal T1, T2: Transmission gate

2 shows a repair block diagram using a latch circuit according to an embodiment of the present invention, which is operated by an anti-fuse control signal to generate an anti-fuse output signal. A block 1, an address predecoder 2 for decoding the addresses input to the address pin and outputting a predecoding address (predec-add), and the input anti-out signal and the pre-decoding address. a repair control unit 3 which compares (predec-add) and outputs a repair control signal (fuse-out), and a normal column decoder that enables the normal column line by enabling the repair control signal (fuse-out) 4) and a data latch unit configured to read / write data during a repair operation by operating by the repair control signal fuse-out and the read enable signal r-en and the write enable signal w-en. 6) as It is composed.

FIG. 3 is a detailed circuit of the data latch unit 6 shown in FIG. 2, which is under the control of the repair control signal (fuse-out) and write enable signal (w-en) and lead enable. The light / read control unit 6-1 outputs the write and read signals during repair by the signal r-en, and is turned on during the repair write operation in response to the output signal of the write / read control unit 6-1. The input data is latched to the data storage unit 6-2-2 through the first switch unit 6-2-1, and the data is switched through the second switch unit 6-2-3 turned on during the repair read operation. It consists of a latch part 6-2 which outputs the stored data latched to the storage part 6-2-2.

The write / read control unit 6-1 performs a logical operation on a first inverter for inverting a repair control signal fuse-out, and an output and a read enable signal r-en of the first inverter IV1. The first NAND gate ND1 for outputting the repair read signal repair-rd, the output of the first inverter IV1 and the write enable signal w-en, and the repair write signal repair-wrt. ) Is configured as a second NAND gate ND2.

The latch unit 6-2 is turned on by a repair write signal repair-wrt, and includes a first switch unit 6-2-1 for transferring input data, and a first switch unit 6- 6 during repair write. A data storage unit 6-2-2 for latching the input data transferred from 2-1), and the data storage unit 6-2-2 is turned on by the repair read signal repair-rd at the time of repair read; 2nd switch part 6-2-3 which read-outs the input data latched by the (), and 6th inverter IV6 which inverts and outputs the output of the said 2nd switch part 6-2-3. do.

The first switch unit 6-2-1 has a second inverter IV2 for inverting the repair write signal repair-wrt and an NMOS type to which the output signal of the second inverter IV2 is applied to a gate. The first transmission gate T1 includes a PMOS transistor to which the repair write signal repair-wrt is applied to the transistor and the gate.

The data storage unit 6-2-2 inverts the fourth inverter IV4 for inverting and outputting the output signal of the first switch unit 6-2-1 and the output of the fourth inverter IV4. And a fifth inverter IV5 outputted to the fourth inverter IV4 input terminal.

The second switch unit 6-2-3 has a third inverter IV3 for inverting the repair read signal repair-rd and an NMOS type to which the output signal of the third inverter IV3 is applied to a gate. The second transmission gate T2 includes a PMOS transistor to which the repair read signal repair-rd is applied to the transistor and the gate.

An operation relationship of a repair circuit according to an embodiment of the present invention having the above configuration will be described with reference to FIGS. 2 and 3 as follows.

First, in the normal operation in which the normal address is input in FIG. 2, the repair control signal (fuse-out) becomes high to prevent the operation of the data latch unit 6, and the read enable signal of the normal column line and the normal path. (r-en) is enabled for normal operation.

That is, when the repair control signal fuse-out becomes high, the repair read signal repair-rd and the repair write signal repair-wrt of FIG. 3 become high, and the first switch unit 6-2-1 becomes high. ) And the second switch unit 6-2-3 are turned off so that data input / output to the data storage unit 6-2-2 does not occur, and the lead enable signal of the normal column line and the normal path ( r-en) is enabled for normal operation.

On the other hand, during a repair operation in which a repair address is input, the repair control signal (fuse-out) shown in FIG. 2 goes low to operate the data latch units 6-2 and 6.

In this case, the normal column line is also enabled, but since the read enable signal r-en of the normal pass is disabled, the normal data is not read.

That is, the repair control signal fuse-out becomes low so that the output of the first inverter IV1 of FIG. 3 is high.

Since the write enable signal w-en becomes high during the repair write operation, the repair write signal repair-wrt, which is the output of the second NAND gate ND2, becomes low, thereby causing the first switch unit 6-2-1 to become low. ) Is turned on and the input data is latched to the data storage 6-2-2.

During the repair read operation, since the read enable signal r-en becomes high, the repair read signal repair-rd, which is an output of the first NAND gate ND1, becomes low, thereby causing the second switch unit 6-2-3 to fail. ) Is turned on and the data latched in the data storage unit 6-2-2 is read out through the sixth inverter IV6.

As described above, since the present invention performs a repair operation using a latch circuit instead of a conventional repair cell, there is no need to float redundant column lines or redundant word lines, thereby preventing waste of the repair cell and improving repair efficiency on the wafer. It can increase the effect.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

An antifuse block operating on the antifuse control signal to generate an antifuse output signal; A repair controller which compares the anti-fuse output signal and a pre-decoding address to be input and outputs a repair control signal for determining a normal operation and a repair operation; A repair apparatus for a semiconductor memory device including a normal column decoder configured to activate a normal column line in response to the repair control signal during a normal operation. And data latch means for latching input data during repair write and outputting the latched input data during repair read in response to the repair control signal, the read enable signal, and the write enable signal. Repair device. The method of claim 1, The repair controller outputs a repair control signal indicating a repair operation when the anti-fuse output signal and the pre-decoding address match with each other. And a repair control signal for notifying a normal operation when the anti-fuse output signal and the pre-decoding address do not match. The method of claim 1, The data latch means enables the repair write signal at the time of repair and enables the repair read signal at the time of repair, in response to the write enable signal and the read enable signal being input under the control of the repair control signal. Repair device for semiconductor memory devices. The method of claim 1, The data latch means includes inverting means for inverting and outputting a repair control means; First calculation means for performing a logic operation on the inverted output and the read enable signal to output a repair read signal; And a second calculating means for logically operating the inverted output and the write enable signal to output a repair write signal. The method of claim 4, wherein And the first calculating means and the second calculating means have a NAND gate. The method of claim 1, The latch means may include first switch means that is turned on by the repair write signal and transfers input data during a repair operation; Data storage means for latching input data transmitted through the first switch means during repair writing; And a second switch means for reading out the stored data which is turned on by the repair read signal and latched to the data storage means during a repair read. The method of claim 6, And the first switch means and the second switch means comprise a transmission gate and an inverter composed of MOS transistors. The method of claim 6, The data storage means is a repair device of a semiconductor memory device, characterized in that it comprises an inverter.