KR20000045431A - Method for fabricating transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor is provided to improve device characteristic and reliability by forming a shallow drain/source junction region of a PMOS transistor using a high phase diffusion. CONSTITUTION: A method for fabricating a transistor comprises forming an isolation layer(15), an N-type well(13) and a P-type well(11) in a semiconductor substrate. A gate electrode consisting of a gate oxide layer and a conductive film is formed on the substrate. An N-type impurity junction region(21) of a low concentration is formed at the wells(11,13) by using the gate electrode as a mask. A diffusion barrier layer(23) is formed on a resultant structure. A first photoresist pattern is formed over the P-type well(11). A spacer is formed at both sidewalls of a gate electrode at the N-type well(13) by using an anisotropic etching method. After removing the first photoresist pattern, a BSG insulating layer(27) is formed on an entire surface of a resultant structure. A spacer(27) is formed at sidewalls of each gate electrode by etching the insulating layer by an anisotropic etching method. A second photoresist pattern is formed over the N-type well(13). An N-type source/drain junction region(31) is formed by implanting an impurity of a high concentration at the P-type well(11). A rapid thermal annealing is performed so as to form a P-type source/drain region(33) of a high concentration.

Description

Transistor Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and in particular, to enable high integration of a complementary metal oxide semiconductor (hereinafter referred to as CMOS) device in which a PMOS and an NMOS are provided on a semiconductor substrate. It relates to a technology that can improve the characteristics and reliability of the.

1A to 1C are cross-sectional views illustrating a transistor forming method of a semiconductor device according to the prior art, and illustrating a CMOS forming process.

First, an isolation layer 45 defining an active region is formed on the semiconductor substrate 100. Then, the enwell 43 is formed by performing an Enwell ion implantation process using an Enwell mask (not shown), a P-channel punch stop ion implantation process, an inter-enwell ion implantation process, and a P-channel field stop ion implantation process. do.

The Pwell 41 is formed by a Pwell ion implantation process using a Pwell mask (not shown), an inter-Pwell ion implantation process, an N-channel field stop ion implantation process, and an ion implantation process for regulating the N-channel threshold voltage. .

A gate electrode is formed on the semiconductor substrate 100 in a stacked structure of a gate oxide film 47 and a gate electrode conductor 49.

A low concentration impurity junction region 51 is formed in the enwell 53 and the pewell 51 of the semiconductor substrate 100 using the gate electrode as a mask. At this time, the low concentration of impurities are implanted with P31 ions. (FIG. 1A)

Next, an oxide film 52 is formed on the entire surface and anisotropically etched to form an oxide film spacer spacer on the sidewall of the gate electrode.

The first photoresist layer pattern 53 is formed on the enwell 43, and As35 ion, which is an en-type impurity, is injected into the pewell 41 at a high concentration by using the first photoresist layer pattern 53 as a mask. An N-type source / drain junction region 55 which is an impurity junction region is formed. (FIG. 1B)

Then, the first photoresist pattern 53 is removed, and a second photoresist pattern 57 is formed on the semiconductor substrate 100 by an exposure and development process using an Enwell mask (not shown). BF ₂ impurity, which is a target impurity, is ion-implanted into the enwell 43 to form a source / drain junction 59 having a high concentration impurity junction region.

In this case, the shaped source / drain junction region 59 formed in the enwell 43 is deeper than the n-type source / drain junction region 55 formed in the pewell 41. (FIG. 1C)

In a subsequent step, the second photoresist pattern 59 is used as a mask, and a subsequent step is performed to form a semiconductor device.

As described above, in the method of forming a transistor of a semiconductor device according to the related art, the depth of a high concentration of impurity junction regions formed in the enwell and the pewell is different, that is, the source / drain junction region formed on the enwell is formed on the pewell. It is formed deeper than the N-type source / drain junction region, which causes a short channel effect and a punch-through phenomenon. In addition, it is difficult to form a shallow junction required in a semiconductor device in which the source / drain junction region formed on the enwell is highly integrated, thereby degrading the characteristics and reliability of the semiconductor device and consequently making the semiconductor device highly integrated.

Therefore, in order to solve the problems of the prior art, the characteristics of a semiconductor device are formed by forming a shallow junction suitable for high integration of a semiconductor device by forming a source / drain junction region by a solid phase diffusion process, which is a diffusion process through a heat treatment process. And to provide a method for forming a transistor of a semiconductor device that can improve the reliability.

1A to 1C are cross-sectional views showing a transistor forming method of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a transistor forming method of a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11,41: P-well 13,43: N-well

15,45 device isolation film 17,47 gate oxide film

19,49: conductor for gate electrode

21,51: low concentration impurity junction region, LDD impurity junction region

23 diffusion barrier film 25, 53 first first photoresist film pattern

27: BSG insulating film 29, 57: second photosensitive film pattern

31,55: En-type source / drain junction region, High concentration of En-type impurity junction region

33,59: corrugated source / drain junction region, high concentration of impurity junction region

29: LDD impurity junction region 31: second photosensitive film pattern

32: source / drain junction area 33: pocket implant area

In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,

Forming a device isolation film, a pewell and an enwell on a semiconductor substrate,

Forming a gate electrode on the semiconductor substrate with a stacked structure of a gate insulating film and a conductor having a high concentration of N-type doped gate electrode;

Forming a low concentration Y-type impurity junction region on the semiconductor substrate using the semiconductor substrate upper structure as a mask;

Forming a diffusion barrier on the entire surface;

Forming a first photoresist pattern on the entire surface including the gate electrode by using an enwell mask;

Forming an diffusion barrier spacer on the sidewall of the gate electrode by anisotropically etching the diffusion barrier layer on the enwell using the first photoresist pattern as a mask;

Removing the first photoresist pattern and forming a BSG insulation spacer on the sidewall of the gate electrode, wherein a diffusion barrier is provided between the BSG insulation spacer of the pewell and the semiconductor substrate;

Forming an NMOS source / drain junction region of an NMOS by forming a second photoresist pattern on the enwell using a Pwell mask and implanting a high concentration of impurity ions into the pewell using the mask as a mask;

And rapidly forming the semiconductor substrate by diffusing impurities of the BSG insulating layer spacer on the top of the enwell to the semiconductor substrate by rapid thermal treatment of the semiconductor substrate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

First, an isolation layer 15 is formed to define an active region of a semiconductor substrate. Then, the enwell 13 is formed by performing an enwell ion implantation process using an enwell mask (not shown), an inter-channel punch stop ion implantation process, an inter-enwell ion implantation process, and a p-channel field stop ion implantation process. do. At this time, the P-channel punch stop ion implantation step is performed by injecting P31 ions with a dose of 2 to 3 E12 at an energy of 50 to 100 KeV.

Then, the Pwell 11 is formed by a Pwell ion implantation process using a Pwell mask (not shown), an inter-Pwell ion implantation process, an N-channel field stop ion implantation process, and an ion implantation process for regulating the N-channel threshold voltage. .

A gate electrode is formed on the semiconductor substrate in a stacked structure of a gate oxide film 17 and a conductor 19 for a gate electrode. In this case, the gate electrode conductor 19 is formed of polycrystalline silicon, polyside or silicide doped with a high concentration of en-type impurities.

A low concentration of the n-type impurity junction region 21 is formed in the enwell 13 and the pewell 11 of the semiconductor substrate using the gate electrode as a mask. In this case, P31 ions are used as the low concentration impurities. (FIG. 2A)

Next, a diffusion barrier 23 is formed on the entire surface of 100 to 1000 mm thick.

In this case, the diffusion barrier 23 is formed of an oxide film or a nitride film-based insulating film. The oxide film or the nitride film-based insulating film may be a silicon nitride film, a silicon oxide film, a medium temperature oxide film, a silicon oxynitride film, a silicon-rich oxide film, or the like. The oxide film or nitride film-based insulating film may be formed by chemical vapor deposition, physical vapor deposition, and thermal oxidation.

Next, the first photoresist layer pattern 25 is formed on the pewell 11 by an exposure and development process using an enwell mask (not shown). (FIG. 2B)

In addition, anisotropic etching of the diffusion barrier 23 using the first photoresist layer pattern 25 as a mask forms a spacer as a diffusion barrier 23 on the sidewall of the gate electrode on the N well 13.

Then, the first photosensitive film pattern 25 is removed. (FIG. 2C)

Then, a BSG insulating film 27 is formed on the entire surface at a constant thickness.

At this time, the BSG insulating film 27 is formed to a thickness of 500 ~ 2000Å. The BSG insulating film 27 is formed with a boron content of about 3 to 15 wt%. (FIG. 2D)

Next, the BSG insulating layer 27 is anisotropically etched to form a BSG insulating layer 27 spacer on the sidewall of the gate electrode. (FIG. 2E)

In addition, a second photoresist layer pattern 29 is formed by an exposure and development process using a Pwell mask (not shown) on the top of the Nwell 13, and a high concentration of impurities are implanted into the Pwell 11 of the semiconductor substrate. The N-type source / drain junction region 31 is formed.

At this time, the N-type source / drain junction region 31 is formed by injecting a dose of As ions 3 to 5 E15 with energy of 20 to 25 KeV. (FIG. 2F)

Next, the second photoresist layer pattern 29 is removed, and the semiconductor substrate is rapidly thermally treated to diffuse impurities in the spacer of the BSG insulating layer 27 formed on the sidewalls of the upper gate electrode of the enwell 13 to the enwell 13. A high concentration source / drain junction region 33 is formed. Here, the rapid heat treatment step is performed for 10 to 30 seconds in a vacuum atmosphere, nitrogen, oxygen, ammonia or hydrogen gas atmosphere, 900 ~ 1100 ℃ temperature.

In this case, the BSG insulating layer 27 spacer on the sidewall of the gate electrode formed on the Pwell 11 is provided with a diffusion barrier at the interface with the semiconductor substrate so that solid phase diffusion does not occur. Solid phase diffusion occurs only in the enwell 13 in which the diffusion barrier is not provided at the interface of the substrate. (Fig. 2g)

As described above, in the method of forming a transistor of the semiconductor device according to the present invention, the source / drain junction region of the PMOS transistor formed in the enwell is shallow by solid phase diffusion, thereby improving characteristics such as short channel effect and punch through. It is possible to improve the characteristics and reliability of the semiconductor device accordingly and to enable high integration of the semiconductor device.

Claims (9)

Forming a device isolation film, a pewell and an enwell on a semiconductor substrate, Forming a gate electrode on the semiconductor substrate with a stacked structure of a gate insulating film and a conductor having a high concentration of N-type doped gate electrode; Forming a low concentration Y-type impurity junction region on the semiconductor substrate using the semiconductor substrate upper structure as a mask; Forming a diffusion barrier on the entire surface; Forming a first photoresist pattern on the entire surface including the gate electrode by using an enwell mask; Forming an diffusion barrier spacer on the sidewall of the gate electrode by anisotropically etching the diffusion barrier layer on the enwell using the first photoresist pattern as a mask; Removing the first photoresist pattern and forming a BSG insulation spacer on the sidewall of the gate electrode, wherein a diffusion barrier is provided between the BSG insulation spacer of the pewell and the semiconductor substrate; Forming an NMOS source / drain junction region of an NMOS by forming a second photoresist pattern on the enwell using a Pwell mask and implanting a high concentration of impurity ions into the pewell using the mask as a mask; Forming a source / drain junction region of a PMOS by rapidly thermally treating the semiconductor substrate and diffusing impurities of the BSG insulating spacer on the top of the enwell to the semiconductor substrate. The method of claim 1, And wherein the low concentration impurity junction region is formed of P31 ions. The method of claim 1, The diffusion barrier is a transistor forming method of a semiconductor device, characterized in that formed in a thickness of 100 to 1000 kHz. The method of claim 1, The diffusion barrier layer is formed of an oxide film or a nitride film-based insulating film, such as a silicon nitride film, a silicon oxide film, a medium temperature oxide film, a silicon oxynitride film, a silicon-rich oxide film and the like. The method of claim 1, And said BSG insulating film is formed to a thickness of 500 to 2000 kHz. The method of claim 1, The BSG insulating film has a boron content of 3 to 15 wt%, the transistor forming method of a semiconductor device. The method of claim 1, And the N-type source / drain junction region is formed by implanting the dose of As ions 3 to 5 E15 with energy of 20 to 25 KeV. The method of claim 1, The rapid heat treatment process is a vacuum atmosphere, transistor formation method of a semiconductor device, characterized in that performed for 10 to 30 seconds at a temperature of 900 ~ 1100 ℃. The method of claim 1, The rapid heat treatment process is a transistor forming method of a semiconductor device, characterized in that carried out for 10 to 30 seconds in a nitrogen, oxygen, ammonia or hydrogen gas atmosphere, 900 ~ 1100 ℃ temperature.