KR20000045236A - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR20000045236A KR20000045236A KR1019980061794A KR19980061794A KR20000045236A KR 20000045236 A KR20000045236 A KR 20000045236A KR 1019980061794 A KR1019980061794 A KR 1019980061794A KR 19980061794 A KR19980061794 A KR 19980061794A KR 20000045236 A KR20000045236 A KR 20000045236A
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229920001903 high density polyethylene Polymers 0.000 claims description 2
- 239000004700 high-density polyethylene Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 22
- 238000009413 insulation Methods 0.000 abstract description 14
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 소자의 신뢰성을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving the reliability of the device.
고집적 DRAM(Dynamic Random Access Memory) 형성 시 비트 라인(Bit Line)과 활성 영역사이에 전기적으로 연결되도록 셀 플러그(Cell Plug) 공정을 진행한다.When forming a highly integrated dynamic random access memory (DRAM), a cell plug process is performed so as to be electrically connected between a bit line and an active region.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 제조 방법은 도 1a에서와 같이, 셀 영역과 주변 영역이 정의된 반도체 기판(11)상에 절연 막을 개재하며 캡 절연 막을 구비한 다수개의 워드 라인(Word Line)(13)을 형성한다.In the method of manufacturing a semiconductor device according to the related art, as illustrated in FIG. 1A, a plurality of word lines 13 are provided on the semiconductor substrate 11 on which a cell region and a peripheral region are defined and include a cap insulation layer. ).
상기 워드 라인(13)들을 포함한 반도체 기판(11)상에 산화 막(14)과 제 1 감광막을 형성한다.An oxide film 14 and a first photosensitive film are formed on the semiconductor substrate 11 including the word lines 13.
이어, 상기 제 1 감광막을 주변 영역에만 남도록 선택적으로 노광 및 현상하고, 상기 선택적으로 노광 및 현상된 상기 제 1 감광막을 마스크로 상기 셀 영역의 산화 막(14)을 에치 백(Etch Back)하여 상기 셀 영역의 각 워드 라인(13) 양측의 반도체 기판(11)상에 산화 막 측 벽(14a)을 형성한 후, 상기 제 1 감광막을 제거한다.Subsequently, the first photoresist layer is selectively exposed and developed so that only the peripheral region remains, and the oxide film 14 of the cell region is etched back using the selectively exposed and developed first photoresist layer as a mask. After forming the oxide film side wall 14a on the semiconductor substrate 11 on each side of each word line 13 in the cell region, the first photosensitive film is removed.
도 1b에서와 같이, 상기 워드 라인(13)들을 포함한 전면에 다결정 실리콘(15)을 형성한 후, 상기 다결정 실리콘(15)을 CMP(Chemical Mechanical Polishing)방법에 의해 평탄화 한다.As shown in FIG. 1B, after the polycrystalline silicon 15 is formed on the entire surface including the word lines 13, the polycrystalline silicon 15 is planarized by a chemical mechanical polishing (CMP) method.
도 1c에서와 같이, 상기 다결정 실리콘(15)을 포함한 전면에 제 2 감광막(16)을 도포 한 다음, 상기 제 2 감광막(16)을 셀 영역에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, the second photoresist film 16 is coated on the entire surface including the polycrystalline silicon 15, and then the second photoresist film 16 is selectively exposed and developed so as to remain only in the cell region.
도 1d에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(16)을 마스크로 상기 주변 영역의 다결정 실리콘(15)을 제거하여 상기 셀 영역에 플러그(Plug) 층(15a)을 형성한 후, 상기 제 3 감광막(16)을 제거한다.As shown in FIG. 1D, the polycrystalline silicon 15 in the peripheral region is removed using the selectively exposed and developed second photoresist layer 16 to form a plug layer 15a in the cell region. The third photosensitive film 16 is removed.
이때, 상기 주변 영역의 다결정 실리콘(15)의 식각 공정 시 잔류 층(17)이 발생한다.At this time, the residual layer 17 is generated during the etching process of the polycrystalline silicon 15 in the peripheral region.
그러나 종래의 반도체 소자의 제조 방법은 워드 라인의 캡 절연 막이 식각되지 않도록 하기 위해서 셀 플러그 형성용 다결정 실리콘의 평탄화 공정 시 충분히 식각하지 못하기 때문에, 셀 플러그 층의 형성 시 주변 영역의 산화 막을 포함한 워드 라인 양측에 다결정 실리콘이 잔류하여 전기적으로 쇼트(Short)가 발생되는 등 소자의 신뢰성을 저하시키는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, since the cap insulation film of the word line is not etched sufficiently during the planarization process of the polycrystalline silicon for forming the cell plug, the word including the oxide film in the peripheral region when the cell plug layer is formed. There is a problem in that the reliability of the device is deteriorated, such as polycrystalline silicon remaining on both sides of the line to electrically short.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 워드 라인의 캡 절연 막 상에 절연 막을 형성시킨 후 셀 플러그 형성용 다결정 실리콘의 평탄화 공정을 실시하므로 주변 영역에 다결정 실리콘의 잔류 층이 발생되지 않는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and since the insulating film is formed on the cap insulating film of the word line, the planarization process of the polycrystalline silicon for cell plug formation is performed so that no residual layer of polycrystalline silicon is generated in the peripheral region. Its purpose is to provide a method for manufacturing a semiconductor device.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31: 반도체 기판 33: 워드 라인31: semiconductor substrate 33: word line
34: 산화 막 34a: 산화 막 측 벽34: oxide film 34a: oxide film side wall
35: 질화 막 36: 제 2 감광막35: nitride film 36: second photosensitive film
37: 다결정 실리콘 37a: 플러그 층37: polycrystalline silicon 37a: plug layer
38: 제 3 감광막38: third photosensitive film
본 발명의 반도체 소자의 제조 방법은 셀 영역과 주변 영역이 정의된 기판을 마련하는 단계, 상기 기판 상에 절연 막을 개재하며 캡 절연 막을 구비한 다수개의 워드 라인을 형성하는 단계, 상기 셀 영역의 각 워드 라인 양측의 기판 상에 제 1 절연 막 측 벽을 그리고 상기 워드 라인들을 포함한 주변 영역의 기판 상에 제 1 절연 막을 형성하는 단계, 상기 셀 영역의 각 워드 라인 상에 제 2 절연 막을 그리고 상기 주변 영역의 제 1 절연 막 상에 제 2 절연 막을 형성하는 단계, 전면에 도전 체를 형성하는 단계, 상기 도전 체를 상기 제 2 절연막이 노출되도록 평탄화하여 상기 셀 영역에 셀 플러그를 형성하는 단계, 상기 노출된 제 2 절연 막을 식각하는 단계와, 상기 주변 영역의 도전 체와 잔류 제 2 절연 막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention, the method comprises: providing a substrate in which a cell region and a peripheral region are defined, forming a plurality of word lines on the substrate, the plurality of word lines having a cap insulating layer interposed therebetween, and each cell region of the cell region. Forming a first insulating film side wall on the substrate on both sides of the word line and a first insulating film on the substrate in the peripheral region including the word lines, a second insulating film on each word line in the cell region and the peripheral Forming a second insulating film on the first insulating film in the region, forming a conductor on the front surface, and planarizing the conductor to expose the second insulating film to form a cell plug in the cell region, the Etching the exposed second insulating film, and removing the conductor and the remaining second insulating film in the peripheral region. The.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
도 2a 내지 도 2f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명의 실시 예에 따른 반도체 소자의 제조 방법은 도 2a에서와 같이, 셀 영역과 주변 영역이 정의된 반도체 기판(31)상에 절연 막을 개재하며 캡 절연 막을 구비한 다수개의 워드 라인(33)을 형성한다.In the method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention, as shown in FIG. 2A, a plurality of word lines 33 are provided on the semiconductor substrate 31 on which a cell region and a peripheral region are defined and include a cap insulation layer. To form.
상기 워드 라인(33)들을 포함한 반도체 기판(31)상에 산화 막(34)과 제 1 감광막을 형성한다.An oxide film 34 and a first photosensitive film are formed on the semiconductor substrate 31 including the word lines 33.
이어, 상기 제 1 감광막을 주변 영역에만 남도록 선택적으로 노광 및 현상하고, 상기 선택적으로 노광 및 현상된 상기 제 1 감광막을 마스크로 상기 셀 영역의 산화 막(34)을 에치 백하여 상기 셀 영역의 각 워드 라인(33) 양측의 반도체 기판(31)상에 산화 막 측 벽(34a)을 형성한 후, 상기 제 1 감광막을 제거한다.Subsequently, selectively exposing and developing the first photoresist film so as to remain only in the peripheral region, and etching back the oxide film 34 of the cell region using the selectively exposed and developed first photoresist film as a mask. After the oxide film side wall 34a is formed on the semiconductor substrate 31 on both sides of the word line 33, the first photosensitive film is removed.
도 2b에서와 같이, 상기 워드 라인(33)들을 포함한 반도체 기판(31)상에 질화 막(35)과 제 2 감광막(36)을 형성한 후, 상기 제 2 감광막(36)을 플러그 층이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2B, after the nitride film 35 and the second photosensitive film 36 are formed on the semiconductor substrate 31 including the word lines 33, the plug layer is formed on the second photosensitive film 36. It is selectively exposed and developed to be removed only in the area to be removed.
이때, 상기 워드 라인(33)의 캡 절연 막이 산화 막이면 상기와 같이 질화 막(35)을 형성하고 그 반대로 상기 워드 라인(33)의 캡 절연 막이 질화 막이면 상기 질화 막(35) 대신에 산화 막을 형성한다.At this time, if the cap insulating film of the word line 33 is an oxide film, the nitride film 35 is formed as described above. On the contrary, if the cap insulating film of the word line 33 is a nitride film, the oxide film is oxidized instead of the nitride film 35. To form a film.
그리고, 상기 질화 막(35)을 인산 용액으로 습식식각할 수 있는 두께로 형성한다.Then, the nitride film 35 is formed to a thickness that can be wet etched with a phosphoric acid solution.
그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(36)을 마스크로 상기 질화 막(35)을 선택적으로 식각한다.The nitride film 35 is selectively etched using the selectively exposed and developed second photosensitive film 36 as a mask.
도 2c에서와 같이, 상기 제 2 감광막(36)을 제거하고, 상기 질화 막(35)을 포함한 전면에 다결정 실리콘(37)을 형성한 후, 상기 다결정 실리콘(37)을 CMP 방법에 의해 평탄화 한다.As shown in FIG. 2C, the second photoresist film 36 is removed, the polycrystalline silicon 37 is formed on the entire surface including the nitride film 35, and the polycrystalline silicon 37 is planarized by the CMP method. .
이때, 플라즈마(Plasma)내 이온농도와 이온에너지를 의존적으로 조절하는 식각장비인 RIE(Reactive Ion Etcher) 또는 MERIE(Magnetically Enhanced Reactive Ion Etcher) 그 외 식각장비인 플라즈마 내 이온농도와 이온에너지를 의존적으로 혹은 독립적으로 조절하는 HDPE(High Density Plasma Etcher)를 사용하여 상기 다결정 실리콘(37)을 평탄화 한다.In this case, depending on the ion concentration and ion energy in the plasma, which is an etching equipment for controlling the ion concentration and ion energy in the plasma depending on RIE or Magnetically Enhanced Reactive Ion Etcher (MERIE), Alternatively, the polycrystalline silicon 37 is planarized by using independently controlled high density plasma plasma (HDPE).
그리고, 상기 워드 라인(33)의 캡 절연 막이 적게 밀링(Milling)되면서 상기 질화 막(35)이 노출되도록 상기 다결정 실리콘(37)의 평탄화 공정을 충분히 진행한다.Then, the planarization process of the polycrystalline silicon 37 is sufficiently performed so that the cap insulation film of the word line 33 is milled with less milling.
도 2d에서와 같이, 상기 다결정 실리콘(37)을 마스크로 상기 노출된 질화 막(35)을 인산 용액에 의해 스핀(Spin)의 식각 방법으로 습식식각한다.As shown in FIG. 2D, the exposed nitride film 35 is wet-etched by spin etching with a phosphoric acid solution using the polycrystalline silicon 37 as a mask.
이때, 상기 질화 막(35) 대신에 산화 막을 형성한 경우에는 산화 막을 BOE(Buffered Oxide Etcher) 용액에 의해 습식식각한다.In this case, when an oxide film is formed instead of the nitride film 35, the oxide film is wet-etched by a BOE (Buffered Oxide Etcher) solution.
도 2e에서와 같이, 상기 다결정 실리콘(37)을 포함한 전면에 제 3 감광막(38)을 도포한 다음, 상기 제 3 감광막(38)을 셀 영역에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 2E, the third photoresist film 38 is coated on the entire surface including the polycrystalline silicon 37, and then the third photoresist film 38 is selectively exposed and developed so as to remain only in the cell region.
도 2f에서와 같이, 상기 선택적으로 노광 및 현상된 제 3 감광막(38)을 마스크로 상기 주변 영역의 다결정 실리콘(37)과 잔류 질화 막(35)을 제거하여 상기 셀 영역에 플러그 층(37a)을 형성한 후, 상기 제 3 감광막(38)을 제거한다.As shown in FIG. 2F, the polycrystalline silicon 37 and the residual nitride film 35 in the peripheral region are removed by using the selectively exposed and developed third photoresist film 38 as a mask, and the plug layer 37a is applied to the cell region. After forming, the third photosensitive film 38 is removed.
본 발명의 반도체 소자의 제조 방법은 워드 라인의 캡 절연 막 상에 절연 막을 형성시킨 후 셀 플러그 형성용 다결정 실리콘의 평탄화 공정을 실시하므로, 셀 플러그 형성용 다결정 실리콘을 충분히 식각하고 주변 영역의 다결정 실리콘과 잔류 절연 막을 제거하기 때문에 셀 플러그 층의 형성 시 주변 영역에 다결정 실리콘의 잔류 층이 발생되지 않아 소자의 신뢰성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, since the insulating film is formed on the cap insulating film of the word line and then the planarization process of the polycrystalline silicon for cell plug formation is performed, the polycrystalline silicon for cell plug formation is sufficiently etched and the polycrystalline silicon in the peripheral region Since the residual insulating film is removed, a residual layer of polycrystalline silicon is not generated in the peripheral region when the cell plug layer is formed, thereby improving the reliability of the device.
Claims (7)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100382541B1 (en) * | 2000-09-21 | 2003-05-01 | 주식회사 하이닉스반도체 | Method for forming plug of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100382541B1 (en) * | 2000-09-21 | 2003-05-01 | 주식회사 하이닉스반도체 | Method for forming plug of semiconductor device |
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