KR20000042844A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20000042844A KR20000042844A KR1019980059136A KR19980059136A KR20000042844A KR 20000042844 A KR20000042844 A KR 20000042844A KR 1019980059136 A KR1019980059136 A KR 1019980059136A KR 19980059136 A KR19980059136 A KR 19980059136A KR 20000042844 A KR20000042844 A KR 20000042844A
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- schottky metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는 단채널 및 얕은 접합을 갖는 모스 트랜지스터에 접합 누설 전류를 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a junction leakage current in a MOS transistor having a short channel and a shallow junction.
현재의 고집적 소자의 유효 채널 길이의 감소화와 더불어 소자의 수직 구조, 즉 접합 깊이의 감소 또한 필연적으로 요구되게 되었으며, 단채널에 의한 핫 캐리어(hot carrier)들이 다량으로 발생되어, 고집적 소자를 구현하는데 얕은 접합의 트랜지스터 형성은 필연적으로 요구되었다.In addition to the reduction of the effective channel length of the current high-density device, the vertical structure of the device, that is, the reduction of the junction depth is also inevitably required, and a large amount of hot carriers are generated by short channels, thereby realizing a high-integration device The formation of transistors with shallow junctions was inevitably required.
예를 들어, 얕은 접합은 모스(MOS: metal oxide silicon) 트랜지스터의 채널 길이가 0.5㎛ 이하로 형성되면, 접합 영역의 깊이는 150nm 이하로 구성되어야 하고, 이러한 얕은 접합을 형성하기 위하여는, 접합 영역을 형성하기 위한 이온 주입시 에너지 투사 범위를 조절하고, 단시간 어닐링 공정을 진행하여야 한다.For example, in a shallow junction, when the channel length of a metal oxide silicon (MOS) transistor is formed to be 0.5 μm or less, the depth of the junction region should be 150 nm or less, and in order to form such a shallow junction, the junction region During the implantation of ions to form energy, the energy projection range must be adjusted and a short time annealing process should be performed.
도 1은 얕은 접합을 갖는 종래의 모스 트랜지스터를 개략적으로 나타낸 도면이다. 도면을 참조하여, 불순물이 도핑된 실리콘 기판(1)에 게이트 절연막(2)을 형성한다음, 그 상부에 게이트 전극(3)을 공지된 방법으로 형성한다. 그리고 난다음, 게이트 전극(3)으로 부터 노출된 실리콘 기판(1) 영역에 비교적 낮은 에너지로 저농도 불순물을 이온 주입하여, 저농도 불순물 영역(4)을 형성한다. 이어서, 게이트 전극(3)의 양측벽에 스페이서(5)를 공지의 방법으로 형성하고, 이 스페이서(5) 및 게이트 전극(3)을 마스크로 하여, 노출된 실리콘 기판(1)에 고농도 불순물을 이온 주입하여 고농도 불순물 영역(6)을 형성한다. 이때, 고농도 불순물 이온도 마찬가지로 낮은 에너지로서 이온주입됨이 바람직하다. 그다음에, 실리콘 기판(1) 상부에 층간 절연막(7)을 형성한다음, 고농도 불순물 영역(6)이 노출되도록 층간 절연막(7)을 식각하여 콘택홀(h)을 형성한다. 그후, 노출된 고농도 불순물 영역(6)과 콘택되도록 금속 배선(8)을 형성한다.1 is a schematic view of a conventional MOS transistor having a shallow junction. Referring to the drawings, a gate insulating film 2 is formed on a silicon substrate 1 doped with impurities, and then a gate electrode 3 is formed thereon by a known method. Then, low concentration impurity regions are ion-implanted with relatively low energy into the silicon substrate 1 region exposed from the gate electrode 3 to form the low concentration impurity regions 4. Subsequently, spacers 5 are formed on both side walls of the gate electrode 3 by a known method, and the high concentration impurity is applied to the exposed silicon substrate 1 by using the spacer 5 and the gate electrode 3 as a mask. Ion implantation forms the highly concentrated impurity region 6. At this time, high concentration impurity ions are preferably implanted with low energy as well. Then, the interlayer insulating film 7 is formed on the silicon substrate 1, and then the interlayer insulating film 7 is etched to expose the high concentration impurity region 6 to form the contact hole h. Thereafter, the metal wiring 8 is formed to be in contact with the exposed high concentration impurity region 6.
그러나, 상기 콘택홀(h)을 형성하는 과정에서, 셀들이 밀집되어 있는 영역은 셀들이 드물게 배치된 영역보다 상대적으로 식각 속도가 느리기 때문에, 접합 영역을 노출시키기 위하여는 정하여진 시간보다 오버 에치(over etch)를 실시하여야 한다.However, in the process of forming the contact hole (h), the area where the cells are densely etched is slower than the area where the cells are rarely disposed, so to expose the junction area, the over-etching time is determined. over etch).
이때, 층간 절연막과 실리콘 기판간의 식각 선택비가 그리 크지 않으므로, 층간 절연막을 식각하는 가운데 접합 영역 즉, 고농도 불순물 영역(6)의 표면이 일부 제거된다. 이로 인하여, 모스 트랜지스터에 접합 누설 전류가 발생된다. 여기서, 미설명 부호 "a"는 접합 영역이 식각된 부분을 나타낸다.At this time, since the etching selectivity between the interlayer insulating film and the silicon substrate is not so large, the surface of the junction region, that is, the highly concentrated impurity region 6, is partially removed while the interlayer insulating film is etched. As a result, a junction leakage current is generated in the MOS transistor. Here, reference numeral "a" represents a portion where the junction region is etched.
이러한 문제점을 해결하기 위하여, 종래의 다른 방법으로는, 층간 절연막과 실리콘 기판간의 식각 선택비를 크게하는 방법과, 플러그 이온을 주입하는 공정등이 제안되었다.In order to solve this problem, as another conventional method, a method of increasing the etching selectivity between the interlayer insulating film and the silicon substrate, a step of implanting plug ions, and the like have been proposed.
여기서, 상기 층간 절연막과 실리콘 기판간의 식각 선택비를 증대시키는 방법은 새로운 장비를 구입하여야 한다는 문제점 있고, 플러그 이온을 주입하는 부분은, 소오스, 드레인 영역이 노출되도록 마스크를 형성하는 단계와, 플러그 이온을 주입하는 단계와, 주입된 이온을 어닐링하여 활성화시키는 단계 및 마스크를 제거하는 단계등 다수번의 공정이 요구된다는 문제점이 있다.Here, the method of increasing the etching selectivity between the interlayer insulating film and the silicon substrate has a problem that a new equipment must be purchased, and the plug ion implantation part includes forming a mask so that the source and drain regions are exposed; There is a problem in that a plurality of processes are required, such as the step of injecting, annealing and activating the implanted ions, and removing the mask.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 추가 장비의 구입 및 다수번의 공정없이, 접합 누설 전류를 방지할 수 있는 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a junction leakage current without the need for purchasing additional equipment and a plurality of steps.
도 1은 종래의 모스 트랜지스터의 단면도.1 is a cross-sectional view of a conventional MOS transistor.
도 2는 본 발명에 따른 모스 트랜지스터의 단면도.2 is a cross-sectional view of a MOS transistor according to the present invention.
도 3은 원자 번호에 대한 일함수를 나타낸 그래프3 is a graph showing the work function for atomic number
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 - 실리콘 기판 10a - P웰10-Silicon substrate 10a-P well
12 - 게이트 절연막 13 - 게이트 전극12-gate insulating film 13-gate electrode
14 - 저농도 불순물 영역 15 - 스페이서14-low concentration impurity region 15-spacer
16 - 고농도 불순물 영역 17 - 층간 절연막16-high concentration impurity region 17-interlayer insulating film
18 - 쇼트키 금속막 19 - 소오스, 드레인 전극 배선18-Schottky metal film 19-Source, drain electrode wiring
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 본 발명은 소정의 제 1 전도 타입의 웰을 포함하는 실리콘 기판에 게이트 절연막을 포함하는 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 제 1 전도웰에 제 2 전도 타입의 소오스, 드레인 영역을 형성하는 단계와, 상기 실리콘 기판 상부에 층간 절연막을 형성하는 단계와, 상기 소오스, 드레인 영역 하부의 제 1 전도 타입 웰이 노출되도록 층간 절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀 저면 및 내벽에 쇼트키 금속막을 형성하는 단계, 및 상기 각각 콘택홀 내의 쇼트키 금속막 상부에 소오스, 드레인 전극을 형성하는 단계를 포함한다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, the present invention comprises the steps of forming a gate electrode comprising a gate insulating film on a silicon substrate comprising a well of a first conductivity type; Forming a second conductive type source and drain region in the first conductive wells at both sides of the gate electrode, forming an interlayer insulating layer on the silicon substrate, and forming a first conductive type well under the source and drain regions Forming a contact hole by etching the interlayer insulating layer to expose the insulating layer, forming a schottky metal film on the bottom and inner walls of the contact hole, and forming a source and a drain electrode on the schottky metal film in the contact hole, respectively. Steps.
또한, 상기 제 1 전도 타입은 P 타입이고, 제 2 전도 타입은 N 타입이면, 쇼트키 금속막은 실리콘 보다 일함수가 작으면서, 일함수 차이가 큰 금속막 예를들어, 리튬막, 나트륨막 또는 리튬-철 합금막으로 형성한다.Further, when the first conductivity type is P type and the second conductivity type is N type, the Schottky metal film has a lower work function than silicon and has a large work function difference, for example, a lithium film, a sodium film or It is formed of a lithium-iron alloy film.
한편, 상기 제 1 전도 타입은 N 타입이고, 제 2 전도 타입은 P 타입이면, 상기 쇼트키 금속막은 실리콘보다 일함수가 크면서, 그 차이가 큰 금속막 예를들어, 백금막을 사용한다.On the other hand, when the first conduction type is N type and the second conduction type is P type, the Schottky metal film has a larger work function than silicon and a metal film having a large difference is used, for example, a platinum film.
본 발명에 의하면, 모스 트랜지스터의 접합 영역을 노출시키는 콘택홀 형성시, 접합 영역 저면의 웰 영역이 노출될 수 있도록 콘택홀을 형성하고, 콘택홀 내벽 및 저면에 실리콘과 쇼트키 다이오드를 형성할 수 있는 금속막을 피복한다음, 소오스, 드레인 전극을 형성한다.According to the present invention, when forming a contact hole exposing a junction region of a MOS transistor, a contact hole may be formed to expose a well region of the bottom of the junction region, and silicon and a Schottky diode may be formed on the inner wall and the bottom of the contact hole. The metal film is coated to form a source and a drain electrode.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2는 본 발명에 따른 모스 트랜지스터의 단면도이고, 도 3은 원자 번호에 대한 일함수를 나타낸 그래프이다. 참고로, 본 실시예에서는 N모스 트랜지스터를 예를들어 설명하도록 한다.2 is a cross-sectional view of a MOS transistor according to the present invention, and FIG. 3 is a graph showing a work function with respect to atomic number. For reference, in the present embodiment, an NMOS transistor will be described as an example.
도 2를 참조하여, 불순물이 도핑된 예를들어 P웰(10a)이 실리콘 기판(10)에 게이트 절연막(12)을 형성한다음, 그 상부에 게이트 전극(13)을 공지된 방법으로 형성한다. 그리고 난 다음, 게이트 전극(13)으로 부터 노출된 실리콘 기판(10) 영역에 비교적 낮은 에너지로 저농도 N형 불순물을 이온 주입하여, 저농도 불순물 영역(14)을 형성한다. 이어서, 게이트 전극(13)의 양측벽에 스페이서(15)를 공지의 방법으로 형성하고, 이 스페이서(15) 및 게이트 전극(13)을 마스크로 하여, 노출된 실리콘 기판(11)에 고농도 N형 불순물을 이온 주입하여 고농도 불순물 영역(16) 즉, 소오스, 드레인 영역을 형성한다. 이때, 고농도 불순물 이온도 마찬가지로 낮은 에너지로서 이온주입함이 바람직하다. 그다음에, 실리콘 기판(10) 상부에 층간 절연막(17)을 형성한다. 그후, 층간 절연막(17) 및 고농도 불순물 영역(6)의 소정 부분을 식각하여, 고농도 불순물 영역(6) 하단의 P웰 영역(10a)이 노출되도록 콘택홀(H)을 형성한다.Referring to FIG. 2, for example, a P well 10a doped with an impurity forms a gate insulating film 12 on a silicon substrate 10, and then a gate electrode 13 is formed thereon by a known method. . Thereafter, low concentration impurity regions 14 are formed by ion implanting low concentration N-type impurities with relatively low energy into the silicon substrate 10 region exposed from the gate electrode 13. Subsequently, spacers 15 are formed on both sidewalls of the gate electrode 13 by a known method, and the spacer 15 and the gate electrode 13 are used as masks, and a high concentration N type is exposed on the exposed silicon substrate 11. An impurity is implanted to form a high concentration impurity region 16, that is, a source and a drain region. At this time, high concentration impurity ions are preferably implanted with low energy as well. Next, an interlayer insulating film 17 is formed over the silicon substrate 10. Thereafter, predetermined portions of the interlayer insulating film 17 and the high concentration impurity region 6 are etched to form a contact hole H such that the P well region 10a at the lower end of the high concentration impurity region 6 is exposed.
그리고나서, 콘택홀(H) 저면과 쇼트키(shorttky) 다이오드를 형성하는 쇼트키 금속막(18)을 증착한다. 이때, 쇼트키 금속막(18)으로는 실리콘과 일함수 차이가 큰 물질로 형성함이 바람직하고, 예를들어, N모스 트랜지스터인 경우(P 웰과 접촉되는 경우)에는 실리콘 보다 일함수가 작은 금속막을 선택하고, P모스 트랜지스터인 경우(N 웰과 접촉되는 경우), 실리콘보다 일함수가 큰 금속막을 선택한다.Then, a Schottky metal film 18 is formed which forms the bottom surface of the contact hole H and a schottky diode. At this time, the Schottky metal film 18 is preferably formed of a material having a large difference in work function from silicon. For example, in the case of an NMOS transistor (in contact with a P well), the work function is smaller than that of silicon. A metal film is selected, and in the case of a P-MOS transistor (in contact with the N well), a metal film having a work function larger than silicon is selected.
여기서, 도 3은 원자 번호에 대한 일함수값을 나타낸 그래프로서, 본 실시예에서는 접합 영역(16)이 N형이므로, 실리콘보다 일함수가 작으며, 일함수의 차이가 큰 리튬막, 나트륨막, 리튬-철 합금막을 사용하고, P모스 트랜지스터의 경우에는 실리콘 보다 일함수가 크며, 그 차이 또한 큰 백금막(Pt)을 이용할 수 있다. 그리고나서, 쇼트키 금속막(18) 표면에 도전층을 증착하고, 소정 부분 패터닝하여 소오스, 드레인 전극(19)을 형성한다.3 is a graph showing work function values for atomic number. In this embodiment, since the junction region 16 is N-type, a lithium film and a sodium film having a lower work function than silicon and having a large work function difference are shown. , A lithium-iron alloy film is used, and in the case of the PMOS transistor, a platinum film Pt having a larger work function than silicon and having a large difference can also be used. Then, a conductive layer is deposited on the surface of the Schottky metal film 18, and predetermined portions are patterned to form the source and drain electrodes 19.
이와같이, N모스 트랜지스터에서는 P웰(10a)이 노출된 콘택홀내에 반도체 기판을 구성하는 실리콘의 일함수보다 작은 일함수를 갖는 쇼트키 금속막(17)이 형성되면, 쇼트키 금속막(18)의 일함수가 노출된 P웰(10a)의 페르미 에너지 준위(fermi energy level)보다 높게되어, 쇼트키 금속막(18)과 P웰(10a) 사이에는 쇼트키 접합이 형성된다. 그러면, 소오스, 드레인 전극(19)을 통하여 소정의 바이어스가 인가되면, 쇼트키 금속막(18)과 P웰(10a) 사이에 페르미 에너지 차이에 의하여 캐리어들이 이동하게 된다.As described above, in the N-MOS transistor, when the Schottky metal film 17 having a work function smaller than that of silicon constituting the semiconductor substrate is formed in the contact hole where the P well 10a is exposed, the Schottky metal film 18 is formed. The work function of becomes higher than the fermi energy level of the exposed P well 10a, and a Schottky junction is formed between the Schottky metal film 18 and the P well 10a. Then, when a predetermined bias is applied through the source and drain electrodes 19, carriers are moved by the Fermi energy difference between the Schottky metal film 18 and the P well 10a.
이때, 전류 특성을 식 1.1과 식 1.2에 나타내었다.At this time, the current characteristics are shown in Equations 1.1 and 1.2.
J = Jst[exp(-qV/kT)-1]---------(식1.1)J = Jst [exp (-qV / kT) -1] --------- (Equation 1.1)
Jst = A*T2exp(-qΦBp/kT)---------(식1.2)Jst = A * T 2 exp (-qΦ Bp / kT) --------- (Equation 1.2)
여기서, Jst는 역방향 누설 전류이고, V는 바이어스 전압이고, kT는 열 에너지이고, A*는 콘택 면적과 관련된 파라미터이고, ΦBp는 금속과 P웰 사이의 페르미 에너지 차이이다.Where Jst is the reverse leakage current, V is the bias voltage, kT is the thermal energy, A * is the parameter related to the contact area, and Φ Bp is the Fermi energy difference between the metal and the P well.
상기 식들에 의하면, 순방향 바이어스(V>0)가 인가될 때, 전류가 지수함수적으로 감소되어 역방향 특성을 갖게되고, 역방향 누설 전류(Jst)는 페르미 에너지 차이(ΦBp)가 클수록 지수함수적으로 줄게된다.According to the above equations, when forward bias (V> 0) is applied, the current decreases exponentially to have a reverse characteristic, and the reverse leakage current (Jst) is exponentially larger as the Fermi energy difference (Φ Bp ) is larger. Will give
따라서, P웰(10a)의 페르미 에너지와 차이가 큰 일함수를 갖는 금속막을 쇼트키 금속막(17)으로 사용하면, P웰(10a)이 노출되도록 콘택홀을 형성하여도 누설 전류가 거의 발생되지 않는다.Therefore, when a metal film having a work function having a large difference from the Fermi energy of the P well 10a is used as the Schottky metal film 17, even if a contact hole is formed so that the P well 10a is exposed, leakage current almost occurs. It doesn't work.
또한, 콘택홀을 형성하기 위한 식각 공정시, P웰(10a)까지 노출되도록 충분히 식각하므로써, 공정이 용이하여 진다.In addition, during the etching process for forming the contact hole, the etching is sufficiently performed so as to expose the P well 10a, thereby facilitating the process.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 모스 트랜지스터의 소오스, 드레인 영역을 노출시키는 콘택홀 형성시, 소오스, 드레인 영역 저면의 웰 영역이 노출될 수 있도록 콘택홀을 형성하고, 콘택홀 내벽 및 저면에 실리콘과 쇼트키 다이오드를 형성할 수 있는 쇼트키 금속막을 피복한다음, 소오스, 드레인 전극을 형성한다.As described in detail above, according to the present invention, when forming a contact hole for exposing a source and a drain region of a MOS transistor, a contact hole is formed to expose the well region of the bottom of the source and drain regions, and the contact hole inner wall And a Schottky metal film capable of forming silicon and a Schottky diode on the bottom, and then a source and a drain electrode are formed.
이에따라, 소오스, 드레인 영역이 콘택홀 형성시 유실되더라도, 노출된 기판과 쇼트키 금속막 사이에 쇼트키 다이오드가 형성되므로써, 전압 인가시 웰 부분과 콘택되는 면에서는 누설 전류가 거의 발생되지 않는다.As a result, even when the source and drain regions are lost during the formation of the contact hole, a Schottky diode is formed between the exposed substrate and the Schottky metal film, so that leakage current is hardly generated in contact with the well portion during voltage application.
따라서, 추가되는 장비 구입 및 다수번의 공정이 블필요하게 되고, 누설 전류를 방지할 수 있다.Thus, additional equipment purchases and a number of steps are unnecessary and leakage currents can be prevented.
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