KR20000041590A - Method for manufacturing semiconductor device - Google Patents
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- KR20000041590A KR20000041590A KR1019980057523A KR19980057523A KR20000041590A KR 20000041590 A KR20000041590 A KR 20000041590A KR 1019980057523 A KR1019980057523 A KR 1019980057523A KR 19980057523 A KR19980057523 A KR 19980057523A KR 20000041590 A KR20000041590 A KR 20000041590A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
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Abstract
Description
본 발명은 에스.티.아이(Shallow Trench Isolation 이하, STI)에 관한 것으로, 특히 트랜치내의 갭필(Gap Fill) 특성을 향상시키도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to STI (Shallow Trench Isolation), and more particularly to a method of manufacturing a semiconductor device to improve gap fill characteristics in a trench.
일반적으로, 반도체 장치의 고집적화에 따라 반도체기판 상에 형성되는 개개의 소자 크기가 축소될뿐만 아니라 개개의 소자를 전기적으로 분리시키는 소자분리영역의 크기도 점차 서브-마이크론(sub-micron)급까지 축소되고 있다. 그에 따라, 반도체 소자의 고집적도와 고성능을 충족시킬 수 있는 미세 패턴이 요구되었으며, 이에 따른 소자분리 형성 방법으로 LOCOS, 폴리-버퍼드(Poly-buffered) LOCOS, STI 등이 적용되기 시작하였다.In general, as the integration of semiconductor devices increases, not only the size of individual devices formed on the semiconductor substrate is reduced, but also the size of the device isolation region for electrically separating the individual devices is gradually reduced to sub-micron level. It is becoming. Accordingly, a fine pattern capable of satisfying high integration and high performance of semiconductor devices has been required, and LOCOS, poly-buffered LOCOS, and STI have begun to be applied as a method of forming device isolation.
이러한 소자분리 형성방법 중에 반도체기판의 비활성영역에 세미-리세스(semi-recess)된 필드산화막을 형성하는 로코스(LOCOS)법은 버즈빅(bird'beak)이 크게 발생하여 미세 패턴에서의 소자분리가 어렵게 된다.Among the device isolation formation methods, the LOCOS method of forming a semi-recessed field oxide film in an inactive region of a semiconductor substrate has a large bird'beak, and thus a device in a fine pattern. It becomes difficult to separate.
따라서, 필드영역에서 발생할 수 있는 버즈빅의 문제점을 해결하기 위하여 STI공정이 개발 되었으며, 씨.엠.피(Chemical Mechanical Polishing)공정이 도입됨에 따라 STI공정은 보다 단순하게 되었다.Therefore, the STI process was developed to solve the problem of Buzzvik which may occur in the field area, and the STI process became simpler as the C.P.C.
도 1 및 도 2 는 종래 반도체소자의 제조방법을 도시한 제조공정도이다.1 and 2 are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor device.
도 1을 참조하면, 먼저, 반도체기판(10) 상에 패드산화막(12)과, 실리콘질화막(14), HTO(High Temperature Oxidation)막(16)을 순차적으로 적층한다. 그 후, HTO막(16) 상에 트랜치용 감광막(도시 안됨)의 패턴을 형성한 다음, 이를 식각마스크로 HTO막(16)에서부터 패드산화막(12)까지 순차적으로 식각하여 이들의 패턴이 적층된 마스크층을 형성한 후, 마스크층의 개구부에 의해 노출된 반도체기판(10)을 식각하여 소정 깊이를 갖는 트랜치(18)를 형성한다.Referring to FIG. 1, first, a pad oxide film 12, a silicon nitride film 14, and an HTO (High Temperature Oxidation) film 16 are sequentially stacked on a semiconductor substrate 10. Thereafter, a pattern of a trench photosensitive film (not shown) is formed on the HTO film 16, and then, the pattern is sequentially etched from the HTO film 16 to the pad oxide film 12 using an etch mask to stack these patterns. After forming the mask layer, the semiconductor substrate 10 exposed by the opening of the mask layer is etched to form a trench 18 having a predetermined depth.
다음, 상기 감광막의 패턴을 제거한 후, 트랜치(18)가 형성될 때 손상된 반도체기판(10)을 보상하기 위하여 트랜치(18) 내측의 반도체기판(10)에 열산화막(20)을 형성한다.Next, after removing the photoresist pattern, a thermal oxide film 20 is formed on the semiconductor substrate 10 inside the trench 18 to compensate for the damaged semiconductor substrate 10 when the trench 18 is formed.
그 후, 트랜치(18)의 내,외측 전면에 측벽산화막으로 실리콘질화막(22)을 적층하고 그 상부에 버퍼산화막으로 MTO(Medium Temperature Oxidation)막(24)을 증착한 다음, MTO막(24)을 암모니아(NH3) 분위기에서 표면처리한다.Thereafter, a silicon nitride film 22 is stacked on the inner and outer sides of the trench 18 with a sidewall oxide film, and a MTO film 24 is deposited thereon with a buffer oxide film. Is surface treated in an ammonia (NH 3 ) atmosphere.
도 2를 참조하면, 트랜치(18)을 갭필하기 위하여 상기 결과물의 전면에 갭필용 산화막으로 CVD산화막(26a, 26b)적층하여 트랜치(18)을 채우게 된다.Referring to FIG. 2, in order to gapfill the trench 18, the CVD oxide layers 26a and 26b are stacked on the entire surface of the resultant to fill the trench 18.
상기와 같은 구조를 갖는 종래 반도체소자의 제조방법에 따르면 다음과 같은 문제점이 발생된다.According to the conventional method of manufacturing a semiconductor device having the above structure, the following problems occur.
첫째, 트랜치내에 CVD산화막을 채우기 전 트랜치내에 실리콘질화막이 적층된 상태에서의 에스펙트(Aspect)비가 2.5 이상일 경우 후속의 CVD산화막 갭필 공정시에 보이드(Void)가 발생된다.First, when the aspect ratio of the silicon nitride film is stacked in the trench before filling the CVD oxide film in the trench is 2.5 or more, voids are generated in the subsequent CVD oxide gap fill process.
둘째, 손상(damage)과 스트레스 측면에서 유리하여 널리 사용되는 CVD산화막을 트랜치의 캡필용으로 이용하는 경우, 도 2에 도시된 바와 같이 일정 두께까지는 CVD산화막(26a)이 균일하게 증착되다가 어느 시점에서 CVD산화막(26b)에 오버행(Overhang)이 발생되면서 보이드(30)를 유발하게 된다.Second, when a CVD oxide film widely used in terms of damage and stress is used for the cap fill of the trench, as shown in FIG. 2, the CVD oxide film 26a is uniformly deposited to a certain thickness, and then the CVD oxide film is uniformly deposited. Overhang occurs in the oxide layer 26b to cause the void 30.
이 때, 트랜치내에 보이드(30)가 액티브영역과 비슷한 높이에서 발생되는 경우 후속의 제조공정에 치명적인 영향을 미치게 되어 결국 소자의 신뢰성을 떨어뜨리게 된다.At this time, if the void 30 in the trench is generated at a height similar to that of the active region, it will have a fatal effect on subsequent manufacturing processes, resulting in deterioration of device reliability.
상기한 문제점을 해결하기 위한 본 발명의 목적은 트랜치를 채우는 갭필용으로 산화된 폴리실리콘막을 이용하여 트랜치의 갭필 특성을 향상시키도록 한 반도체소자의 제조방법에 제공하는 데 있다.An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device to improve the gap fill characteristics of the trench using a polysilicon film oxidized for the gap fill to fill the trench.
도 1 및 도 2 는 종래 기술에 따른 반도체소자의 제조방법을 도시한 제조공정도1 and 2 is a manufacturing process diagram showing a manufacturing method of a semiconductor device according to the prior art
도 3 내지 도 5 는 본 발명에 따른 반도체소자의 제조방법을 도시한 제조공정도3 to 5 are manufacturing process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
50 : 반도체기판 52 : 패드산화막50: semiconductor substrate 52: pad oxide film
54, 62 : 실리콘질화막 56 : HTO막54, 62: silicon nitride film 56: HTO film
58 : 트랜치 60, 70 : 열산화막58: trench 60, 70: thermal oxide film
64 : MTO막 66 : CVD 산화막64: MTO film 66: CVD oxide film
68 : 폴리실리콘막68: polysilicon film
상기한 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은The semiconductor device manufacturing method according to the present invention to achieve the above object is
반도체기판에 소정 깊이를 갖는 트랜치를 형성하는 단계;Forming a trench having a predetermined depth in the semiconductor substrate;
상기 트랜치의 내,외측 전면에 제 1산화막과 제 2산화막을 적층하는 단계;Stacking a first oxide film and a second oxide film on the inside and outside of the trench;
상기 제 2산화막 상에 CVD산화막과 폴리실리콘막을 증착하는 단계; 및Depositing a CVD oxide film and a polysilicon film on the second oxide film; And
상기 폴리실리콘막을 열산화시켜 상기 트랜치를 채우는 열산화막을 형성하는 단계를 포함한다.Thermally oxidizing the polysilicon film to form a thermal oxide film filling the trench.
바람직하게, 상기 폴리실리콘막은 모노 실렌(Mono - Silane : SiH4)계로 형성된다.Preferably, the polysilicon layer is formed of mono-silane (SiH 4 ).
상기한 본 발명에 따르면, 반도체기판에 소정 깊이를 갖는 트랜치를 형성한 다음, 트랜치의 내,외측에 CVD산화막을 형성하고 그 전면에 스텝커버리지가 우수한 모노 실렌계의 폴리실리콘막을 형성한 후, 이를 열산화시켜 트랜치를 채우는 열산화막을 형성함으로서 트랜치내의 보이드 형성을 억제함과 더불어 트랜치의 갭필 특성을 향상시킬 수 있다.According to the present invention, a trench having a predetermined depth is formed on a semiconductor substrate, and then a CVD oxide film is formed on the inside and the outside of the trench, and a monosilicon polysilicon film having excellent step coverage is formed on the entire surface thereof. By thermally oxidizing to form a thermal oxide film filling the trenches, void formation in the trenches can be suppressed and the gap fill characteristics of the trenches can be improved.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세하게 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 5 는 본 발명에 따른 반도체소자의 제조방법을 도시한 제조공정도이다.3 to 5 are manufacturing process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3을 참조하면, 먼저, 반도체기판(50) 상에 패드산화막(52)과, 실리콘질화막(54), HTO막(56)을 순차적으로 적층한다. 이 때, 실리콘질화막(54)과 HTO막(56)의 두께 합은 2000Å ∼ 3000Å 정도로 형성한다.Referring to FIG. 3, first, the pad oxide film 52, the silicon nitride film 54, and the HTO film 56 are sequentially stacked on the semiconductor substrate 50. At this time, the sum of the thicknesses of the silicon nitride film 54 and the HTO film 56 is about 2000 kPa to 3000 kPa.
다음, HTO막(56) 상에 트랜치용 감광막(도시 안됨)의 패턴을 형성한 다음, 이를 식각마스크로 HTO막(56)에서부터 패드산화막(52)까지 순차적으로 식각하여 이들의 패턴이 적층된 마스크층을 형성한 후, 마스크층의 개구부에 의해 노출된 반도체기판(50)을 식각하여 2500Å ∼ 5000Å 정도의 깊이를 갖는 트랜치(58)를 형성한다. 이어서, 트랜치(58)의 식각 공정시에 손상된 반도체기판(50)을 보상하기 위하여 트랜치(58) 내측의 반도체기판(50)에 열산화막(60)을 형성한다.Next, a pattern of a trench photosensitive film (not shown) is formed on the HTO film 56, and then, the etching mask is sequentially etched from the HTO film 56 to the pad oxide film 52 using an etch mask to stack the patterns thereof. After the layer is formed, the semiconductor substrate 50 exposed by the opening of the mask layer is etched to form a trench 58 having a depth of about 2500 Å to 5000 Å. Subsequently, a thermal oxide film 60 is formed on the semiconductor substrate 50 inside the trench 58 to compensate for the damaged semiconductor substrate 50 during the etching process of the trench 58.
그 후, 트랜치(58)의 내,외측에 측벽산화막으로 실리콘질화막(62)을 적층한 다음, 그 전면에 버퍼산화막으로 MTO막(64)을 증착한 후, MTO막(64)을 암모니아(NH3) 분위기에서 표면처리한다.After that, the silicon nitride film 62 is laminated on the inside and the outside of the trench 58 by a sidewall oxide film, and then the MTO film 64 is deposited on the entire surface of the trench 58 by using a buffer oxide film. 3 ) Surface treatment in atmosphere.
도 4를 참조하면, 트랜치(58) 내,외측의 MTO막(64) 상에 CVD산화막(66)과 스텝커버리지가 우수한 모노 실렌(Mono-sillan)계의 폴리실리콘막(68)을 순차적으로 증착한다.Referring to FIG. 4, a CVD oxide film 66 and a mono-sillan-based polysilicon film 68 having excellent step coverage are sequentially deposited on the MTO film 64 inside and outside the trench 58. do.
이 때, CVD산화막(66)은 후속의 열산화 공정시 완충역할을 하지만, 폴리실리콘막(68)이 과다 증착되는 경우 반도체기판(50)에 스트레스가 유발되므로 스트레스를 완화시킬 수 있을 정도의 두께, 예컨대 500Å ∼ 1000Å 두께 정도로 형성한다. 그리고, 후속의 열산화 공정시에 산소원자의 반도체기판(50)에 대한 어택(attack)은 트랜치(58)의 내,외측 전면에 증착된 실리콘질화막(62)에 의해 방지할 수 있다.At this time, the CVD oxide film 66 acts as a buffer during the subsequent thermal oxidation process, but when the polysilicon film 68 is over-deposited, stress is caused on the semiconductor substrate 50 so that the thickness can be alleviated. For example, it forms in about 500 to 1000 micrometer thickness. In the subsequent thermal oxidation process, an attack on the semiconductor substrate 50 of the oxygen atom can be prevented by the silicon nitride film 62 deposited on the inner and outer surfaces of the trench 58.
여기서, 폴리실리콘막(68)의 두께는 후속의 열산화 공정시에 2배 가량 증가됨을 고려하여 설정함이 바람직하다. CVD산화막(66) 상에 폴리실리콘막(68)을 증착할 때 디실렌(Di-sillan)계를 사용하지 않고 모노실렌계로 증착하는 것은 박막의 도포성, 즉 스텝커버리지가 우수하기 때문이다. 따라서, 트랜치(58)의 에스펙트비가 큰 경우에도 트랜치(58)를 채우는 갭필에는 아무런 문제가 없다.Here, the thickness of the polysilicon film 68 is preferably set in consideration of the increase of about 2 times in the subsequent thermal oxidation process. When the polysilicon film 68 is deposited on the CVD oxide film 66, the deposition of the polysilicon film without the use of a di-sillan system is performed because the coating property of the thin film, that is, the step coverage is excellent. Therefore, even when the aspect ratio of the trench 58 is large, there is no problem in the gap fill filling the trench 58.
도 5을 참조하면, 그 후, 폴리실리콘막(68)을 열산화시켜 폴리실리콘막(68)의 부피 팽창에 따른 열산화막(70)을 형성하여 트랜치(58)를 채운 다음, 필요에 따라 O3-TEOS막(도시 안됨)을 증착하고 이를 CMP 공정으로 연마하여 평탄화한다. 따라서, 트랜치(58)내의 보이드 형성을 방지함과 더불어 트랜치의 갭필 특성을 향상시킬 수 있다.Referring to FIG. 5, after that, the polysilicon film 68 is thermally oxidized to form a thermal oxide film 70 according to the volume expansion of the polysilicon film 68 to fill the trench 58. A 3- TEOS film (not shown) is deposited and polished by a CMP process to planarize. Therefore, it is possible to prevent the formation of voids in the trench 58 and to improve the gap fill characteristics of the trench.
이상에서와 같이 본 발명에 따르면, 반도체기판에 소정 깊이를 갖는 트랜치를 형성한 다음, 트랜치의 내,외측에 후속의 열산화 공정시에 유발되는 스트레스를 완화시킬 수 있을 정도 두께의 CVD산화막을 형성하고 그 전면에 스텝커버리지가 우수한 폴리실리콘막을 형성한 후, 이를 열산화시켜 트랜치를 채우는 열산화막을 형성한다.As described above, according to the present invention, a trench having a predetermined depth is formed in the semiconductor substrate, and then a CVD oxide film having a thickness sufficient to relieve the stress caused during the subsequent thermal oxidation process is formed inside and outside the trench. After forming a polysilicon film having excellent step coverage on the entire surface, and thermally oxidized it to form a thermal oxide film filling the trench.
따라서, 트랜치의 갭필용으로 CVD산화막을 이용할 때 트랜치내에 발생되는 보이드를 방지할 수 있어 트랜치의 갭필 특성을 향상시킨다.Therefore, when the CVD oxide film is used for the gap fill of the trench, voids generated in the trench can be prevented, thereby improving the gap fill characteristic of the trench.
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