KR20000041380A - Manufacturing method of thin film transistor of bottom gate type - Google Patents
Manufacturing method of thin film transistor of bottom gate type Download PDFInfo
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- KR20000041380A KR20000041380A KR1019980057239A KR19980057239A KR20000041380A KR 20000041380 A KR20000041380 A KR 20000041380A KR 1019980057239 A KR1019980057239 A KR 1019980057239A KR 19980057239 A KR19980057239 A KR 19980057239A KR 20000041380 A KR20000041380 A KR 20000041380A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010409 thin film Substances 0.000 title claims abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 34
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 SRAM(static random access memory) 등에 소자에 사용되는 바텀 게이트형(bottom gate type) 박막 트랜지스터(thin film transistor, TFT) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a bottom gate type thin film transistor (TFT) used in an element such as a static random access memory (SRAM).
종래의 바텀 게이트형 TFT를 사용하는 SRAM과 같은 소자에서는 TFT 게이트 폴리실리콘막을 정의하고, TFT 게이트 산화막을 형성한 다음, 노드 콘택에 접속되는 채널 폴리실리콘막을 정의하는 공정을 통해 제조해 왔다.In a device such as an SRAM using a conventional bottom gate type TFT, a TFT gate polysilicon film is defined, a TFT gate oxide film is formed, and a channel polysilicon film connected to a node contact is manufactured by a process.
이러한 공정을 통해 형성된 종래의 일반적인 바텀 게이트형 TFT는 게이트 산화막이 게이트 폴리실리콘막의 에지 부분을 지나가게 되는데, 보통 이 부분에 기하학적인 이유로 전계가 집중되어 TFT 게이트 산화막의 특성을 열화시키는 동시에 대기상태 전류(standby current)를 증가시키는 요인이 된다.In a conventional general bottom gate type TFT formed by such a process, a gate oxide film passes through an edge portion of a gate polysilicon film. In general, an electric field is concentrated in this portion to deteriorate the characteristics of the TFT gate oxide film and at the same time, a standby current This increases the standby current.
또한, 바텀 게이트 형성시 폴리실리콘막의 도핑을 위한 이온주입 공정과 플라즈마 식각에 의해 게이트의 식각 손상이 유발되고 후속 게이트 산화막 형성시 산화막과 게이트간의 계면 상태가 상당히 불안정하여 TFT 특성 열화의 주요 원인이 되고 있다.In addition, gate etching is caused by ion implantation process for plasma doping of polysilicon film and plasma etching during bottom gate formation, and the interfacial state between oxide film and gate is considerably unstable during subsequent gate oxide film formation, which is a major cause of TFT deterioration. have.
본 발명은 게이트 모서리의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와 그에 따른 대기상태 전류의 증가를 억제하는 바텀 게이트형 박막 트랜지스터 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a bottom gate type thin film transistor which suppresses deterioration of the gate oxide film due to the concentration of the electric field due to the geometry of the gate edge and an increase in the standby current.
또한, 본 발명은 게이트 산화막과 게이트간의 계면 상태를 안정화할 수 있는 바텀 게이트형 박막 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a bottom gate type thin film transistor capable of stabilizing an interface state between a gate oxide film and a gate.
도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 SRAM의 바텀 게이트형 박막 트랜지스터(TFT) 제조 공정도.1A to 1E are diagrams illustrating a process of manufacturing a bottom gate thin film transistor (TFT) of an SRAM according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 층간절연막10 silicon substrate 11 interlayer insulating film
12, 17 : 폴리실리콘막 12a : TFT 게이트12, 17 polysilicon film 12a: TFT gate
12b : 노드 콘택 14, 18 : 포토레지스트 패턴12b: node contact 14, 18: photoresist pattern
15 : 실리콘산화막 16 : 게이트 산화막15 silicon oxide film 16 gate oxide film
본 발명은 드레인 오프셋 영역의 게이트 전극 모서리를 국부적으로 산화시켜 게이트 모서리의 기하학적 구조에 의한 전계 집중을 완화시키는 기술이다. 게이트 전극 모서리의 국부 산화를 위하여 산소 이온주입 및 어닐링 공정을 수행할 수 있다.The present invention is a technique of locally oxidizing the gate electrode corner of the drain offset region to mitigate field concentration due to the geometry of the gate edge. Oxygen ion implantation and annealing may be performed to locally oxidize the gate electrode corners.
상기 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 특징적인 바텀 게이트형 박막 트랜지스터 제조방법은, 소정의 하부층 상부에 게이트 전극을 형성하는 제1 단계; 드레인 오프셋 영역의 상기 게이트 전극 모서리를 국부적으로 산화시키는 제2 단계; 상기 게이트 전극을 덮는 게이트 절연막을 형성하는 제3 단계; 및 소오스, 드레인 및 채널을 형성하는 제4 단계를 포함하여 이루어진다.In order to achieve the above technical problem, a characteristic bottom gate type thin film transistor manufacturing method provided by the present invention includes: a first step of forming a gate electrode on a predetermined lower layer; Locally oxidizing the gate electrode edge of the drain offset region; A third step of forming a gate insulating film covering the gate electrode; And a fourth step of forming a source, a drain, and a channel.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 SRAM의 바텀 게이트형 TFT 제조 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.1A to 1E illustrate a process of manufacturing a bottom gate TFT of an SRAM according to an exemplary embodiment of the present invention, which will be described below with reference to the drawing.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 액세스 트랜지스터(도시되지 않음), 구동 트랜지스터(도시되지 않음) 등의 벌크(bulk) 트랜지스터를 형성한 다음, 층간절연막(11)을 증착하고, 이를 선택 식각하여 노드 콘택홀을 형성한다. 이어서, 전체구조 상부에 TFT 게이트 형성을 위한 폴리실리콘막(12)을 형성한 다음, 60keV의 에너지와 4.0E15의 도즈(dose)를 사용하여 As 이온주입을 실시하여 폴리실리콘막(12)을 n형으로 도핑한다.First, as shown in FIG. 1A, a bulk transistor such as an access transistor (not shown) and a driving transistor (not shown) is formed on the silicon substrate 10, and then the interlayer insulating film 11 is deposited. Selective etching is performed to form node contact holes. Subsequently, a polysilicon film 12 for forming a TFT gate is formed on the entire structure, and then As ion implantation is performed using energy of 60 keV and a dose of 4.0E15 to n the polysilicon film 12. Doping with the mold.
다음으로, 도 1b에 도시된 바와 같이 폴리실리콘막(12)을 선택 식각하여 TFT 게이트(12a) 및 노드 콘택(12b)을 패터닝하고, 포토레지스트 패턴(14)을 형성한다. 이때, 포토레지스트 패턴(14)은 드레인 오프셋(offset) 영역이 오픈 되도록 형성한다. 이어서, 포토레지스트 패턴(14)을 이온주입 마스크로 사용하여 O2 +이온주입 공정을 실시한다.Next, as illustrated in FIG. 1B, the polysilicon film 12 is selectively etched to pattern the TFT gate 12a and the node contact 12b to form a photoresist pattern 14. In this case, the photoresist pattern 14 is formed so that the drain offset region is opened. Subsequently, an O 2 + ion implantation process is performed using the photoresist pattern 14 as an ion implantation mask.
계속하여, 도 1c에 도시된 바와 같이 포토레지스트 패턴(14)을 제거하고, N2O 분위기에서 어닐링을 실시하여 O2 +가 주입된 게이트 전극(12a) 모서리 부분에서 실리콘산화막(15)이 형성되도록 한다. 이어서, 전체구조 상부에 게이트 산화막(16)을 증착하고, 게이트 산화막(16)을 선택 식각하여 노드 콘택(12b)의 일부(TFT 드레인 콘택 영역)를 노출시킨다. 이때, 게이트 산화막(16)은 830℃의 온도에서 고온산화막(HTO)을 증착하여 형성할 수 있으며, 어닐링을 통해 게이트 전극(12a)의 식각 손상 및 이온주입 손상을 제거할 수 있다.Subsequently, as shown in FIG. 1C, the photoresist pattern 14 is removed, and annealing is performed in an N 2 O atmosphere to form the silicon oxide film 15 at the corner portion of the gate electrode 12a into which the O 2 + is injected. Be sure to Subsequently, the gate oxide film 16 is deposited on the entire structure, and the gate oxide film 16 is selectively etched to expose a part of the node contact 12b (TFT drain contact region). In this case, the gate oxide layer 16 may be formed by depositing a high temperature oxide layer (HTO) at a temperature of 830 ° C, and may remove an etching damage and an ion implantation damage of the gate electrode 12a through annealing.
이어서, 세정 공정을 실시하고, 채널 형성을 위한 폴리실리콘막(17)을 증착하고, SPG(solid phase growth) 열처리를 실시한 다음, TFT의 문턱전압(VT)을 결정하기 위한 VT이온주입을 실시한다. 계속하여, TFT의 대기상태 전류를 감소시키기 위해 LDO(lightly doped offset) 이온주입을 실시한다.Then subjected to the washing step, and, depositing a polysilicon film 17 for channel formation subjected to the SPG (solid phase growth) Heat Treatment Next, V T ion implantation for determining a threshold voltage (V T) of the TFT Conduct. Subsequently, lightly doped offset (LDO) ion implantation is performed to reduce the standby current of the TFT.
다음으로, 도 1d에 도시된 바와 같이 소오스/드레인 형성을 위한 포토레지스트 패턴(18)을 형성하고, 이를 이온주입 마스크로 사용하여 소오스/드레인 이온주입을 실시한다. 이때, TFT의 온 전류(on current)를 증가시키기 위하여 소오스 오버랩이 형성되도록 포토레지스트 패턴(18)을 형성한다.Next, as shown in FIG. 1D, a photoresist pattern 18 for forming a source / drain is formed, and source / drain ion implantation is performed using the photoresist pattern 18 as an ion implantation mask. At this time, the photoresist pattern 18 is formed such that a source overlap is formed in order to increase the on current of the TFT.
계속하여, 도 1e에 도시된 바와 같이 포토레지스트 패턴(18)을 제거하고, 폴리실리콘막(17)을 선택 식각하여 TFT의 소오스, 드레인 및 채널을 디파인함으로써 TFT 제조를 완료한다. 이때, TFT의 소오스측에 Vss 라인을 함께 디파인한다.Subsequently, as shown in FIG. 1E, the photoresist pattern 18 is removed, and the polysilicon film 17 is selectively etched to fine-tune the source, drain and channel of the TFT to complete the TFT fabrication. At this time, the Vss line is defined together on the source side of the TFT.
이후, 층간절연막을 형성하고 평탄화 공정을 거쳐, 금속배선 공정을 실시하고, 비트라인, 파워라인 등을 형성한다.Thereafter, an interlayer insulating film is formed, a planarization process is performed, a metal wiring process is performed, and bit lines, power lines, and the like are formed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 실시예에서는 SRAM의 TFT를 제조하는 경우를 일례로 들어 설명하였으나, 본 발명은 액정표시장치(LCD)와 같은 다른 소자 제조시에도 적용할 수 있다.For example, in the above-described embodiment, a case of manufacturing a TFT of an SRAM has been described as an example, but the present invention can be applied to manufacturing other devices such as a liquid crystal display (LCD).
또한, 전술한 실시예에서는 게이트 모서리의 국부적인 산화를 위해 O2 +이온주입 및 N2O 분위기에서의 어닐링을 실시하는 것을 일례로 들어 설명하였으나, 본 발명은 다른 방법을 통해 게이트 모서리를 산화시키는 경우에도 적용할 수 있다.In addition, the above-described embodiment has been described as an example of performing an annealing in an O 2 + ion implantation and N 2 O atmosphere for the local oxidation of the gate edge, the present invention is to oxidize the gate edge through another method It can also be applied.
전술한 본 발명은 게이트 모서리 영역을 산화함으로써 오프셋 영역의 게이트 산화막을 두껍게 형성하여 드레인 전계의 집중에 의한 대기상태 전류의 증가를 억제하는 효과가 있으며, 또한 상기 열처리를 통해 게이트 모서리 영역에 형성된 게이트 산화막의 밀도를 향상시키고 게이트 전극의 식각 손상 및 이온주입 손상을 제거함으로써 게이트 산화막과 채널 폴리실리콘간의 계면 특성을 향상시키는 효과가 있다.The present invention described above has the effect of thickening the gate oxide film in the offset region by oxidizing the gate edge region to suppress an increase in the standby current due to concentration of the drain electric field, and also by forming the gate oxide film in the gate edge region through the heat treatment. By improving the density and removing the etching damage and ion implantation damage of the gate electrode has an effect of improving the interface characteristics between the gate oxide film and the channel polysilicon.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980057239A KR20000041380A (en) | 1998-12-22 | 1998-12-22 | Manufacturing method of thin film transistor of bottom gate type |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980057239A KR20000041380A (en) | 1998-12-22 | 1998-12-22 | Manufacturing method of thin film transistor of bottom gate type |
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| Publication Number | Publication Date |
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| KR20000041380A true KR20000041380A (en) | 2000-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019980057239A KR20000041380A (en) | 1998-12-22 | 1998-12-22 | Manufacturing method of thin film transistor of bottom gate type |
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| KR (1) | KR20000041380A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8476631B2 (en) | 2010-06-08 | 2013-07-02 | Samsung Display Co., Ltd. | Thin film transistor with offset structure and electrodes in a symmetrical arrangement |
-
1998
- 1998-12-22 KR KR1019980057239A patent/KR20000041380A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8476631B2 (en) | 2010-06-08 | 2013-07-02 | Samsung Display Co., Ltd. | Thin film transistor with offset structure and electrodes in a symmetrical arrangement |
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