KR20000041363A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
- Publication number
- KR20000041363A KR20000041363A KR1019980057222A KR19980057222A KR20000041363A KR 20000041363 A KR20000041363 A KR 20000041363A KR 1019980057222 A KR1019980057222 A KR 1019980057222A KR 19980057222 A KR19980057222 A KR 19980057222A KR 20000041363 A KR20000041363 A KR 20000041363A
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- film
- layer
- semiconductor
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 콘택 형성 방법에 관한 것으로, 좀 더 구체적으로는 얕은 접합을 갖는 고집적 소자에 옴성 콘택(ohmic contact)을 형성하는 반도체 장치의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming contacts in a semiconductor device, and more particularly, to a method for forming contacts in a semiconductor device for forming ohmic contacts in a highly integrated device having a shallow junction.
반도체 장치가 고집적화 됨에 따라, 트랜지스터의 게이트 폭(gate width)이 감소할 뿐아니라, 접합의 깊이(junction depth)도 감소하고 있다.As semiconductor devices become more integrated, not only the gate width of the transistor is reduced, but also the junction depth is decreasing.
이에 따라, 소오스/드레인 영역(source/drain region)과 전기적으로 접속되는 콘택 형성에 있어서 실리콘의 소모를 최소화해야 한다.Accordingly, it is necessary to minimize the consumption of silicon in forming a contact electrically connected to the source / drain region.
도 1은 종래의 반도체 장치의 콘택 형성 방법에 의한 콘택 구조를 보여주는 단면도이다.1 is a cross-sectional view illustrating a contact structure by a contact forming method of a conventional semiconductor device.
도 1을 참조하면, 종래의 반도체 장치의 콘택 형성 방법은 먼저, 활성 영역(active region)과 비활성 영역(inactive region)을 정의하기 위한 소자격리막(device isolation layer)(12)이 형성된다. 다음, 활성 영역 상에 게이트 전극(gate electrode)(14), 게이트 스페이서(gate spacer)(16), 소오스/드레인 영역(18)을 갖는 트랜지스터(transistor)가 형성된다.Referring to FIG. 1, in the conventional method for forming a contact of a semiconductor device, a device isolation layer 12 is formed to define an active region and an inactive region. Next, a transistor having a gate electrode 14, a gate spacer 16, and a source / drain region 18 is formed on the active region.
상기 트랜지스터를 포함하여 반도체 기판(10) 전면에 층간절연막(interlayer dielectric)(20)이 증착 된다. 상기 소오스/드레인 영역(18)의 일부가 노출되도록 층간절연막(20)이 식각 되어 콘택홀(contact hole)(22)이 형성된다. 다음, 이 분야에서 잘 알려진 실리사이드화 공정을 수행하여 상기 콘택홀(22)의 하부에 실리사이드막(silicide layer)(24)이 선택적으로 형성된다.The interlayer dielectric 20 is deposited on the entire surface of the semiconductor substrate 10 including the transistor. The interlayer insulating layer 20 is etched to expose a portion of the source / drain region 18 to form a contact hole 22. Next, a silicide layer 24 is selectively formed on the lower portion of the contact hole 22 by performing a suicide process well known in the art.
상기 실리사이드막(24)은 콘택 저항을 최소화하기 위해 형성되는 옴성막(ohmic layer)으로서, 예를 들어 티타늄 실리사이드막(TiSix)이다.The silicide layer 24 is an ohmic layer formed to minimize contact resistance. For example, the silicide layer 24 is a titanium silicide layer TiSix.
상기 콘택홀(22)의 내벽에 금속 배리어막(metal barrier layer)(26)인 티타늄 질화막(TiN)(26)이 증착된 후, 상기 콘택홀(22)이 완전히 채워지도록 금속 배선막(28)인 텅스텐막(W)(28)이 증착 된다.After the titanium nitride layer TiN 26, which is a metal barrier layer 26, is deposited on the inner wall of the contact hole 22, the metal wiring layer 28 is completely filled. Phosphorous tungsten film (W) 28 is deposited.
상기 텅스텐막 및 티타늄 질화막이 사진식각공정(photolithography)으로 패터닝(patterning) 되어 금속 콘택(metal contact)(30)이 형성된다.The tungsten film and the titanium nitride film are patterned by photolithography to form a metal contact 30.
그러나, 상기 실리사이드막(24) 형성시 반도체 기판(10) 즉, 상기 소오스/드레인 영역(18)의 일부가 소모되는데, 소오스/드레인 영역(18)이 얕은 경우, 접합 누설(junction leakage) 등의 문제점이 발생된다.However, when the silicide layer 24 is formed, a portion of the semiconductor substrate 10, that is, the source / drain region 18 is consumed. When the source / drain region 18 is shallow, junction leakage may be caused. Problems arise.
본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 콘택 저항을 감소시키기 위해 접합 영역에 실리사이드화 공정 적용시 접합 영역의 소모에 따른 접합 누설을 방지할 수 있는 반도체 장치의 콘택 형성 방법을 제공함에 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, and provides a method for forming a contact of a semiconductor device which can prevent the junction leakage due to the consumption of the junction region when the silicide process is applied to the junction region to reduce the contact resistance. Has its purpose.
도 1은 종래의 반도체 장치의 콘택 형성 방법에 의한 콘택 구조를 보여주는 단면도;1 is a cross-sectional view showing a contact structure by a contact forming method of a conventional semiconductor device;
도 2 내지 도 4는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도.2 to 4 are flowcharts sequentially showing processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 반도체 기판 12, 102 : 소자격리막10, 100: semiconductor substrate 12, 102: device isolation film
14, 104 : 게이트 전극 16, 106 : 게이트 스페이서14, 104: gate electrode 16, 106: gate spacer
18, 108 : 소오스/드레인 영역 20, 110 : 층간절연막18, 108: source / drain regions 20, 110: interlayer insulating film
22, 112 : 콘택홀 24, 114a : 실리사이드막22, 112: contact hole 24, 114a: silicide film
26, 116 : 금속 배리어막 28, 118 : 금속 배선막26 and 116 metal barrier films 28 and 118 metal wiring films
30, 120 : 금속 콘택 114 : 반도체막, 실리콘막30, 120: metal contact 114: semiconductor film, silicon film
(구성)(Configuration)
상술한 목적을 달성하기 위한 본 발명의 특징에 의하면, 반도체 장치의 콘택 형성 방법은, 접합 영역(junction region)(108)을 갖는 반도체 기판(100)과, 반도체 기판(100) 상에 형성된 절연막(110)을 식각 하여 상기 접합 영역(108)의 일부가 노출되도록 형성된 콘택홀(112)과, 옴성 콘택(ohmic contact)을 형성하기 위해 콘택홀(112)의 하부면에 형성된 실리사이드막(114a)을 갖는 반도체 장치의 콘택 형성 방법에 있어서, 상기 실리사이드막(114a)은 상기 콘택홀(112)을 포함하여 절연막(110) 상에 반도체막(114)을 증착 하는 단계; 및 상기 반도체막(114)을 실리사이드화(silicidation)하여 실리사이드막(114a)을 형성하는 단계를 포함한다.According to a feature of the present invention for achieving the above object, a contact forming method of a semiconductor device includes a semiconductor substrate 100 having a junction region 108 and an insulating film formed on the semiconductor substrate 100. The contact hole 112 formed to expose a portion of the junction region 108 by etching 110 and the silicide layer 114a formed on the bottom surface of the contact hole 112 to form an ohmic contact are formed. A method for forming a contact of a semiconductor device having a semiconductor device, the silicide layer comprising: depositing a semiconductor layer on an insulating layer (110) including the contact hole (112); And silicidating the semiconductor film 114 to form a silicide film 114a.
(작용)(Action)
도 4를 참조하면, 본 발명의 실시예에 따른 신규한 반도체 장치의 콘택 형성 방법은, 콘택홀의 내벽에 실리콘막이 증착된 후, 이 실리콘막이 실리사이드화 되어 실리사이드막이 형성된다. 이로써, 얕은 접합에 실리사이드막 형성시 접합 소모에 따른 접합 누설을 방지할 수 있다.Referring to FIG. 4, in the method for forming a contact of a novel semiconductor device according to an embodiment of the present invention, after a silicon film is deposited on an inner wall of a contact hole, the silicon film is silicided to form a silicide film. As a result, it is possible to prevent junction leakage due to junction consumption when forming the silicide film in the shallow junction.
(실시예)(Example)
이하, 도 2 내지 도 4를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.
도 2 내지 도 4는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.2 to 4 are flowcharts sequentially showing processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 2를 참조하면, 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법은 먼저, 반도체 기판(100) 상에 활성 영역과 비활성 영역을 정의하기 위해 소자격리막(102)이 형성된다. 상기 소자격리막(102)은 예를 들어, 얕은 트렌치 격리(shallow trench isolation) 방법으로 형성된다.Referring to FIG. 2, in the method for forming a contact of a semiconductor device according to an embodiment of the present invention, a device isolation layer 102 is first formed on a semiconductor substrate 100 to define active regions and inactive regions. The device isolation layer 102 is formed by, for example, a shallow trench isolation method.
상기 활성 영역 상에 게이트 전극(104), 게이트 스페이서(106), 그리고 소오스/드레인 영역(108)을 갖는 트랜지스터가 형성된다. 상기 소오스/드레인 영역(108)은 예를 들어, 0.1㎛ 이하로 얕게 형성된다.A transistor having a gate electrode 104, a gate spacer 106, and a source / drain region 108 is formed on the active region. The source / drain regions 108 are shallow, for example, 0.1 μm or less.
상기 트랜지스터를 포함하여 반도체 기판(100) 전면에 층간절연막(110)이 증착 된다. 상기 소오스/드레인 영역(108)의 일부가 노출되도록 층간절연막(110)이 식각 되어 콘택홀(112)이 형성된다.The interlayer insulating layer 110 is deposited on the entire surface of the semiconductor substrate 100 including the transistor. The interlayer insulating layer 110 is etched to expose a portion of the source / drain region 108 to form a contact hole 112.
도 3을 참조하면, 상기 콘택홀(112)을 포함하여 층간절연막(110) 상에 실리콘막(114) 예를 들어, 폴리실리콘막(poly-Si layer)이 증착 된다. 여기서, 상기 실리콘막(114)은 500Å 이하의 두께로 증착 된다.Referring to FIG. 3, a silicon film 114, for example, a poly-Si layer, is deposited on the interlayer insulating film 110 including the contact hole 112. Here, the silicon film 114 is deposited to a thickness of 500 kPa or less.
이 분야에서 잘 알려진 실리사이드화 공정으로 상기 실리콘막(114)이 옴성막인 실리사이드막(114a)으로 변화되도록 한다. 즉, 상기 실리콘막(114) 상에 금속막이 증착된 후 열처리 공정을 수행하고, 이어서 반응하지 않은 금속막을 습식 식각 등으로 제거하면 상기 실리사이드막(114a)이 형성된다. 여기서, 상기 금속막은 Ti 또는 Co 등이 사용된다.The silicon film 114 is changed to the silicide film 114a which is an ohmic film by a silicide-forming process well known in the art. That is, the silicide film 114a is formed by performing a heat treatment process after the metal film is deposited on the silicon film 114, and then removing the unreacted metal film by wet etching. Here, Ti or Co is used as the metal film.
상술한 바와 같이 형성된 실리사이드막(114a)은 종래 콘택의 하부에 형성되는 실리사이드막과 달리, 상기 소오스/드레인 영역(108)을 소모하지 않고 형성된다. 따라서, 접합 누설이 방지된다.The silicide layer 114a formed as described above is formed without consuming the source / drain regions 108, unlike the silicide layer formed under the conventional contact. Thus, junction leakage is prevented.
상기 실리사이드막(114a) 상에 금속 배리어막(116)이 증착 된다. 상기 금속 배리어막(116)은 실리콘과 금속의 상호 반응을 억제하고, 금속 배선막(118)의 접착 특성을 향상시키기 위해 형성되는 막으로서, 예를 들어 Ti, TiN, Ta, TaN, WN, 그리고 TiSiN 등의 단일막 또는 이들의 복합막이다.The metal barrier layer 116 is deposited on the silicide layer 114a. The metal barrier film 116 is a film formed to suppress the mutual reaction between silicon and the metal and to improve the adhesion property of the metal wiring film 118. For example, Ti, TiN, Ta, TaN, WN, and Single films such as TiSiN or composite films thereof.
상기 금속 배리어막(116) 상에 콘택홀(112)이 완전히 채워지도록 금속 배선막(118)이 증착 된다. 상기 금속 배선막(118)은 예를 들어, W, Al, Cu, Ti, TiN, poly-Si, W-Si, Al-Cu, 또는 Al-Cu-Si막이다.The metal wiring layer 118 is deposited to completely fill the contact hole 112 on the metal barrier layer 116. The metal wiring film 118 is, for example, a W, Al, Cu, Ti, TiN, poly-Si, W-Si, Al-Cu, or Al-Cu-Si film.
상기 금속 배선막(118), 금속 배리어막(116), 그리고 실리사이드막(114a)이 패터닝 되어 도 4에 도시된 바와 같이, 금속 콘택(120)이 형성된다.The metal wiring layer 118, the metal barrier layer 116, and the silicide layer 114a are patterned to form a metal contact 120, as shown in FIG. 4.
한편, 상기 금속 배선막(118)이 증착된 후, 상기 층간절연막(110)의 상부 표면이 노출되도록 금속 배선막(118), 금속 배리어막(116), 그리고 실리사이드막(114a)이 차례로 평탄화 식각(planarization etch)되어 콘택 플러그(contact plug)가 형성된 후, 다시 다른 금속 배선막(도면에 미도시)이 증착 및 패터닝 되어 상기 금속 콘택(120)이 형성될 수도 있다. 상기 평탄화 식각 공정은 예를 들어, CMP(chemical mechanical polishing) 공정으로 수행된다.Meanwhile, after the metal wiring layer 118 is deposited, the metal wiring layer 118, the metal barrier layer 116, and the silicide layer 114a are sequentially planarized in order to expose the upper surface of the interlayer insulating layer 110. After the planarization etch to form a contact plug, another metal wiring layer (not shown) may be deposited and patterned to form the metal contact 120. The planarization etching process is performed by, for example, a chemical mechanical polishing (CMP) process.
상기 콘택홀(112)을 채우는 금속 배리어막(116)은 예를 들어, 텅스텐막이 사용되고, 상기 패터닝 하는 금속막은 예를 들어, 알루미늄막이 사용된다.As the metal barrier film 116 filling the contact hole 112, for example, a tungsten film is used, and the patterning metal film is, for example, an aluminum film.
본 발명은 콘택홀의 내벽에 실리콘막을 증착한 후, 이 실리콘막을 실리사이드화 함으로써, 얕은 접합에 실리사이드막 형성시 접합 소모에 따른 접합 누설을 방지할 수 있는 효과가 있다.According to the present invention, after depositing a silicon film on the inner wall of the contact hole, the silicon film is silicided, thereby preventing the leakage of the junction due to the consumption of the bond when forming the silicide film in the shallow junction.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980057222A KR20000041363A (en) | 1998-12-22 | 1998-12-22 | Method for forming contact of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980057222A KR20000041363A (en) | 1998-12-22 | 1998-12-22 | Method for forming contact of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000041363A true KR20000041363A (en) | 2000-07-15 |
Family
ID=19564603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980057222A KR20000041363A (en) | 1998-12-22 | 1998-12-22 | Method for forming contact of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000041363A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100730472B1 (en) * | 2001-06-28 | 2007-06-19 | 매그나칩 반도체 유한회사 | Fabricating method of image sensor |
-
1998
- 1998-12-22 KR KR1019980057222A patent/KR20000041363A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100730472B1 (en) * | 2001-06-28 | 2007-06-19 | 매그나칩 반도체 유한회사 | Fabricating method of image sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6090700A (en) | Metallization method for forming interconnects in an integrated circuit | |
| US20110263113A1 (en) | Method for manufacturing a semiconductor device | |
| KR100439242B1 (en) | Method of forming a contact opening adjacent to an isolation trench in a semiconductor substrate | |
| JPH11191623A (en) | Manufacture of semiconductor device for making self-aligned local interconnection which is self-aligned | |
| US6207543B1 (en) | Metallization technique for gate electrodes and local interconnects | |
| JPH1187529A (en) | Integrated circuit contact | |
| US6329720B1 (en) | Tungsten local interconnect for silicon integrated circuit structures, and method of making same | |
| US6184113B1 (en) | Method of manufacturing a gate electrode in a semiconductor device | |
| US20030113973A1 (en) | Method for fabricating local interconnects | |
| JPH09153546A (en) | Semiconductor device and its manufacture | |
| JP3534589B2 (en) | Multilayer wiring device and method of manufacturing the same | |
| KR20000041363A (en) | Method for forming contact of semiconductor device | |
| US20050142841A1 (en) | Method for forming metal pattern to reduce contact resistivity with interconnection contact | |
| JP2000150681A (en) | Semiconductor device | |
| US20070145492A1 (en) | Semiconductor device and method of manufacture | |
| JP2005209710A (en) | Manufacturing method for semiconductor integrated circuit device | |
| KR100357181B1 (en) | Plug layer of semiconductor device and method for forming the same | |
| US6323540B1 (en) | Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure | |
| KR100200745B1 (en) | Fabricating method of semiconductor device | |
| KR100365412B1 (en) | Method for forming metal line of semicoductor device | |
| KR0161882B1 (en) | Method of manufacturing semiconductor device | |
| KR100304967B1 (en) | Metal line of semiconductor device and method for fabricating the same | |
| KR20000027911A (en) | Method of forming contact of semiconductor device | |
| KR20010107101A (en) | Metal wiring method of semiconductor device | |
| KR20000043913A (en) | Method for forming metal contact of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |