JPH09153546A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a phenomenon which has an influence upon the reliability of a semiconductor device by making the open width of an opening part formed in a first insulating film wider than that formed in the second insulating film and making a conductive film formed in the inner wall of the opening part and a conductive film formed in the bottom part of the opening part continue in the boundary. SOLUTION: An element separating film 12 is formed in a semiconductor substrate 10, and a diffused layer 14 is formed in the region of an element. A layer insulating film 20 comprising an etching stopper film 16 and an insulating film 18 is formed in the semiconductor substrate 10, and therein a contact hole 22 which reaches the semiconductor substrate is perforated. A conductive film 24 which functions as a barrier metal is formed on the inner wall of the contact hole 22 and the layer insulating film 20, and a plug 26 is buried in the contact hole 22 in which it is formed. A wiring layer 28 connected to the plug 26 is formed on the layer insulating film 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring technique in a semiconductor device, and more particularly to a semiconductor device having a wiring structure suitable for high integration and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the increase in the scale of LSIs, miniaturization of elements has been pursued. 2. Description of the Related Art In order to realize a semiconductor integrated circuit having a gate, a wiring, and a contact hole with finer dimensions, it has been conventionally practiced to shorten the exposure wavelength in photolithography to improve the resolution.

[0003] While the minimum resolution size is reduced in this way, various device structures for reducing the alignment margin between lithography steps have been studied, and the device size can be reduced without reducing the size of the pattern to be formed. Attempts have been made to make it smaller. As such a device structure, for example, a self-aligned contact (Self-Align
Contact: hereinafter referred to as SAC) or borderless contact (hereinafter referred to as BLC).

A conventional SAC structure will be described in comparison with a case where no SAC structure is used. As shown in FIG. 30A, in the case where two gate electrodes 40 are formed on the semiconductor substrate 10 and the interlayer insulating film 20 is formed on the upper layer of the gate electrodes 40, two gate electrodes 40 are formed. When the contact hole 22 is opened to the semiconductor substrate 10 through the gap, it is necessary to arrange the gate electrode 40 in advance in consideration of the alignment accuracy when the contact hole 22 is opened.

That is, the distance a between the contact hole 22 and the gate electrode 40 must be at least as high as the alignment accuracy so that the conductive film and the gate electrode 40 are not short-circuited when the contact hole 22 is filled with the conductive film. It must be (FIG. 30 (b)). Therefore, the distance between the gate electrodes 40 is affected by the contact holes 22, and further miniaturization becomes difficult.

On the other hand, in the case of the SAC structure, as shown in FIG.
As shown in 0 (c), the gate electrode 40 is covered with the interlayer insulating film 20 and the insulating film 38 having etching selectivity. Therefore, when the interlayer insulating film 20 is etched, the insulating film 38 is not etched and the contact hole 2
Even when the conductive film is embedded in 2, the conductive film and the gate electrode 4
There is no short circuit with 0.

Therefore, even when a positional deviation occurs in the lithography process for forming the contact hole 22, the opening of the semiconductor substrate 10 is determined only by the gate electrode 40 and the insulating film 38, so that FIG. As shown, the gate electrode 40 and the contact hole 22 are
It can be arranged without considering alignment. As a result, the element can be miniaturized.

The SAC structure is described in, for example, Japanese Patent Laid-Open No. 61-61.
-292323, JP-A-4-106929, and '94 Symp. VLSI Tech., Tech. Dig., Pp.99-100. Next, regarding the conventional BLC structure, B
Description will be made in comparison with the case where the LC structure is not used.

As shown in FIG. 31A, the semiconductor substrate 1
In the case where the element isolation film 12 is formed on the substrate 0 and the interlayer insulating film 20 is formed thereover, when the contact hole 22 is opened in the vicinity of the element isolation film 12 and when the positional deviation occurs, In order to prevent the contact hole 22 from being located on the element isolation film 12, the contact hole 22
And the element isolation film 12 must be separated from each other.

That is, when the contact hole 22 is located on the element isolation film, the element isolation film 12 is etched in the etching for opening the contact hole 22, and when the contact hole 22 is filled with a conductive film, the conductivity is reduced. This is because a junction short circuit occurs between the conductive film 24 and the semiconductor substrate 10 (FIG. 31B). On the other hand, in the case of the BLC structure, as shown in FIG. 31C, the interlayer insulating film 20 is formed by the insulating films 16 and 18 having different etching selectivity. At this time, if a material is selected so that the etching selectivity of the insulating film 16 in contact with the element isolation film 12 is sufficient for the element isolation film 12, the element isolation is achieved even when the contact hole 22 is opened to the surface of the semiconductor substrate 10. Since the film 12 is not etched, a junction short circuit between the conductive film embedded in the contact hole 22 and the semiconductor substrate 10 can be prevented.

Therefore, the BLC structure can prevent a junction short even when the element isolation film 12 and the contact hole 22 overlap each other. Therefore, it is necessary to consider the alignment margin between the element isolation film 12 and the contact hole 22. Without
For example, as shown in FIG. 31D, the contact hole 2
2 can be arranged. As a result, the element can be miniaturized.

[0012]

However, the semiconductor device using the above-mentioned conventional BLC structure has the following problems. That is, when the insulating film 16 is etched, it is desirable to use wet etching in order to obtain a selection ratio with the element isolation film 12, but wet etching for removing the insulating film 16 is isotropic etching. The insulating film 16 under the insulating film 18 is also etched to form the holes 30 (FIG. 32A). Since the holes 30 thus formed cannot be covered by the conventional sputtering method, they remain even after the conductive film 24 is deposited (FIG. 3).
2 (b)). Therefore, when the plug 26 is formed by using the W filling method in the contact formation process of the next step, WF ₆ which is the source gas invades from the vacancy portion to cause substrate erosion called wormhole, which causes the source / drain. Junction breakage sometimes occurred in the diffusion layer 14 (FIG. 32C).

Further, when Al (aluminum) deposited by the CVD method is used as the wiring material instead of the W plug, the Al and the semiconductor substrate are in direct contact with each other in the hole 30, so that The heat treatment of the process may cause Al to react with the semiconductor substrate, resulting in junction breakdown in the source / drain diffusion layer 14 (FIG. 33).
(A)).

The same was true when Cu was used as the wiring material. Particularly, when Cu is diffused in the semiconductor substrate, a deep level is formed, so that the characteristics of the transistor may be significantly deteriorated. Further, since Cu easily diffuses in the silicon oxide film, when Cu reaches the gate oxide film 34, the leak current between the gate electrode 40 and the semiconductor substrate 10 may increase (FIG. 33 (b)).

As shown in FIG. 34, the semiconductor substrate 2
In the semiconductor device having the wiring 210 connected to the contact plug 208 embedded in the interlayer insulating film 202 on 00, when the BLC structure is applied when opening the via hole connected to the wiring 210, when the via hole is opened. The insulating film 220 may become the interlayer insulating film 208 due to misalignment or the like.
When the etching stopper film 216 immediately above is etched, the contact plug 208 is exposed in the hole 224 formed when the etching stopper film 216 is etched, and the contact plug 230 and the contact plug 2 are exposed.
08 was sometimes short-circuited.

Further, if the etching stopper film 112 is removed without forming the holes 124 by using anisotropic reactive ion etching, it is difficult to secure the selectivity with respect to the underlying film. That is, FIG. 35 (a)
In the structure shown in FIG. 2, if the etching stopper film 112 in the wiring groove 118 is etched under the condition that a sufficient selection ratio with respect to the interlayer insulating film 104 can be secured, a sufficient selection ratio with respect to the contact plug 110 can be secured. However, the contact plug 110 was sometimes etched (FIG. 35B).

On the contrary, the etching stopper film 11
When 2 is etched under the condition that a sufficient selection ratio can be secured with respect to the contact plug 110, the interlayer insulating film 104
In some cases, it was not possible to secure a sufficient selection ratio with respect to, and the interlayer insulating film 104 was sometimes etched (FIG. 35).
(C) As described above, in the etching of the etching stopper film 112, it is difficult to secure the etching selectivity with respect to the contact plug 110 and the interlayer insulating film 104 at the same time. May have affected.

Further, when the BLC structure is applied when forming the contact plug 144 on the wiring 122 formed by being buried in the interlayer insulating film 114, the etching stopper film 130 is recessed into the hole 138. Since the wiring 122 is exposed even after the conductive film 140 is formed, when the plug 142 is embedded, the source gas of the plug 142 and the wiring 122 may react with each other to form a high resistance reactant 146. Therefore, the contact plug 144 and the wiring 1
In some cases, the contact characteristics with 22 were deteriorated (FIG. 36).

Further, in the course of the detailed examination by the inventors of the present application, a new problem which has not been known has been found. That is, for example, as shown in FIG. 37A, in the case of the SAC structure in which the position of the gate electrode 40 and the contact hole 22 overlap each other and there is a step in the contact hole 22, the insulating film 16 made of the SiN film is formed. Insulating film 18
When the contact hole 22 is opened in the interlayer insulating film 20 made of Si, the Si at the shoulder of the step is etched when the insulating film 18 is etched.
It was found that the N film was easily worn. As a result, when the depleted SiN film is removed by the conventional method, as shown by the dotted line in FIG. 37A, the insulating film 38 immediately below the SiN film may be etched, and the gate electrode 40 may be exposed. .

Further, in order to suppress the wear of the SiN film as described above, if the selection ratio between the SiN film and the oxide film is increased by etching with phosphoric acid or fluorine radicals, the results shown in FIG.
As shown in (b), the etching of the insulating film 16 in the lateral direction proceeds to form the holes 30. After this, the conductive film 24
When deposited, since the conductive film 24 is not deposited in the holes 30, when using the W embedding a contact formation process of the next step, WF ₆ vacancies 3 is a source gas
A wormhole may be generated by penetrating from the zero portion, and a junction breakdown may occur at the source / drain diffusion layer 14 portion.

Even when salicide is formed on the source / drain diffusion layer 14, since the semiconductor layer 10 is not sufficiently covered with the silicide layer 44 at the edge portion of the element isolation film 12, the edge portion of the element isolation film 12 is not covered. Occasionally, wormholes were generated and junction destruction occurred (FIG. 38). An object of the present invention is to provide a semiconductor device having a SAC structure or a BLC structure, which can reduce a phenomenon that affects the reliability of the semiconductor device, such as a junction leak or a short circuit between wirings, and a manufacturing method thereof.

[0022]

The above object comprises a base substrate, a first insulating film formed on the base substrate, and a second insulating film formed on the first insulating film. An interlayer insulating film having an opening reaching the base substrate,
A conductive film formed on the inner wall and the bottom of the opening, and the opening width of the opening formed in the first insulating film is the opening formed in the second insulating film. And a conductive film formed on the inner wall of the opening and the conductive film formed on the bottom of the opening are continuous at a boundary. To be achieved. Since the base substrate is not exposed in the opening by configuring the semiconductor device in this manner, when the conductive material is embedded in the opening, the source gas of the conductive material erodes the base substrate or the conductive material and the base The reaction with the substrate can be prevented. Thereby, the reliability of the semiconductor device can be improved.

Further, in the above semiconductor device, it is preferable that the conductive film is buried under the second insulating film in the opening formed in the first insulating film. By configuring the semiconductor device in this way, the base substrate can be isolated from the inside of the opening. Further, the above-mentioned object is to provide a base substrate, an interlayer insulating film formed on the base substrate and having an opening having a different opening width depending on the depth, and a conductive film formed on the inner wall and the bottom of the opening. And the opening width of the bottom of the opening is substantially equal to the minimum opening width of the opening, and the base substrate at the bottom of the opening is covered with the conductive film. It is also achieved by the semiconductor device. By configuring the semiconductor device in this way, the base substrate can be completely isolated from the opening by conductive film formation.

In the above semiconductor device, the interlayer insulating film includes a first insulating film formed on the base substrate, a second insulating film formed on the first insulating film,
The opening width of the opening formed of the third insulating film formed on the second insulating film is the opening formed in the third insulating film. It is desirable that the opening width of the opening formed in the first insulating film is substantially equal to the opening width of the opening formed in the third insulating film.

Further, in the above semiconductor device, it is preferable that the underlying substrate further has at least one wiring layer. The semiconductor device according to the present invention can be applied to any wiring layer in a multilayer wiring structure having a plurality of wiring layers. Further, the above-mentioned object is a first insulating film deposition step of depositing a first insulating film on a base substrate,
A second insulating film deposition step of depositing a second insulating film having a different etching characteristic from that of the first insulating film on the first insulating film; and anisotropically etching the second insulating film. A first opening forming step of forming an opening reaching the first insulating film, and removing the first insulating film in the opening by a method in which etching also progresses in a lateral direction, A second opening forming step of opening the opening to the base substrate and simultaneously forming a void by etching the first insulating film under the second insulating film; and the base in the opening. So that the board is not exposed
And a conductive film deposition step of depositing a conductive film for closing at least the opening of the void in the opening. By manufacturing the semiconductor device in this manner, the inside of the opening and the base substrate can be completely separated by conductive film formation. This prevents the source gas of the conductive material from eroding the base substrate or reacting the base substrate with the conductive material when the conductive material is embedded in the opening in a later step. Thereby, the reliability of the semiconductor device can be improved.

In the method of manufacturing a semiconductor device described above, it is desirable that the conductive film is deposited by a collimating sputtering method in the conductive film depositing step. By depositing a conductive film by the collimate sputtering method,
The opening of the void can be easily closed. Further, in the above-described method for manufacturing a semiconductor device, in the conductive film depositing step, the conductive film is formed so that a film thickness of the conductive film at a bottom of the opening is larger than that of the first insulating film. It is desirable to deposit By doing so, the opening of the void can be easily closed.

In the method of manufacturing a semiconductor device described above, the conductive film is deposited by CVD in the conductive film deposition step.
Deposition by the method is desirable. By depositing the conductive film by the CVD method, the conductive film can be easily embedded in the void. Further, in the above-described method for manufacturing a semiconductor device, in the conductive film deposition step, the film thickness of the conductive film at the bottom of the opening is 1/2 or more of the film thickness of the first insulating film. Thus it is desirable to deposit the conductive film. By doing so, the opening of the void can be easily filled.

Further, the above-mentioned object is different from the first insulating film in the first insulating film deposition step of depositing the first insulating film on the underlying substrate and the etching property of the first insulating film on the first insulating film. A second insulating film deposition step of depositing a second insulating film; and a third insulating film of depositing a third insulating film having etching characteristics different from those of the second insulating film on the second insulating film. A deposition step, a first opening formation step of forming an opening reaching the second insulation film by anisotropically etching the third insulation film, and a second insulation inside the opening. A second opening forming step of opening the opening up to the first insulating film by removing the film by a method in which the etching also progresses in the lateral direction; and the first insulation in the opening. By anisotropically etching the film, the opening is formed in the base substrate. And a conductive film deposition step of depositing a conductive film so as to cover at least the underlying substrate exposed in the opening. Also achieved by. By manufacturing the semiconductor device in this manner, the inside of the opening and the base substrate can be completely separated by conductive film formation. Accordingly, even when the second insulating film needs to be isotropically etched to use the SAC structure, it is possible to prevent substrate erosion due to the source gas when the conductive material is embedded. Further, it is possible to prevent the reaction between the conductive material and the base substrate.

In the method of manufacturing a semiconductor device described above, in the step of forming the third opening, the overetching amount when etching the first insulating film is about 50%.
It is desirable to set the following. By manufacturing the semiconductor device in this manner, the opening can be formed while suppressing damage to the base substrate. In the method of manufacturing a semiconductor device described above, it is preferable that the underlying substrate further has at least one wiring layer. The method for manufacturing a semiconductor device according to the present invention can be applied to any wiring layer in a multilayer wiring structure having a plurality of wiring layers.

Further, the above-mentioned objects are as follows: a first insulating film deposition step of depositing a first insulating film on a base substrate; and a first insulating film thicker than the first insulating film on the first insulating film. A second insulating film deposition step of depositing a second insulating film having an etching characteristic different from that of the first insulating film; and a second insulating film thicker than the second insulating film on the second insulating film. And a third insulating film deposition step of depositing a third insulating film having different etching characteristics, and etching the third insulating film using the second insulating film as a stopper to reach the second insulating film. A first opening forming step of forming an opening, and etching the second insulating film in the opening using the first insulating film as a stopper to bring the opening up to the first insulating film. The second opening forming step of opening and the first insulating film in the opening are removed. And quenching also achieved by a method of manufacturing a semiconductor device characterized by having a third opening forming step of opening the opening to the said underlying substrate. By manufacturing a semiconductor device in this way,
The opening can be formed while reducing the influence on the base substrate.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

[A First Embodiment] The semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIGS. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIG. 2 and FIG. 3 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment, and FIG. 4 is a diagram explaining the principle of the collimating sputtering method. 5A and 5B are views for explaining the effect of the method for manufacturing the semiconductor device according to the present embodiment.

The structure of the semiconductor device according to the present embodiment is shown in FIG.
This will be described with reference to FIG. An element isolation film 12 that defines an element region is formed on the semiconductor substrate 10, and a diffusion layer 14 is formed in the element region. On the semiconductor substrate 10,
An interlayer insulating film 20 including an etching stopper film 16 and an insulating film 18 is formed, and a contact hole 22 reaching the semiconductor substrate is opened in the interlayer insulating film 20.
A conductive film 24 functioning as a barrier metal is formed on the inner wall of the contact hole 22 and the interlayer insulating film 20, and a plug 26 is embedded in the contact hole 22 having the conductive film 24 formed therein. A wiring layer 28 connected to the plug 26 is formed on the interlayer insulating film 20.

Here, the semiconductor device according to the present embodiment is characterized in that the etching stopper film 16 in the vicinity of the contact hole 22 is laterally etched to form the hole 30, but is formed in the contact hole 22. The conductive film 24 is formed so as to completely surround the inside of the contact hole without being interrupted at the hole 30 portion.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, an insulating film serving as an etching stopper film 16 is deposited on the semiconductor substrate 10 having the diffusion layer 14 formed in the element region defined by the element isolation film 12 (FIG. 2A). For example, a SiN film can be used as the etching stopper film. For example, the substrate temperature is set to 40 by the plasma CVD method.
0 ℃, power 300W, SiH ₄ flow rate 100cc,
The NH ₃ flow rate is set to 50 cc and deposited.

Next, an insulating film 18 is deposited on the etching stopper film 16 to form an interlayer insulating film 20 (FIG. 2).
(B)). As the insulating film 18, for example, a SiO ₂ film can be used. For example, by the plasma CVD method,
The substrate temperature is 400 ° C., the power is 300 W, the SiH ₄ flow rate is 50 cc, and the N ₂ O flow rate is 500 cc.
Then, a contact hole 22 penetrating the insulating film 18 and reaching the etching stopper film 16 is opened by ordinary lithography and anisotropic etching (FIG. 2).
(C)). At this time, the etching conditions are set so that the etching rate of the etching stopper film 16 made of the SiN film is sufficiently lower than that of the insulating film 18 made of the SiO ₂ film, so that the etching of the contact hole 22 is performed on the semiconductor substrate 10. Never reach.

After that, the etching stopper film 16 in the contact hole 22 is removed by isotropic etching (FIG. 2D). As a result, the bottom of the contact hole 22 reaches the semiconductor substrate 10, and at the same time, the etching stopper film 1 below the insulating film 18 near the contact hole 22.
6 is etched to form the holes 30. here,
Isotropic etching is performed, for example, at a temperature of 100 ° C. and a concentration of 90.
% Wet etching using a phosphoric acid aqueous solution. This isotropic etching is performed by the etching stopper film 1
Only 6 is removed, and the semiconductor substrate 10, the insulating film 18, and the element isolation film 12 are not affected at all.

Next, the conductive film 24 is formed so as to cover the openings of the holes 30 (FIG. 3A). When depositing the conductive film 24, it is desirable to use a collimating sputtering method that allows the conductive film 24 to be deposited thicker on the bottom of the contact hole 22 than the ordinary sputtering method. For example, the conductive film 24 is formed by depositing a TiN film with a power of 10 kW, a collimator aspect ratio of 2, and a pressure of 2 mTorr.

The collimating sputtering method is shown in FIG.
As shown in (a), by providing a collimator 54 between the target 50 and the substrate 52, only sputtered particles having a vertical component with respect to the substrate 52 are deposited on the substrate 52. In the normal sputtering method, sputtered particles contain particles with various directional components,
If a film is to be formed in the contact hole 22 having a large aspect ratio, as shown in FIG. 4B, the deposition rate becomes higher near the opening, and it becomes difficult to deposit at the bottom of the contact hole.

However, by providing the collimator 54, most of the sputtered particles have a vertical component, so that a film can be easily formed on the bottom of the contact hole (FIG. 4C). The conductive film 24 serves as a barrier layer against the WF ₆ gas at the time of embedding in a later step, and spatially isolates the semiconductor substrate 10 and the contact hole 22 and electrically conducts them. Is to have.

Since the conductive film 24 needs to be formed so as to cover at least the opening of the hole 30, the thickness of the conductive film 24 formed is at least as high as the opening of the hole 30. Is necessary. That is, the height of the opening is 100
When the thickness is nm, the thickness of the conductive film 24 to be formed needs to be 100 nm or more. Then, blanket W-
Using the CVD and etchback techniques, W is buried in the contact hole 22 to form the plug 26 (FIG. 3).
(B)). For example, the substrate temperature is 400 ° C and the pressure is 80T.
orr, WF ₆ flow rate is 20 cc, H ₂ flow rate is 2000 cc
As a result, a W film is formed, and the etchback is performed at a Cl ₂ flow rate of 100 cc, a power of 200 W and a pressure of 6 mTorr.

Here, for forming the W film, the semiconductor substrate 10 is used.
Although a WF ₆ gas that reacts extremely well with Si constituting the semiconductor substrate is used, the semiconductor substrate 10 is separated from the contact hole 22 by the conductive film 24. Conductive film 24 of TiN film is excellent in barrier properties against erosion WF _6, WF ₆ molecules 36 does not reach the semiconductor substrate 10 in the holes 30, the junction of the source / drain regions by erosion Breakage can be prevented (Fig. 5).

After that, by forming the wiring layer 28 and performing patterning, a semiconductor device can be formed without causing junction breakage (FIG. 3C). As described above, according to the present embodiment, the holes generated by the isotropic etching of the etching stopper film are spatially isolated by the deposition of the conductive film, so that the W film is formed using the WF ₆ gas. Even at this time, the WF ₆ gas and the semiconductor substrate do not come into direct contact with each other, and it is possible to prevent the junction breakdown due to the erosion of the WF ₆ gas. Thus, the reliability of the semiconductor device can be improved.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, WF ₆
Although the case where the W plug is formed by the CVD method using gas has been shown, the present invention can be applied to the case where the plug 26 is formed of another metal material such as Al or Cu. That is, in the semiconductor device according to the above-described embodiment, the hole 30 generated for isotropically etching the etching stopper film 16 is spatially isolated from the inside of the contact hole 22 by the conductive film 24. Therefore, the plug 26
When Al or Cu is used as the material of the
Since 4 functions as a barrier film that prevents the silicon substrate in the holes 30 and the plug material from directly contacting each other,
It is possible to prevent the junction breakage due to the reaction between the silicon substrate and the plug material.

When Al is used as the plug material, a blanket Al-CVD technique or a selective aluminum CVD technique can be applied. Further, when Cu is used as the plug material, Cu is deposited by the CVD method, or Cu is deposited by the sputtering method and then reflowed to fill the contact hole 22 with Cu, and then the CMP method is used to polish back. As a result, the plug 26 can be formed.

In the above embodiment, the etching stopper film 16 is a SiN film and the insulating film 18 is a SiO ₂ film.
Although films are used, any combination of these films may be used as long as the films can be etched independently by setting etching conditions. Also,
TiN formed by the collimate sputtering method as the conductive film 24
Although the film is used, a laminated film including a TiN film / Ti film may be used. If such a laminated film is used, the semiconductor substrate 1
The contact resistance between 0 and the conductive film 24 can be reduced.

The Ti film can be deposited by the CVD method or the sputtering method. When depositing the Ti film by the sputtering method, it is not always necessary to use the collimating sputtering method. The holes 3 are formed by the TiN film deposited on the Ti film.
The Ti film may be deposited by a normal sputtering method as long as 0 can be completely blocked. Further, instead of using the TiN film, another conductive film having corrosion resistance to the WF ₆ gas can be applied. For example, a W film or the like deposited by the collimate sputtering method can be used.

Further, as the conductive film 24, a material having an effect as a diffusion barrier against Cu and Al, such as WN, is used.
A film, a Ta film, a TaN film, a TiSiN film, a WSiN film or the like can also be used. Although the phosphoric acid aqueous solution was used for etching the SiN film, other etching methods may be used.

Although the blanket W-CVD and the etch-back technique are used when burying W used for the plug 26, W may be buried in the contact hole 22 by the selective tungsten CVD method. Further, the above-mentioned process conditions show one example thereof, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected at all. [A Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

6A and 6B are process sectional views showing the structure of the semiconductor device according to the present embodiment, and FIG. 7 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment. The structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. The semiconductor device according to the present embodiment is characterized in that the holes 30 are filled with the conductive film 24. That is, in the semiconductor device according to the first embodiment shown in FIG. 1, the inside of the contact hole 22 and the hole 30 are spatially separated by depositing the conductive film 24 using the collimating sputtering method.
In the semiconductor device according to the present embodiment, the inside of the hole 30 is filled with the conductive film 24, and the contact hole 2
2 The inside and the semiconductor substrate 10 are separated.

By doing so, erosion during plug formation is prevented. Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, FIG.
Similar to the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 2D, a contact hole 22 is opened in the interlayer insulating film 20.

Next, the conductive film 24 is deposited by the CVD method. As the conductive film, for example, a TiN film can be used. For example, the substrate temperature is set to 50 by the CVD method.
0 ° C., TiCl ₄ flow rate 10 cc, NH ₃ flow rate 500 c
c, the pressure is 100 mTorr, and the deposition is performed. Note that T
The source gas of i is TDMAT (tetrakis dimet
hylamino titanium), TDEAT (tetrakis diethyla)
mino titanium), TiI ₄ or the like may be used. TDMA
When T is used, for example, the substrate temperature is 400 ° C., T
The deposition can be performed with a DMAT flow rate of 2 cc, an NH ₃ flow rate of 10 cc, and a pressure of 100 mTorr. TDE
When AT is used, for example, the substrate temperature is 400 ° C.,
The deposition can be performed with a TDEAT flow rate of 30 cc, a mixed gas flow rate of NH ₃ and Ar of 10 slm, and a pressure of 10 Torr.

Since the CVD method has better coverage than the sputtering method, the holes 3 can be formed by optimizing the film forming conditions.
The inside of 0 can be easily embedded. Therefore, WF
_{The 6} gas has a high barrier effect, and the semiconductor substrate 10 and the contact hole 22 are spatially isolated from each other, and the effect of electrically connecting the semiconductor substrate 10 and the contact hole 22 can be made higher than in the case of the sputtering method.

When the conductive film 24 is formed by using the TiN film formed by the CVD method, in order to fully exert the effect of the present invention, at least a film thickness that closes the opening of the hole 30 is deposited. There is a need to. This film thickness cannot be uniquely determined because it depends on the coverage of the CVD film. However, for example, the height of the opening is 100 nm,
When the TiN film is formed under the above conditions, about 10
A film thickness of 0 nm or more is required.

Conductive film 24 having excellent step coverage
In the case of depositing, the holes 30 can be completely filled by depositing the conductive film 24 having a film thickness of about ½ or more of the film thickness of the etching stopper film 16. After this,
Similar to the method of manufacturing the semiconductor device according to the first embodiment, the plug 26 is formed (FIG. 7B), and the wiring layer 28 is further formed (FIG. 7C).

As described above, according to the present embodiment, the holes formed by the isotropic etching of the etching stopper film are filled with the conductive film, so that W using WF ₆ gas is used.
Even when the film is formed, the WF ₆ gas and the semiconductor substrate do not come into direct contact with each other, and it is possible to prevent the junction breakdown due to the erosion of the WF ₆ gas. Thus, the reliability of the semiconductor device can be improved.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, as the conductive film 24, CV
Although the TiN film formed by the method D is used, any conductive film having corrosion resistance to the WF ₆ gas can be applied.
For example, even if a polycrystalline silicon film or an amorphous silicon film doped with impurities is used, it is sufficient that the WF ₆ does not reach the semiconductor substrate 10.

Further, as in the first embodiment, the structure of the semiconductor device according to the present embodiment can be applied to the method of manufacturing a semiconductor device in which an Al plug or a Cu plug is formed. Further, the above process conditions show an example thereof, and even if these numerical values are changed to appropriate values,
It does not affect the effect of the present invention. [A Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS.

FIG. 8 is a diagram for explaining the buried wiring to which the BLC structure is applied, FIG. 9 is a diagram for explaining the problem in the buried wiring using Cu, and FIG. 10 is a plan view showing the structure of the semiconductor device according to the present embodiment. Sectional views, FIG. 11 and FIG.
Is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment. In the first and second embodiments, the present invention is applied to the case of opening a contact hole on a semiconductor substrate, but the BLC structure according to the present invention can be applied to various underlying structures.

That is, the present invention solves a common problem in the process of burying a conductive material in the opening, and is not limited to the case of forming the plug in the contact hole opened on the semiconductor substrate, and other contacts. It is also effective in a process of filling a hole, for example, a via hole with a plug, a process of forming a buried wiring, or the like.

In this embodiment, the case where the BLC structure is applied to the buried wiring will be described with reference to FIGS. 8 and 9. First, the embedded wiring and the embedded wiring using the BLC structure will be described. With the demand for higher speed LSIs, lower resistance of wiring materials is required. In order to realize this, a novel low resistance material such as Cu (copper) has been studied as a wiring material.

However, since Cu does not generate a reactant having a high vapor pressure, RIE (reactive ion etching: Reactive
It is difficult to use a patterning method utilizing a reaction such as the Ion Etching method, and it is difficult to form fine wiring. Therefore, when forming a wiring using Cu, a groove for wiring is formed in the insulating film in advance, Cu is embedded in the groove by a sputtering method or the like, and Cu on the insulating film is etched back by a CMP method or the like. It is useful to form the wiring embedded in the insulating film by (polishing back).

The above BLC structure can also be applied to the case of forming such a buried wiring. A case where the BLC structure is applied to the embedded wiring will be described with reference to FIG. As shown in FIGS. 8A and 8B, when the contact plug 110 is embedded in the interlayer insulating film 104 formed on the semiconductor substrate 100, the wiring 122 embedded in the interlayer insulating film 116 as an upper layer. To form
A wiring groove 118 in which the wiring 122 is embedded in the interlayer insulating film 116.
It is necessary to prevent the interlayer insulating film 104 from being etched when the etching for forming the film is performed. This is because when the etching reaches the interlayer insulating film 104, the shape of the wiring 122 embedded in the wiring groove 118 is greatly affected (FIG. 8C). When the shape of the wiring 122 is changed in this manner, variations in wiring resistance are increased, and an interlayer breakdown voltage between the wiring 122 and a wiring (not shown) in a lower layer is reduced, which affects reliability of the semiconductor device. It will be.

Therefore, by applying the BLC structure in such a case, it is possible to prevent the interlayer insulating film 104 from being excessively etched. That is, the interlayer insulating film 1
04 and the interlayer insulating film 116, by forming an etching stopper film 112 having a different etching selectivity from these insulating films, the etching of the interlayer insulating film 116 can be stopped by the etching stopper film 112 with good controllability. (FIG.8 (d)).

By doing so, when the wiring groove 118 that embeds the wiring 122 is etched, the influence of the etching does not reach the interlayer insulating film 104, and the wiring 12 is formed.
The shape of 2 is determined only by the thickness of the interlayer insulating film 116, and the wiring can be stably formed. However, when Cu is used as the material for the embedded wiring, it is not preferable to apply the BLC structure as it is.
Hereinafter, the reason will be described.

Even when the buried wiring using Cu is formed, when the etching stopper film 112 is etched as in the case of the normal BLC structure, the interlayer insulating film 104 is formed.
It is preferable to use wet etching in order to secure etching selectivity with the insulating film 114. But,
Since wet etching is isotropic etching,
The etching stopper film 112 under the insulating film 114 is also etched, and a hole 124 is formed under the insulating film 114 (FIG. 9A). Since the holes 124 thus formed cannot be covered by the conventional sputtering method, they remain even after the conductive film 120 is deposited (FIG. 9).
(B)).

Therefore, in the wiring forming process of the next step, C
When u is embedded, Cu is embedded in the holes 124 and Cu diffuses from this portion into the insulating film 114,
Inter-wiring leakage and the dielectric constant of the insulating film may increase (FIG. 9C). As described above, it is not preferable to directly apply the conventional BLC structure to the buried wiring using Cu.

Next, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 10A is a plan view showing the structure of the semiconductor device according to the present embodiment.
FIG. 6B is a sectional view showing the structure of the semiconductor device according to the present embodiment. On the semiconductor substrate 100, an interlayer insulating film 104 having a contact hole 102 opened in a predetermined region is formed. In the contact hole 102, a contact plug 1 including a conductive film 106 and a plug 108.
10 are formed.

The contact plug 110 is the interlayer insulating film 10.
An interlayer insulating film 116 including an etching stopper film 112 and an insulating film 114 is formed on the underlying substrate exposed on the surface 4. A wiring groove 118 for embedding a wiring is formed in the interlayer insulating film 116, and the contact plug 110 is exposed at the bottom of the groove. Wiring groove 118
A conductive film 120 serving as a barrier metal is formed on the inner wall and the interlayer insulating film 104, and a wiring 122 is embedded in the wiring groove 118 in which the conductive film 120 is formed.

Here, the semiconductor device according to the present embodiment is
The etching stopper film 112 near the wiring groove 118 is laterally etched to form a hole 124.
The conductive film 120 formed in the wiring groove 118 is a hole 12
It is characterized in that it is formed so as to completely surround the inside of the wiring groove 118 without interruption in the four portions. Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the interlayer insulating film 104 with the contact plugs 110 embedded therein is formed on the semiconductor substrate 100. The contact plug 110 is connected to an electrode (not shown) of a transistor formed on the semiconductor substrate 100. The interlayer insulating film 104 is formed of, for example, a silicon oxide film. Here, the contact plug 110 may have any structure.

Further, the semiconductor substrate 100 and the interlayer insulating film 10
One or two or more wiring layers may be formed between the wiring layers 4 and 4. That is, the wiring 122 may be the metal wiring of the second layer or the metal wiring of the upper layer. In the present specification, such a base structure will be collectively referred to as a base substrate. That is, not only the semiconductor substrate itself but also a semiconductor substrate on which elements such as transistors are formed and a structure in which one or two or more wiring layers are further formed on the underlying substrate are referred to as the base substrate in this specification. Shall also be included.

Next, an insulating film to be the etching stopper film 112 is deposited on such a base substrate. As the etching stopper film 112, for example, a SiN film can be used. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, the SiH ₄ flow rate is 100 cc, and the NH ₃ flow rate is 50 cc. Subsequently, an insulating film 114 is deposited on the etching stopper film 112, and the etching stopper film 112 and the insulating film 114 are deposited.
To form an interlayer insulating film 116 (FIG. 11).
(A)). As the insulating film 114, for example, a SiO ₂ film can be used. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, and SiH _{4 is used.}
The flow rate is 50 cc and the N ₂ O flow rate is 500 cc.

After that, the wiring groove 118 penetrating the insulating film 114 and reaching the etching stopper film 112 is opened by using the usual lithography technique and anisotropic etching technique (FIG. 11B). At this time, the etching condition is S
By setting the etching rate of the etching stopper film 112 made of SiN film to be sufficiently lower than that of the insulating film 114 made of iO _2, the etching of the wiring groove 118 can be carried out in the interlayer insulating film 104 and the contact plug 11.
It never reaches zero.

Then, the etching stopper film 112 in the wiring groove 118 is removed by isotropic etching (FIG. 1).
1 (c)). As a result, the bottom of the wiring groove 118 reaches the interlayer insulating film 104 or the contact plug 110, and at the same time, the etching stopper film 112 under the insulating film 114 in the vicinity of the wiring groove 118 is etched to form a hole 124. Here, the isotropic etching is performed, for example, at a temperature of 10
It is performed by wet etching using a phosphoric acid aqueous solution having a concentration of 90% at 0 ° C.

Subsequently, a conductive film 120 is formed so as to cover the openings of the holes 124 (FIG. 12A). here,
The conductive film 118 serves as a barrier layer that prevents the wiring material from entering the holes 124 when the wiring material is embedded in a later step, and the interlayer insulating films 104 and 116 and the wiring groove 118 are spatially separated. It has the effect of isolating. Since the conductive film 120 needs to be formed so as to cover at least the opening of the hole 124, the conductive film 12 to be formed.
The film thickness of 0 needs to be at least as high as the opening of the hole 124. Therefore, it is desirable to use the collimate sputtering method for depositing the conductive film 120 (see the first embodiment).

After that, a Cu film is deposited by a sputtering method and reflow is performed to fill the wiring trench 118 with Cu.
For example, Cu is sputtered at a pressure of 1.5 mTorr, a power of 5 kW, an Ar flow rate of 25 sccm, and a temperature of 35
Cu reflow is performed at 0 ° C., Ar flow rate of 1000 sccm, and pressure of 80 Torr. Then, the interlayer insulating film 116
The upper Cu and the conductive film 120 are removed by the CMP method,
The Cu and the conductive film 120 are left only in the wiring groove 118. For example, an alumina-based polishing agent is used, and the rotation speed is 100
CMP is performed at rpm and polishing pressure of 6 psi. Thus, the wiring 122 embedded in the wiring groove 118 is formed (FIG. 12B).

The Cu method may be used for embedding Cu. For example, Cu (PMPS) (HFAC) is introduced at a flow rate of 0.08 g / min and H ₂ as a carrier gas at a flow rate of 300 cc, and is deposited at a temperature of 200 ° C. and a pressure of 200 mTorr. Here, the wiring 122
Although Cu which is easy to diffuse in the silicon oxide film is used as the insulating film, the interlayer insulating film 104 and the insulating film 114 made of the silicon oxide film are isolated from the wiring 122 by the conductive film 120. The conductive film 120 made of a TiN film has an excellent effect as a diffusion barrier of Cu, so that Cu does not diffuse into the interlayer insulating films 104 and 116, and there is a leak between wirings and a dielectric of the interlayer insulating film. It is possible to prevent an increase in the rate.

As described above, according to the present embodiment, the holes 124 formed by the isotropic etching of the etching stopper film 112 are spatially isolated by the deposition of the conductive film 120, so that the Cu in the wiring groove 118 is formed. C when embedded
Since u and the interlayer insulating films 104 and 116 do not come into direct contact with each other, it is possible to prevent leakage between wirings and increase in the dielectric constant of the interlayer insulating film due to diffusion of Cu.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, although the case where the embedded wiring is formed has been described in the above embodiment, it may be applied to the filling of the via hole used for the interlayer connection of the multilayer wiring.
In this case, it can be easily achieved by replacing the wiring groove 118 with a via hole. Further, in the above embodiment, an example in which the conductive film 120 is formed by the collimating sputtering method has been shown, but the conductive film 120 may be deposited by using the CVD method as in the second embodiment. In this case, hole 1
24 can be completely embedded by the conductive film 120.

A material having a diffusion barrier effect on Cu as the conductive film 120, for example, a WN film,
If a Ta film, a TaN film, a TiSiN film, a WSiN film or the like is used, Cu or Al diffuses in the conductive film 120 and the holes 1
It is possible to more effectively prevent reaching within 24. Further, as an example of using wet etching with a phosphoric acid aqueous solution as a method of isotropically etching the etching stopper film 112, when the plug 110 exposed at the bottom of the wiring groove 118 is Al or Cu, dry etching or the like is used. If using anisotropic etching, plug 11
The etching stopper film 112 can be etched without affecting 0. Here, for the isotropic dry etching, for example, the SF ₆ flow rate is set to 12
0 cc, O ₂ flow rate 30 cc, power 200 W, pressure 200 mTorr, temperature 20 ° C.

The above-mentioned process conditions are just an example, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected. [A Fourth Embodiment] The semiconductor device and the method for fabricating the same according to a fourth embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 13 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 14 to 17 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment has the etching stopper film 1
An insulating film 32 is further formed under the layer 6, and the inner diameter of the contact hole 22 formed in the interlayer insulating film 20 changes in the depth direction.

That is, the etching stopper film 16 in the vicinity of the contact hole 22 is laterally etched to have a large inner diameter, but the inner diameter of the insulating film 32 is substantially equal to the inner diameter of the insulating film 18, and the inner diameter of the etching stopper film 16 is substantially the same. It is getting narrower. Contact hole 22
The conductive film 24 formed inside is the etching stopper film 1
Although it is interrupted at the portion of 6, the opening formed in the insulating film 32 is completely covered by the conductive film 24 formed at the bottom of the contact hole 22.
The semiconductor substrate 10 is not exposed inside.

By thus configuring the semiconductor device, it is possible to prevent erosion of the semiconductor substrate 10 by the source gas when forming the plug 26. Next, the method for fabricating the semiconductor device according to the present embodiment will be explained.
The element isolation film 12 having a thickness of about 250 nm is formed on the main surface of the semiconductor substrate 10. Then, in the desired area, the well,
A channel stop layer and a threshold control impurity layer (not shown) are formed.

Then, a gate oxide film 34 having a thickness of about 6 nm is formed by thermal oxidation, and an amorphous silicon film having a thickness of about 200 nm is deposited on the gate oxide film 34 by CVD. Then, P (phosphorus) ions are introduced into the amorphous silicon film in the region where the N-channel transistor is formed, and B is introduced into the amorphous silicon film in the region where the P-channel transistor is formed.
F ₂ (boron fluoride) ions are implanted respectively.

Next, a silicon oxide film having a thickness of about 80 nm is deposited on the amorphous silicon film by the CVD method. Then, photolithography and RIE (Reacti
ve Ion Etching: reactive ion etching)
A gate electrode 40 is formed by patterning a laminated film composed of an amorphous silicon film and a silicon oxide film 38 (FIG. 14A).

After that, impurities are implanted into the semiconductor substrate 10 using the gate electrode as a mask, and LDD (Lightly Doped) is applied.
Drain) is formed. Film thickness of about 100 nm by CVD method
After depositing the silicon oxide film, the side wall 42 is formed on the side wall portion of the gate electrode by etching back. Then, using the gate electrode and the sidewall 42 as a mask, impurities are implanted into the semiconductor substrate 10 to form the source / drain diffusion layer 14.

After that, a heat treatment is performed at 800 ° C. to activate the implanted impurities (FIG. 14B). Next, a Co (cobalt) film having a thickness of about 8 nm and a T (thickness) film having a thickness of about 15 nm are formed.
After continuously depositing the iN film by the sputtering method,
RTA (Rapid Thermal Annealing) is performed at 0 ° C., and C is selectively formed on the source / drain diffusion layers.
An oSi ₂ film 44 is formed.

Subsequently, the TiN film is removed with ammonia hydrogen peroxide and the unreacted Co film is removed with sulfuric acid hydrogen peroxide (FIG. 14 (c)).
In this way, CoS is formed on the source / drain diffusion layer 14.
After the MOS transistor in which the i ₂ film 44 is selectively formed is formed on the semiconductor substrate 10, the insulating film 32 made of a silicon oxide film having a film thickness of about 10 nm and the S film having a film thickness of about 50 nm are formed.
An etching stopper film 16 made of an iN film and a film thickness of about 2
The insulating film 18 made of a 50 nm silicon oxide film and PE
-Deposit by the CVD method. Next, S on the insulating film 18
The OG film 46 is spin-coated to form the interlayer insulating film 20 whose surface is flattened.

Then, a resist film 48 having a pattern of contact holes to be formed is formed on the SOG film 46 by lithography (FIG. 15A). Next, using the resist film as a mask, etching is performed using a mixed gas plasma of C ₄ F ₈ and Ar to process the SOG film 46 and the insulating film 18. At this time, a SiN film is used as the etching stopper film 16, but S of the shoulder portion of the gate electrode is used.
About half of the total thickness of the iN film is consumed (Fig. 15).
(B)).

After removing the resist film 48, it is immersed in a phosphoric acid aqueous solution at 150 ° C. to remove the etching stopper film 16 made of the SiN film. By the etching using phosphoric acid, the selection ratio of the SiN film and the silicon oxide film can be secured at about 50, so that the underlying insulating film 32 is hardly worn. Further, since the etching with phosphoric acid is isotropic, the SiN film is also laterally etched. As a result, the insulating film 18 has an overhang shape and the holes 3
0 is formed (FIG. 16A).

Then, the insulating film 32 made of a silicon oxide film is anisotropically etched by mixed gas plasma of CF ₄ , CHF ₃ and Ar. At the time of etching, since the upper insulating film 18 serves as a mask, only the insulating film 32 immediately below the opening of the overhanging insulating film 18 is removed (FIG. 16B). At this time, by setting the over-etching to about 50% or less, the wear of the sidewalls 42 surrounding the gate electrode can be suppressed sufficiently small, so that a short circuit with the plug 26 formed later can be prevented. In addition, the element isolation film 1 is formed in the contact hole 22.
2 also when there is a boundary between the device region and the device region 1
Since the wear of No. 2 can also be suppressed, a junction short circuit can be prevented.

Thereafter, a film thickness of about 70 n is formed by the sputtering method.
A conductive film 24 of m TiN film is deposited. At this time, the TiN film is deposited on the bottom of the contact hole 22, but is not deposited inside the hole 30. However,
Since the insulating film 32 remains in the holes 30, the semiconductor substrate 10 is not exposed in the contact holes 22 after the conductive film 24 is deposited. Therefore, since the conductive film 24 can be deposited so as to cover the semiconductor substrate 10 even if some overhang occurs when depositing the conductive film 24, a normal sputtering method can be used (FIG. 17).
(A)).

Then, the film thickness is about 600 nm by the CVD method.
W film is deposited. As mentioned above, inside the contact hole
When the W film is deposited, the semiconductor substrate 10 is not exposed.
WF ₆The gas does not come into contact with the semiconductor substrate 10,
Corrosion of the conductor substrate 10 can be prevented. This
In addition, it is possible to prevent the junction from breaking. Then, etch the W film.
Click to leave it only in the contact hole.
Forming the plug 26.

After that, the wiring layer 28 is formed on the upper layer, and if necessary, a wiring layer (not shown) is further formed on the upper layer (FIG. 17B). As described above, according to the present embodiment, by providing the insulating film 32 under the etching stopper film 16, even if the insulating film 18 has an overhang shape, the semiconductor substrate 10 at the bottom of the contact hole 22 is made conductive. Since it can be completely covered with the conductive film 24, the plug 2
It is possible to prevent erosion of the semiconductor substrate during formation of 6.

As a result, when the etching stopper film 16 is removed, an etching method having a high selection ratio can be used. Therefore, even if the SAC structure in which the shoulder of the gate electrode 40 hangs inside the contact hole 22, It is possible to prevent the gate electrode 40 from being exposed by etching the sidewall 42 and the insulating film 38 on the gate electrode 40.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the insulating film 32 immediately below the etching stopper film 16 is made of SiO ₂
Although a film is used, a SiON film may be used. In addition, Si
Although wet etching using a phosphoric acid aqueous solution was used for removing the N film, it is also possible to use fluorine radicals by using down flow of mixed gas plasma of CF ₄ and O ₂ . In this case, a selection ratio of about 10 can be obtained, so that it can be used in the above-described manufacturing method. By further adding chlorine, the selection ratio between the silicon oxide film and the SiN film can be improved to almost infinity.

SF ₆ gas plasma may be used to remove the SiN film. In this case, the selection ratio is slightly reduced to about 5, but the above manufacturing method can be applied by setting the thickness of the insulating film 32 to about 20 nm.
In etching using SF ₆ gas plasma, the etching rate in the vertical direction is faster than that in the horizontal direction.

It is desirable that the film thickness of the insulating film 32 be appropriately set according to the etching conditions of the SiN film. Further, in the above embodiment, CoS is formed on the source / drain diffusion layer 14.
Although the i ₂ film 44 was formed in a self-aligned manner, the CoSi ₂ film 44
The same can be applied to a semiconductor device in which the is not formed.

The above-mentioned process conditions are just one example, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected. [A Fifth Embodiment] The semiconductor device and the method for fabricating the same according to a fifth embodiment of the present invention will be explained with reference to FIGS.

FIG. 18 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 19 and 20 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. In the present embodiment, the case where the semiconductor device and the manufacturing method thereof according to the fourth embodiment are applied to a semiconductor device having embedded wiring will be described. First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG.
18A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 18B is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment.

In addition to the wiring structure shown in the third embodiment, the buried wiring may be used for a local wiring that directly contacts the semiconductor substrate. For example, as shown in FIG. 18A, in the structure in which the gate electrodes 62 and 64 are arranged in parallel on the element region 60, the embedded wiring is used as the wiring 66 connecting the element region 60 and the gate electrode 62. You can

When the BLC structure is applied when forming the wiring groove 68 for embedding the wiring in such a semiconductor device, as in the conventional semiconductor device shown in FIG. Will occur (Fig. 3
9). Therefore, in the semiconductor device according to the present embodiment, the insulating film 32 is further formed below the etching stopper film 16,
The opening width of the wiring groove 68 formed in the interlayer insulating film 20 is changed in the depth direction (FIG. 18B).

That is, although the etching stopper film 16 in the vicinity of the wiring groove 68 is laterally etched to have a large opening width, the inner diameter of the insulating film 32 is substantially equal to the inner diameter of the insulating film 18, and thus the etching stopper film 16 is formed. It is narrower than the inner diameter. The conductive film 24 formed in the wiring groove 68 is interrupted at the etching stopper film 16, but the opening formed in the insulating film 32 is completely covered by the conductive film 24 formed in the bottom of the wiring groove 68. It is covered, and the semiconductor substrate 10 is not exposed in the wiring groove 68.

By constructing the semiconductor device in this way, it is possible to prevent erosion of the semiconductor substrate 10 by the raw material gas when forming the plug 26, and junction breakage due to the reaction between the wiring material and the semiconductor substrate 10. . Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. These process drawings are shown in FIG.
It is the figure which shows the AA 'line cross section in (a).

First, a MOS transistor is formed on the main surface of the semiconductor substrate 10 in the same manner as in the semiconductor device manufacturing method according to the fourth embodiment, for example. At this time, the silicon oxide film 38 in a predetermined region on the gate electrode 62 which will be connected to the wiring 66 in a later step is removed in advance (FIG. 19A).
After the MOS transistor is formed on the semiconductor substrate 10 in this manner, the insulating film 32 made of a silicon oxide film having a film thickness of about 10 nm, the etching stopper film 16 made of a SiN film having a film thickness of about 50 nm, and the film thickness of about 250 nm. And an insulating film 18 made of a silicon oxide film are deposited by PE-CVD. Next, the surface of the insulating film 18 is polished by the CMP method to form the interlayer insulating film 20 whose surface is flattened (FIG. 19B).

Next, the insulating film 18 is processed into the pattern of the embedded wiring to be formed by the usual lithography and etching techniques. The etching of the insulating film 18 is performed by using, for example, mixed gas plasma of C ₄ F ₈ and Ar.
Then, the etching stopper film 16 made of the SiN film is etched. For example, wet etching with a phosphoric acid aqueous solution at 150 ° C. is used. By the etching using phosphoric acid, the selection ratio of the SiN film and the silicon oxide film can be secured at about 50, so that the underlying insulating film 32 is hardly worn. Further, since the etching with phosphoric acid is isotropic, the SiN film is also laterally etched. As a result, the insulating film 18 has an overhang shape and the holes 30 are formed.

Then, the insulating film 32 made of a silicon oxide film is anisotropically etched by mixed gas plasma of CF ₄ , CHF ₃ and Ar. Since the upper insulating film 18 serves as a mask during etching, only the insulating film 32 immediately below the opening of the overhanging insulating film 18 is removed. Thus, the wiring groove 68 in which the source / drain diffusion layer 14 and the gate electrode 62 are exposed is formed (FIG. 19C).

Thereafter, a film thickness of about 70 n is formed by the sputtering method.
A conductive film 24 of m TiN film is deposited. At this time, the TiN film is deposited on the bottom of the wiring groove 68, but is not deposited in the holes 30. However, since the insulating film 32 remains in the holes 30, the semiconductor substrate 10 is not exposed in the wiring groove 68 after the conductive film 24 is deposited. Therefore, since the conductive film 24 can be deposited so as to cover the semiconductor substrate 10 even if some overhang occurs when depositing the conductive film 24, a normal sputtering method can be used (FIG. 20A). ).

Then, a W film is deposited by the CVD method,
W is embedded in the wiring groove 68. For example, if the substrate temperature is 40
0 ° C., pressure 80 Torr, WF ₆ flow rate 20 cc, H ₂
A W film is formed at a flow rate of 2000 cc. Where W
A WF ₆ gas that reacts extremely well with Si forming the semiconductor substrate 10 is used for forming the film, but since the semiconductor substrate 10 is separated from the wiring groove 68 by the conductive film 24, the WF ₆ molecules are separated from the semiconductor substrate. The semiconductor substrate 10 can be prevented from eroding without coming into contact with the semiconductor substrate 10.

Subsequently, the W film on the interlayer insulating film 20 and the conductive film 24 are removed by the CMP method to leave W only in the wiring trench 68. For example, CMP is performed using an alumina-based abrasive at a rotation speed of 50 rpm and a polishing pressure of 6 psi. Thus, the wiring 66 embedded in the wiring groove 68 and connecting the source / drain diffusion layer 14 and the gate electrode 62.
Are formed (FIG. 20 (b)).

As described above, according to the present embodiment, by providing the insulating film 32 under the etching stopper film 16, even when the insulating film 18 has an overhang shape, the semiconductor substrate 10 at the bottom of the wiring groove 68 is formed. Since it is completely covered with the conductive film 24, it is possible to prevent the wiring material from reacting with the semiconductor substrate 10 when forming the wiring 66. Note that the present invention is not limited to the above embodiment, and various modifications are possible.

For example, although W is embedded as the embedded wiring in the above embodiment, the wiring 66 may be formed by embedding Cu. However, in this case, it is better to form the conductive film 24 by using the collimating sputtering method as shown in the first embodiment or the CVD method as shown in the second embodiment in order to suppress the diffusion of Cu. It is effective. Alternatively, Al may be used as the embedded wiring. Also in this case, the reaction between Al and the semiconductor substrate 10 can be prevented.

The above-mentioned process conditions are just one example, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected at all. [A Sixth Embodiment] The semiconductor device and the method for fabricating the same according to a sixth embodiment of the present invention will be explained with reference to FIGS.

FIG. 21 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 22 and 23 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. As shown in FIG. 36, if a hole 138 is formed under the interlayer insulating film 134 when a via hole is formed on the embedded wiring 122, the source gas of the plug 142 and the embedded wiring 122 are filled when the via hole is filled with the plug. And hole 138
Since the high resistance reaction product 146 is generated by the reaction inside, the contact characteristics may be deteriorated.

In this embodiment, a semiconductor device and a method of manufacturing the same which solve the above problems are provided. The semiconductor device according to the present embodiment is characterized in that the interlayer insulating film 134 formed on the embedded wiring 122 has the same structure as the interlayer insulating film according to the fourth embodiment. That is, in the semiconductor device according to the present embodiment, the insulating film 128 is further provided under the etching stopper film 130 in the via hole of the BLC structure, and the wiring 122 embedded in the via hole has the insulating film inside the hole 138. 12
8 separates it from the contact plug 144.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, the interlayer insulating film 114 is formed on the semiconductor substrate 100 in the same manner as, for example, the method for manufacturing the semiconductor device according to the third or fifth embodiment.
The wiring 122 embedded in is formed (FIG. 22).
(A)).

Then, on the underlying substrate in which the wiring 122 is embedded in this way, an insulating film 128 made of a silicon oxide film having a film thickness of about 10 nm, an etching stopper film 130 made of a SiN film having a film thickness of about 50 nm, and a film are formed. Thickness about 700nm
And an insulating film 132 made of a silicon oxide film of PE-CV
An interlayer insulating film 134 including the insulating film 128, the etching stopper film 130, and the insulating film 132 is formed by depositing by the D method.

Then, the surface of the interlayer insulating film 134 is subjected to CMP.
By polishing to flatten the surface (FIG. 22).
(B)). After that, the via hole 136 formed on the wiring 122 is formed by ordinary lithography and etching.
Open. First, the insulating film 132 is processed by etching with mixed gas plasma of C ₄ F ₈ and Ar.

Next, the etching stopper film 130 in the via hole 136 is immersed in a phosphoric acid aqueous solution at 150 ° C.
Is removed. By etching using phosphoric acid, a selection ratio of the SiN film and the silicon oxide film can be secured at about 50, so that the underlying insulating film 128 is hardly worn.
In addition, since etching with phosphoric acid is isotropic, Si
The N film is also laterally etched. As a result, the insulating film 132 has an overhang shape and the holes 138 are formed.

Subsequently, the insulating film 128 made of a silicon oxide film is anisotropically etched by a mixed gas plasma of CF ₄ , CHF ₃ and Ar. Since the upper insulating film 128 serves as a mask during etching, only the insulating film 128 immediately below the opening of the overhanging insulating film 132 is removed (FIG. 22C). After that, a conductive film 140 made of a TiN film having a film thickness of about 70 nm is deposited by a sputtering method. At this time, the conductive film 140 is deposited on the bottom of the via hole, but is not deposited inside the hole 138. However, the insulating film 128 is formed in the holes 138.
Remains, the wiring 122 is not exposed in the via hole 136 after the conductive film 140 is deposited. Therefore, even if some overhang occurs when depositing the conductive film 140, the conductive film 140 is covered so as to cover the wiring 122.
Therefore, a normal sputtering method can be used (FIG. 23A).

Then, a film thickness of about 600 nm is formed by the CVD method.
W film is deposited. As described above, since the wiring 122 is not exposed in the via hole 136, the WF is deposited when the W film is deposited.
_{6 The} gas does not come into contact with the wiring 122. Therefore, C
Since the wiring made of u and the WF ₆ gas do not react with each other to form a high resistance reaction product, the contact characteristics between the wiring 122 and the W film can be kept good.

Then, the W film is etched back to remain only in the via hole 136 to form a contact plug 144 (FIG. 23B). As described above, according to the present embodiment, by providing the insulating film 128 under the etching stopper film 130, even if the insulating film 132 has an overhang shape, the wiring 122 in the via hole 136 has a conductive film. Since it is completely covered with 140, the raw material gas of the plug does not react with the wiring 122 when forming the plug 142. As a result, contact reliability between the contact plug 144 and the wiring 122 can be improved.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, although the case where the contact plug 144 is formed on the embedded wiring 122 has been described in the above embodiment, the present invention can also be applied to the case where the embedded wiring is formed on the contact plug. The present invention prevents the conductive material exposed in the holes 138 from adversely affecting the contact characteristics due to the reaction with the source gas of CVD or the wiring material of the upper layer. It can be applied in a wiring structure.

In the above embodiment, the problem is solved by providing the insulating film 128 under the etching stopper film 130. However, the structure of the semiconductor device according to the first or second embodiment is applied, and the conductive film 140 is used to form the via hole. Thirteen
6 and the holes 138 are spatially isolated from each other, or the conductive film 14
0 may be completely embedded in the hole 138. Further, the above-mentioned process conditions show one example thereof, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected at all. [A Seventh Embodiment] The semiconductor device and the method for fabricating the same according to a seventh embodiment of the present invention will be explained with reference to FIGS.

FIG. 24 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 25 and 26 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. As shown in FIG. 34, the interlayer insulating film 2 on the semiconductor substrate 200
In the semiconductor device having the wiring 210 connected to the contact plug 208 embedded in 02, the wiring 210
When the BLC structure is applied when opening the via hole connected to the contact plug 2, the contact plug 2 is formed in the hole 224 formed when the etching stopper film 216 is etched.
30 and the contact plug 208 were sometimes short-circuited.

In this embodiment, a semiconductor device and a method of manufacturing the same for reducing the above-mentioned short circuit between plugs are provided. The semiconductor device according to the present embodiment is characterized in that the insulating film 214 is further provided below the etching stopper film 216. That is, the upper interlayer insulating film 220 filling the contact plug 230 is composed of the insulating film 214, the etching stopper film 216, and the insulating film 218, and the contact plug 230 filled in the via hole is in the hole 224. It is insulated from the contact plug 208 by the insulating film 214.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. First, for example, similarly to the method of manufacturing the semiconductor device according to the third embodiment, the interlayer insulating film 202 in which the contact plugs 208 are embedded is formed on the semiconductor substrate 200.

Next, on the inter-layer insulation film 202 with the contact plugs 208 buried in, a wiring layer composed of a wiring 210 made of, for example, Al and a conductive film 212 made of, for example, TiN is formed (FIG. 25 (a)). )). The conductive film 212 functions as an antihalation film when patterning the wiring 210 and / or as an electromigration prevention film.

Subsequently, an insulating film 214 made of a silicon oxide film having a film thickness of about 10 nm, an etching stopper film 216 made of a SiN film having a film thickness of about 50 nm, are formed on the base substrate on which the wiring 210 is formed in this manner. An insulating film 218 made of a silicon oxide film having a thickness of about 700 nm is formed by PE-CVD.
Then, the interlayer insulating film 220 including the insulating film 214, the etching stopper film 216, and the insulating film 218 is formed by the method.

After that, the surface of the interlayer insulating film 220 is subjected to CMP.
Method, and the surface is flattened (FIG. 25).
(B)). Then, a via hole 222 formed on the wiring 210 by usual lithography and etching.
Open. First, etching with mixed gas plasma of C ₄ F ₈ and Ar is performed to process the insulating film 218. Then, the via hole 2 was immersed in a phosphoric acid aqueous solution at 150 ° C.
The etching stopper film 216 in 22 is removed. The etching using phosphoric acid can secure a selection ratio of about 50 between the SiN film and the silicon oxide film, so that the underlying insulating film 2
Almost no wear of 14 is seen. Further, since the etching with phosphoric acid is isotropic, the SiN film is also laterally etched. As a result, the insulating film 218 has an overhang shape and a hole 224 is formed.

After that, the insulating film 214 made of a silicon oxide film is anisotropically etched by mixed gas plasma of CF ₄ , CHF ₃ and Ar. Since the upper insulating film 218 serves as a mask during etching, only the insulating film 214 immediately below the opening of the overhanging insulating film 218 is removed (FIG. 25C). At this time, holes 2
Even when 24 extends over the contact plug 208, the contact plug 208 is not exposed in the via hole 222 because the insulating film 214 is formed in the hole 224.

Then, a film thickness of about 70 n is formed by the sputtering method.
m, a conductive film 226 of a TiN film is deposited (FIG. 2).
6 (a)). Then, the film thickness is about 600 nm by the CVD method.
W film is deposited. As described above, since the contact plug 208 is not exposed in the via hole 222, the W film and the contact plug 208 will not be short-circuited.

After that, the W film is etched back and left only in the via hole 222 to form the contact plug 230 (FIG. 26B). As described above, according to the present embodiment, by providing the insulating film 214 below the etching stopper film 216, the contact plug 208 is exposed below the hole 224 even when the insulating film 218 has an overhang shape. Therefore, the short circuit between the contact plug 230 and the contact plug 208 can be reduced as compared with the conventional semiconductor device.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, although the problem is solved by providing the insulating film 214 under the etching stopper film 216 in the above embodiment, the structure of the semiconductor device according to the first embodiment is applied and the via hole 2 is formed by the conductive film 226.
22 and the hole 224 may be spatially completely blocked.

The above-mentioned process conditions are just an example, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected at all. [Eighth Embodiment] The semiconductor device and the method for fabricating the same according to an eighth embodiment of the present invention will be explained with reference to FIGS.

FIG. 27 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 28 and 29 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. In the fourth to seventh embodiments, the structure in which the insulating film is further provided below the etching stopper film is applied to the interlayer insulating film. However, if this structure is applied to the case where the embedded wiring is formed on the interlayer insulating film, the wiring groove is formed. It is also possible to facilitate the etching for forming.

In this embodiment, the case where the structure of the interlayer insulating film according to the fourth embodiment is applied to the structure of the semiconductor device according to the third embodiment will be described. The semiconductor device according to the present embodiment is characterized in that, in the semiconductor device according to the third embodiment shown in FIG. 10, an insulating film 126 made of a silicon oxide film is further formed under the etching stopper film 112.

By providing the insulating film 126 in this manner, the etching process for forming the wiring groove 118 in which the wiring 122 is embedded can be facilitated. Next, the method for fabricating the semiconductor device according to the present embodiment will be explained. First, for example, in the same manner as the method for manufacturing the semiconductor device according to the third embodiment, the contact plug 1 is formed on the semiconductor substrate 100.
An interlayer insulating film 104 in which 10 is embedded is formed (FIG. 2).
8 (a)).

Then, on such a base substrate, an insulating film 126 made of a SiO ₂ film having a film thickness of about 10 nm and an etching stopper film 11 made of a SiN film having a film thickness of about 50 nm are formed.
2 are sequentially deposited. Then, the etching stopper film 11
Insulating film 1 made of SiO ₂ film with a thickness of about 250 nm on ₂
14 is deposited, the insulating film 126, the etching stopper film 1
An interlayer insulating film 116 including the insulating film 114 and the insulating film 114 is formed (FIG. 28B).

After that, a wiring groove 118 penetrating the insulating film 114 and reaching the etching stopper film 112 is opened by using a normal lithography technique and an anisotropic etching technique. At this time, the etching stopper film 112 is almost etched by setting the etching conditions so that the etching rate of the etching stopper film 112 made of the SiN film is sufficiently lower than that of the insulating film 114 made of SiO _2. Instead, the wiring groove 118 can be opened up to the etching stopper film 112.
For the etching of the insulating film 114, for example, reactive ion etching using a mixed gas plasma of C ₄ F ₈ and Ar is used, and the selection ratio to the etching stopper film 112 is 20.
It is desirable to carry out the above conditions.

Subsequent to the etching of the insulating film 114, the etching stopper film 112 is etched up to the insulating film 126. At this time, the etching conditions are set so that the etching rate of the film insulating film 126 made of SiO ₂ is sufficiently small with respect to the etching stopper film 112 made of SiN film, so that the insulating film 126 is almost etched. Without wiring groove 118 with insulating film 126
It can be opened to the top (FIG. 28 (c)). The etching of the etching stopper film 112 is preferably performed, for example, by reactive ion etching using SF ₆ and O ₂ , under the condition that a selection ratio of 3 or more with respect to the insulating film 126 can be secured.

In the conventional structure shown in FIG. 35, since the underlying interlayer insulating film 104 and the contact plug 110 are exposed by this etching, the etching stopper film 112 is formed.
Although the etching conditions are set by the trade-off between the etching selection ratios of the two with respect to the above, in the structure of the semiconductor device according to the present embodiment, only the selection ratio of the insulating film 126 with respect to the etching stopper film 112 may be considered, and the wiring groove 118 It can be easily opened.

Next, the insulating film 126 in the wiring groove 118 is etched to form the contact plug 11 in the wiring groove 116.
Expose 0. At this time, since the interlayer insulating film 104 is exposed in the wiring trench 118, the interlayer insulating film 104 is also etched at the same time as the etching of the insulating film 126. Even if the etching amount is taken into consideration, the film loss of the interlayer insulating film 104 due to the etching of the insulating film 126 is sufficiently small. Therefore, there is a level difference that affects the contact characteristics.
It does not occur inside (FIG. 29 (a)).

Since the insulating film 126 can be etched with a sufficient selection ratio with respect to the contact plug 110, the contact plug 110 is not etched. Then, the conductive film 12 connected to the contact plug 110 is formed on the inner wall and the bottom surface of the wiring groove 118.
Form 0.

After that, a Cu film is deposited by a sputtering method and reflow is performed to fill the wiring trench 118 with Cu.
For example, Cu is sputtered at a pressure of 1.5 mTorr, a power of 5 kW, an Ar flow rate of 25 sccm, and a temperature of 35
Cu reflow is performed at 0 ° C., Ar flow rate of 1000 sccm, and pressure of 80 Torr. Then, the interlayer insulating film 116
The upper Cu is removed by the CMP method to leave Cu only in the wiring groove 118. For example, using an alumina-based abrasive, the rotation speed is 100 rpm, and the polishing pressure is 6 psi.
Perform P. Thus, the wiring 120 embedded in the wiring groove 116 is formed (FIG. 29B).

As described above, according to the present embodiment, when the wiring 120 embedded in the interlayer insulating film 116 is formed on the interlayer insulating film 104 in which the contact plug 110 is embedded, the wiring is further formed below the etching stopper film 110. Insulating film 12
Since the BLC structure having 4 is used, the contact plug and the interlayer insulating film 104 are not etched when the etching stopper film 110 is etched. As a result, the contact characteristics between the contact plug and the wiring 120 can be improved, and at the same time, the reliability of the semiconductor device can be improved.

The above-mentioned process conditions are just one example, and even if these numerical values are changed to appropriate values, the effect of the present invention is not affected at all.

[0149]

As described above, according to the present invention, the base substrate, the first insulating film formed on the base substrate, and the second insulating film formed on the first insulating film are formed. An interlayer insulating film having an opening reaching the base substrate and a conductive film formed on the inner wall and bottom of the opening are provided, and the opening width of the opening formed in the first insulating film is set to the second width. The opening width of the opening formed in the insulating film is made wider so that the conductive film formed on the inner wall of the opening and the conductive film formed at the bottom of the opening are continuous at the boundary. With this configuration, when the conductive material is embedded in the opening, it is possible to prevent erosion of the base substrate by the source gas of the conductive material and reaction between the conductive material and the base substrate. Thereby, the reliability of the semiconductor device can be improved.

If the conductive film is embedded in the opening formed in the first insulating film below the second insulating film, the base substrate can be isolated from the opening. Further, the base substrate, the interlayer insulating film formed on the base substrate and having an opening having a different opening width depending on the depth, and the conductive film formed on the inner wall and the bottom of the opening are provided. Since the opening width of the bottom of the substrate is almost equal to the minimum opening width of the opening and the semiconductor device is configured so that the base substrate at the bottom of the opening is covered with the conductive film, the base substrate is completely formed by conductive film formation. It can be isolated from within the opening. Accordingly, when the conductive material is embedded in the opening, it is possible to prevent erosion of the base substrate by the source gas of the conductive material and reaction between the conductive material and the base substrate.

In the above semiconductor device, the first insulating film formed on the base substrate, the second insulating film formed on the first insulating film, and the second insulating film formed on the second insulating film. The third formed
And the opening width of the opening formed in the second insulating film is wider than the opening width of the opening formed in the third insulating film. An interlayer insulating film in which the opening width of the opening is approximately equal to the opening width of the opening formed in the third insulating film can be applied.

The structure of the semiconductor device described above can be applied to any wiring layer in the multilayer wiring structure having a plurality of wiring layers. A first insulating film deposition step of depositing a first insulating film on the base substrate;
A second insulating film deposition step of depositing a second insulating film having a different etching characteristic from that of the first insulating film on the second insulating film;
Is anisotropically etched to form an opening reaching the first insulating film, and the first insulating film in the opening is also laterally etched. By removing the first opening under the second insulating film at the same time as opening the opening up to the base substrate.
A second opening forming step of etching the insulating film to form a void, and preventing the underlying substrate from being exposed in the opening,
By manufacturing a semiconductor device by a conductive film deposition step of depositing a conductive film that closes at least the opening of the void in the opening, the inside of the opening and the underlying substrate can be completely separated by conductive film formation. This prevents the source gas of the conductive material from eroding the base substrate or reacting the base substrate with the conductive material when the conductive material is embedded in the opening in a later step. Thereby, the reliability of the semiconductor device can be improved.

In the method of manufacturing a semiconductor device described above, if the conductive film is deposited by the collimating sputtering method, the opening of the void can be easily closed. Further, in the above-described method for manufacturing a semiconductor device, if the conductive film is deposited such that the thickness of the conductive film at the bottom of the opening is larger than that of the first insulating film, the opening of the void can be easily formed. Can be closed.

In the method of manufacturing a semiconductor device described above, if the conductive film is deposited by the CVD method, the conductive film can be embedded in the void. In the method for manufacturing a semiconductor device described above, if the conductive film is deposited so that the film thickness of the conductive film at the bottom of the opening is ½ or more of the film thickness of the first insulating film, the gap The opening can be easily embedded.

In addition, a first insulating film deposition step of depositing a first insulating film on a base substrate, and a second insulating film having an etching characteristic different from that of the first insulating film on the first insulating film. A second insulating film deposition step of depositing, a third insulating film deposition step of depositing a third insulating film having a different etching characteristic from that of the second insulating film on the second insulating film, and a third insulating film A first opening forming step of forming an opening reaching the second insulating film by anisotropically etching the film, and a method of laterally etching the second insulating film in the opening. By removing the first insulating film in the opening by anisotropic etching of the first insulating film in the opening. And a third opening forming step of opening up to The conductive film depositing step of depositing a conductive layer to cover the substrate by manufacturing a semiconductor device, it is possible to completely isolate the opening portion and the base substrate by a conductive film formation. Accordingly, even when the second insulating film needs to be isotropically etched to use the SAC structure, it is possible to prevent substrate erosion due to the source gas when the conductive material is embedded. Further, it is possible to prevent the reaction between the conductive material and the base substrate.

In the method of manufacturing a semiconductor device described above, if the over-etching amount when etching the first insulating film is set to about 50% or less, the damage to the base substrate is suppressed and the opening is formed. be able to. Further, the method for manufacturing a semiconductor device according to the present invention can be applied to any wiring layer formed in a multilayer wiring structure having a plurality of wiring layers.

In addition, a first insulating film deposition step of depositing a first insulating film on a base substrate, and a first insulating film thicker than the first insulating film on the first insulating film and having an etching characteristic Second insulating film deposition step of depositing a second insulating film having a different thickness, and a third insulating film having a different etching characteristic from that of the second insulating film on the second insulating film. Third to deposit
Of the insulating film, the third insulating film is etched using the second insulating film as a stopper to form an opening reaching the second insulating film, and the first opening in the opening is formed. Etching the second insulating film using the first insulating film as a stopper to form a second opening forming an opening up to the first insulating film; and etching the first insulating film in the opening, By manufacturing the semiconductor device by the third opening forming step of opening the opening to the base substrate, the opening can be formed while reducing the influence on the base substrate.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating the principle of a collimate sputtering method.

FIG. 5 is a diagram illustrating effects in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a process sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating embedded wiring to which a BLC structure is applied.

FIG. 9 is a diagram for explaining a problem in embedded wiring using Cu.

FIG. 10 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a process sectional view (1) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a schematic sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 14 is a process sectional view (1) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 15 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 16 is a process sectional view (3) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention.

FIG. 17 is a process sectional view (4) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 18 is a plan view and a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 19 is a process sectional view (1) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 20 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the invention.

FIG. 21 is a schematic sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 22 is a process sectional view (1) showing the method of manufacturing the semiconductor device according to the sixth embodiment of the invention.

FIG. 23 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the invention.

FIG. 24 is a schematic sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 25 is a process sectional view (1) illustrating the method of manufacturing the semiconductor device according to the seventh embodiment of the invention.

FIG. 26 is a process cross-sectional view (2) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 27 is a schematic cross-sectional view showing the structure of the semiconductor device according to the eighth embodiment of the present invention.

FIG. 28 is a process sectional view (1) illustrating the method for manufacturing the semiconductor device according to the eighth embodiment of the invention.

FIG. 29 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the eighth embodiment of the invention.

FIG. 30 is a diagram illustrating a structure of a conventional semiconductor device having a SAC structure.

FIG. 31 is a diagram illustrating a structure of a conventional semiconductor device having a BLC structure.

FIG. 32 is a diagram (part 1) explaining a problem of the conventional semiconductor device.

FIG. 33 is a diagram (part 2) explaining a problem of the conventional semiconductor device.

FIG. 34 is a diagram (part 3) explaining a problem of the conventional semiconductor device.

FIG. 35 is a diagram (No. 4) explaining a problem of the conventional semiconductor device.

FIG. 36 is a diagram (No. 5) for explaining the problem of the conventional semiconductor device.

FIG. 37 is a diagram (No. 6) explaining a problem of the conventional semiconductor device.

FIG. 38 is a diagram (No. 7) explaining a problem of the conventional semiconductor device.

FIG. 39 is a diagram (No. 8) for explaining the problem of the conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... Element isolation film 14 ... Diffusion layer 16 ... Etching stopper film 18 ... Insulating film 20 ... Interlayer insulating film 22 ... Contact hole 24 ... Conductive film 26 ... Plug 28 ... Wiring layer 30 ... Hole 32 ... Insulation Film 34 ... Gate oxide film 36 ... WF ₆ molecule 38 ... Insulating film 40 ... Gate electrode 42 ... Sidewall 44 ... CoSi ₂ film 46 ... SOG film 48 ... Resist film 50 ... Target 52 ... Substrate 54 ... Collimator 60 ... Element region 62 ... gate electrode 64 ... gate electrode 66 ... wiring 68 ... wiring groove 100 ... semiconductor substrate 102 ... contact hole 104 ... interlayer insulating film 106 ... conductive film 108 ... plug 110 ... contact plug 112 ... etching stopper film 114 ... insulating film 116 ... Interlayer insulating film 118 ... Wiring groove 120 ... Conductive film 122 ... Wiring 12 ... Void 126 ... Insulating film 128 ... Insulating film 130 ... Etching stopper film 132 ... Insulating film 134 ... Interlayer insulating film 136 ... Via hole 138 ... Void 140 ... Conductive film 142 ... Plug 144 ... Contact plug 146 ... High resistance reactant 200 ... Semiconductor substrate 202 ... Interlayer insulating film 204 ... Conductive film 206 ... Plug 208 ... Contact plug 210 ... Wiring 212 ... Conductive film 214 ... Insulating film 216 ... Etching stopper film 218 ... Insulating film 220 ... Interlayer insulating film 222 ... Via hole 224 ... Holes 226 ... Conductive film 228 ... Plug 230 ... Contact plug

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H05H 1/46 H01L 21/88 F

Claims (14)

[Claims] 1. A base substrate, a first insulating film formed on the base substrate, and the first insulating film.
An insulating film formed of a second insulating film formed on the insulating film and having an opening reaching the base substrate, and a conductive film formed on an inner wall and a bottom of the opening. The opening width of the opening formed in the first insulating film is
The opening is wider than the opening formed in the second insulating film, and the conductive film formed on the inner wall of the opening and the conductive film formed on the bottom of the opening are boundaries. A semiconductor device characterized by being continuous with each other. 2. The semiconductor device according to claim 1, wherein the conductive film is buried under the second insulating film in the opening formed in the first insulating film. Semiconductor device. 3. A base substrate, an interlayer insulating film formed on the base substrate and having an opening having a different opening width depending on the depth, and a conductive film formed on an inner wall and a bottom of the opening. The opening width of the bottom of the opening is substantially equal to the minimum opening width of the opening, and the base substrate at the bottom of the opening is covered with the conductive film. Semiconductor device. 4. The semiconductor device according to claim 3, wherein the interlayer insulating film is a first insulating film formed on the underlying substrate, and a second insulating film formed on the first insulating film. A film and a third insulating film formed on the second insulating film, and an opening width of the opening formed in the second insulating film is
The opening width of the opening formed in the first insulating film is wider than the opening width of the opening formed in the third insulating film.
A semiconductor device having a width substantially equal to an opening width of the opening formed in the third insulating film. 5. The semiconductor device according to claim 1, wherein the base substrate further has at least one wiring layer. 6. A first insulating film deposition step of depositing a first insulating film on a base substrate, and a second insulating film having an etching characteristic different from that of the first insulating film on the first insulating film. A second insulating film deposition step of depositing the second insulating film, and anisotropically etching the second insulating film,
A first opening forming step of forming an opening reaching the first insulating film; and removing the first insulating film in the opening by a method in which etching also proceeds in a lateral direction, At the same time as opening the opening to the base substrate, the second
A second opening forming step of forming a void by etching the first insulating film under the insulating film, and conductive for closing at least the opening of the void so that the underlying substrate is not exposed in the opening. Conductive film deposition step of depositing a conductive film in the opening. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the conductive film depositing step, the conductive film is deposited by a collimating sputtering method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the conductive film deposition step, the film thickness of the conductive film at the bottom of the opening is larger than that of the first insulating film. A method of manufacturing a semiconductor device, comprising depositing the conductive film as described above. 9. The method of manufacturing a semiconductor device according to claim 6, wherein in the conductive film depositing step, the conductive film is deposited by a CVD method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the conductive film deposition step, a film thickness of the conductive film at a bottom of the opening is equal to a film thickness of the first insulating film. 1 /
A method of manufacturing a semiconductor device, characterized in that the conductive film is deposited so as to have two or more. 11. A first insulating film deposition step of depositing a first insulating film on a base substrate, and a second insulating film having etching characteristics different from those of the first insulating film on the first insulating film. A second insulating film depositing step of depositing a film, and a third insulating film depositing step of depositing a third insulating film having a different etching characteristic from that of the second insulating film on the second insulating film, By anisotropically etching the third insulating film,
A first opening forming step of forming an opening reaching the second insulating film; and removing the second insulating film in the opening by a method in which etching also proceeds in a lateral direction, A second opening forming step of opening the opening to the first insulating film; and anisotropically etching the first insulating film in the opening to bring the opening to the base substrate. A method of manufacturing a semiconductor device, comprising: a third opening forming step of forming an opening; and a conductive film depositing step of depositing a conductive film so as to cover at least the underlying substrate exposed in the opening. 12. The method of manufacturing a semiconductor device according to claim 11, wherein in the third opening forming step, an overetching amount when etching the first insulating film is set to about 50% or less. A method for manufacturing a semiconductor device, comprising: 13. The method of manufacturing a semiconductor device according to claim 6, wherein the base substrate further has at least one wiring layer. 14. A first insulating film deposition step of depositing a first insulating film on a base substrate, and a first insulating film thicker than the first insulating film on the first insulating film. A second insulating film deposition step of depositing a second insulating film having different etching characteristics, and a second insulating film thicker than the second insulating film on the second insulating film, A third insulating film deposition step of depositing a different third insulating film; and etching the third insulating film with the second insulating film as a stopper to form an opening reaching the second insulating film. Forming a first opening, and etching the second insulating film in the opening using the first insulating film as a stopper to form the opening in the first opening.
A second opening forming step of opening to above the insulating film; and a third opening forming step of etching the first insulating film in the opening to open the opening to above the underlying substrate, A method of manufacturing a semiconductor device, comprising: