KR100365412B1 - Method for forming metal line of semicoductor device - Google Patents
Method for forming metal line of semicoductor device Download PDFInfo
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- KR100365412B1 KR100365412B1 KR1020000084497A KR20000084497A KR100365412B1 KR 100365412 B1 KR100365412 B1 KR 100365412B1 KR 1020000084497 A KR1020000084497 A KR 1020000084497A KR 20000084497 A KR20000084497 A KR 20000084497A KR 100365412 B1 KR100365412 B1 KR 100365412B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판상에 층간절연막을 형성하는 단계; 상기 층간절연막과 반도체기판을 패터닝하여 배선 콘택을 형성하는 단계; 상기 배선콘택에 실리콘층을 형성하는 단계; 상기 실리콘층 상에 배선금속층을 형성하는 단계; 실리사이드용 열처리공정을 실시하여 배선금속층 과 실리콘층을 금속실리사이드화하는 단계;를 포함하여 이루어진다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor substrate; Patterning the interlayer insulating film and the semiconductor substrate to form a wiring contact; Forming a silicon layer on the wiring contact; Forming a wiring metal layer on the silicon layer; And performing a silicide heat treatment process to metallize the wiring metal layer and the silicon layer.
Description
본 발명은 반도체소자의 콘택배선에 관한 것으로, 보다 상세하게는 콘택 저항을 감소시켜 고집적소자에 적합하도록한 반도체소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to contact wiring of semiconductor devices, and more particularly, to a method of forming metal wirings of semiconductor devices in which contact resistance is reduced to be suitable for highly integrated devices.
종래 콘택배선 형성 방법에 있어서는, 콘택형성후 실리사이드 형성을 위한금속막과 확산방지막을 형성한 후 실리사이드 열처리 및 플러그와 배선금속을 증착하는 것으로 배선형성을 완료한다.In the conventional contact wiring forming method, after forming a contact, a metal film for forming a silicide and a diffusion barrier layer are formed, and then silicide heat treatment and deposition of a plug and a wiring metal are completed.
이 경우, 첫째 콘택창의 면적이 작아지면서 이 비율 이상으로 콘택저항이 증가하고, 둘째 콘택 식각시 실리콘 기판이 식각되어 실리사이드를 형성할 때 실리사이드와 실리콘 기판과의 접촉면이 도펀트 농도가 낮은 위치에서 존재하게 되어 콘택저항을 증가시키는데 기여하게 된다.In this case, as the area of the first contact window decreases, the contact resistance increases more than this ratio, and when the silicon substrate is etched to form silicide during the etching of the contact, the contact surface between the silicide and the silicon substrate is present at a low dopant concentration. This contributes to increasing the contact resistance.
또한, 셋째 접합부(metallurgical junction)와 실리사이드 계면이 서로 가까워져 접합누설 전류가 커지는 등의 문제점이 있다.In addition, the third junction (metallurgical junction) and the silicide interface is close to each other there is a problem such as a large junction leakage current.
최근에는 이러한 문제를 개선시키기 위한 방법으로 화학증착법에 의한 실리사이드 형성 금속 증착 방법, 로직 반도체 소자와 마찬가지로 실리사이드를 형성하고자 하는 방법이 제안되고 있다.Recently, as a method for improving such a problem, a silicide-forming metal deposition method by chemical vapor deposition and a method for forming silicides like a logic semiconductor device have been proposed.
그러나, 상기 화학증착법에 의한 실리사이드 형성 방법의 경우, 작은 콘택창에서 실리사이드를 형성시킬 수 있어 상기 콘택창의 면적이 작아서 콘택저항이 증가하는 문제를 개선할 수 있으나, 그 한계를 근본적으로 해결할 수는 없다.However, in the case of the silicide formation method by the chemical vapor deposition method, silicide can be formed in a small contact window, and the area of the contact window is small, thereby improving the problem of increasing contact resistance, but the limitation cannot be fundamentally solved. .
특히, 실리사이드를 적용할 경우, 콘택저항은 해결할 수 있으나, 접합누설 전류가 커지고 새로운 공정 적용에 따른 패터닝 공정에 부담이 될 개연성이 있다.In particular, when the silicide is applied, the contact resistance can be solved, but there is a possibility that the junction leakage current becomes large and the burden on the patterning process according to the new process is applied.
이에 본 발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, 콘택저항을 감소시켜 고집적 반도체소자에 적합한 반도체소자의 콘택배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming contact wiring of a semiconductor device suitable for a highly integrated semiconductor device by reducing contact resistance.
도 1a 및 도 1b은 본 발명의 일실시예에 따른 반도체소자의 콘택배선 형성방법을 설명하기 위한 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to an embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 다른 실시예에 따른 반도체소자의 콘택배선 형성방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to another embodiment of the present invention.
[도면부호의설명][Description of Drawing Reference]
31, 41, 51 : 반도체기판 32, 42, 52 : 층간절연막31, 41, 51: semiconductor substrate 32, 42, 52: interlayer insulating film
34 : 도프트 또는 언도프트 에피텍셜실리콘층34: dope or undoped epitaxial silicon layer
35 : 금속배선층35 metal wiring layer
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성 방법은, 반도체기판상에 층간절연막을 형성하는 단계; 상기 층간절연막과 반도체 기판을 패터닝하여 배선콘택을 형성하는 단계; 상기 배선콘택에 실리콘층을 형성 하는 단계; 상기 실리콘층상에 배선금속층을 형성하는 단계; 실리사이드용 열처리 공정을 실시하여 배선금속층과 실리콘층을 금속실리사이드화하는 단계;를 포함하여 이루어지는 것을 특징으로한다.According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming an interlayer insulating film on a semiconductor substrate; Patterning the interlayer insulating film and the semiconductor substrate to form a wiring contact; Forming a silicon layer on the wiring contact; Forming a wiring metal layer on the silicon layer; And performing a silicide heat treatment process to metallize the interconnection metal layer and the silicon layer.
이하, 본 발명에 따른 반도체소자의 금속배선 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 및 도 1b은 본 발명의 일실시예에 따른 반도체소자의 콘택배선 형성방법을 설명하기 위한 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to an embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 다른 실시예에 따른 반도체소자의 콘택배선 형성방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming contact wirings in a semiconductor device according to another embodiment of the present invention.
본 발명의 일실시예에 따른 반도체소자의 콘택배선 형성방법은, 도 1a에 도시된 바와같이, 실리콘기판(31)상에 층간절연막(32)를 형성한다.In the method for forming contact wiring of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 1A, an interlayer insulating film 32 is formed on a silicon substrate 31.
그다음, 상기 층간절연막(32)상에 콘택형성용 감광막패턴(미도시)을 형성하고, 이를 마스크로 상기 층간절연막(32)과 반도체기판(31)을 선택적으로 패터닝하여 배선콘택홀(33)을 형성한다. 이때, 상기 반도체기판(31)은 Y1만큼 과도식각된다.Next, a contact forming photoresist pattern (not shown) is formed on the interlayer insulating layer 32, and the wiring contact hole 33 is formed by selectively patterning the interlayer insulating layer 32 and the semiconductor substrate 31 using the mask. Form. At this time, the semiconductor substrate 31 is overetched by Y1.
이어서, 상기 배선콘택홀(33)의 바닥에 실리콘층(34)을 형성한다. 이때, 상기 실리콘층(34)은 에피텍셜성장에 의한 실리콘성장을 통해 형성한다. 또한, 상기 실리콘층(34)은 도프트 또는 언도프트실리콘층을 사용할 수도 있다. 그리고, 상기 실리콘층(34)의 두께는 X1만큼 형성한다.Subsequently, a silicon layer 34 is formed on the bottom of the wiring contact hole 33. In this case, the silicon layer 34 is formed through silicon growth by epitaxial growth. In addition, the silicon layer 34 may use a doped or undoped silicon layer. Then, the thickness of the silicon layer 34 is formed by X1.
그다음, 실리사이드 형성을 위해 상기 실리콘층(34)을 포함한 콘택홀(33) 그리고 층간절연막(32)의 상면에 배선금속층(35)을 증착한다. 이때, 상기 배선금속층(35)은 Ti, Co, Mo, Pt 등의 금속으로 형성한다.Then, the wiring metal layer 35 is deposited on the contact hole 33 including the silicon layer 34 and the upper surface of the interlayer insulating layer 32 to form silicide. At this time, the wiring metal layer 35 is formed of a metal such as Ti, Co, Mo, Pt.
이어서, 실리사이드 열처리공정을 실시한후 상기 콘택홀(33)의 바닥에 있는 실리콘층(34)과 배선금속층(35)부분이 금속실리사이드화(34a)된다.Subsequently, after the silicide heat treatment process, the silicon layer 34 and the wiring metal layer 35 at the bottom of the contact hole 33 are metal silicided 34a.
이때, 원래 증착된 실리콘층(34)의 두께 X1을 조절하여 실리사이드와 실리콘층의 접촉면 깊이가 Y1이상 되지 않게 조절이 가능하다. 오히려, Y1의 깊이를 더 낮출 수 있다.At this time, by adjusting the thickness X1 of the originally deposited silicon layer 34, the contact surface depth of the silicide and the silicon layer can be adjusted not to be more than Y1. Rather, the depth of Y1 can be lowered.
한편, 본 발명의 다른 실시예로서, 도 2a에 도시된 바와같이, 실리콘기판(41)상에 층간절연막(42)를 형성한다.Meanwhile, as another embodiment of the present invention, an interlayer insulating film 42 is formed on the silicon substrate 41 as shown in FIG. 2A.
그다음, 상기 층간절연막(42)상에 콘택형성용 감광막패턴(미도시)을 형성하고, 이를 마스크로 상기 층간절연막(42)과 반도체기판(41)을 선택적으로 패터닝하여 배선콘택홀(43)을 형성한다. 이때, 상기 반도체기판(41)은 Y1만큼 과도식각된다.Next, a contact forming photoresist pattern (not shown) is formed on the interlayer insulating layer 42, and the wiring contact hole 43 is formed by selectively patterning the interlayer insulating layer 42 and the semiconductor substrate 41 using the mask as a mask. Form. At this time, the semiconductor substrate 41 is overetched by Y1.
이어서, 상기 배선콘택홀(43)의 바닥과 측벽 및 층간절연막(42)상에 도프트실리콘층(44)을 형성한다.Subsequently, a doped silicon layer 44 is formed on the bottom and sidewalls of the wiring contact hole 43 and the interlayer insulating film 42.
그다음, 실리사이드 형성을 위해 상기 도프트실리콘층(44)상에배선금속층(45)을 증착한다. 이때, 상기 배선금속층(45)은 Ti, Co, Mo, Pt 등의 금속으로 형성한다. 또한, 상기 배선금속층(45)의 두께는 X1만큼 증착한다.Then, a wiring metal layer 45 is deposited on the doped silicon layer 44 for silicide formation. At this time, the wiring metal layer 45 is formed of a metal such as Ti, Co, Mo, Pt. In addition, the thickness of the wiring metal layer 45 is deposited by X1.
이렇게 배선금속층(45)을 형성한후 확산방지막(미도시)을 증착하고, 실리사이드열처리공정을 행하거나, 실리사이드 열처리후 확산방지막(미도시)을 증착하는 방법을 이용하여 플러그 또는 배선층의 전단계까지 형성한다.After the wiring metal layer 45 is formed, a diffusion barrier layer (not shown) is deposited and a silicide heat treatment process is performed, or after the silicide heat treatment, a diffusion barrier layer (not shown) is deposited to form a plug or a wiring layer up to the previous stage. do.
그다음, 도 2b에 도시된 바와같이, 실리사이드용 열처리공정을 실시하여 상기 도프트실리콘층(44)과 배선금속층(45)을 금속실리사이드화(46)시킨다.Next, as shown in FIG. 2B, a silicide heat treatment process is performed to metallize the doped silicon layer 44 and the wiring metal layer 45.
이어서, 도 2c에 도시된 바와같이, 상기 금속실리사이드(46)을 다마신공정(CMP)후 상기 층간절연막(42)상에 있는 금속실리사이드(46)부분을 패터닝하여 배선(46a)을 형성한다.Subsequently, as shown in FIG. 2C, after the damascene process (CMP), the portion of the metal silicide 46 on the interlayer insulating layer 42 is patterned to form the wiring 46a.
이때, 상기 배선금속(46a)과 실리사이드(46)의 접촉면이 없어짐과 함께 두께 Y1의 증가도 없어 콘택저항이 개선되어진다. 또한, 접합누설전류 특성의 열화가능성이 없어진다.At this time, the contact surface between the wiring metal 46a and the silicide 46 disappears and the thickness Y1 does not increase, thereby improving contact resistance. In addition, the possibility of deterioration of the junction leakage current characteristic is eliminated.
상기 본 발명에 따른 반도체소자의 금속배선 형성방법에 있어서는, 배선금속과 실리사이드의 접촉면이 없어짐과 함께 두께 Y1의 증가도 없어 콘택저항이 개선되어지고, 접합누설전류 특성의 열화가능성이 없어진다.In the method for forming a metal wiring of the semiconductor device according to the present invention, the contact surface between the wiring metal and the silicide is eliminated, the thickness Y1 is not increased, the contact resistance is improved, and the possibility of deterioration of the junction leakage current characteristic is eliminated.
따라서, 본 발명은 콘택저항을 감소시킬 수 있으므로 차세대 반도체소자에서 소자 동작 속도와 같은 문제를 해결 할 수 있어 제품의 질을 향상할 수 있다.Therefore, the present invention can reduce the contact resistance, thereby solving problems such as device operating speed in the next-generation semiconductor device, thereby improving product quality.
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| KR101120181B1 (en) * | 2008-04-21 | 2012-02-27 | 주식회사 하이닉스반도체 | Method for Manufacturing Semiconductor Device |
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