KR20000039892A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000039892A KR20000039892A KR1019980055359A KR19980055359A KR20000039892A KR 20000039892 A KR20000039892 A KR 20000039892A KR 1019980055359 A KR1019980055359 A KR 1019980055359A KR 19980055359 A KR19980055359 A KR 19980055359A KR 20000039892 A KR20000039892 A KR 20000039892A
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 36
- 150000004767 nitrides Chemical class 0.000 claims description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 0.2㎛급 이하의 모스전계효과 트랜지스터(MOSFET)의 제조공정을 단순화함과 아울러 채널길이의 감소에 따른 공정마진을 확보할 수 있도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to simplify a manufacturing process of a MOSFET having a class of 0.2 μm or less and to secure a process margin according to a decrease in channel length. It relates to a manufacturing method.
종래 반도체소자의 제조방법을 도1a 내지 도1j의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1J.
먼저, 도1a에 도시한 바와같이 소자간 분리영역(2)이 형성된 반도체기판(1) 상에 버퍼산화막(3)을 100Å 정도 성장시킨다. 이때, 버퍼산화막(3)은 후속 웰형성 이온주입에 따른 반도체기판(1)의 손상(damage)을 완화하기 위하여 형성한다.First, as shown in FIG. 1A, a buffer oxide film 3 is grown on the semiconductor substrate 1 on which the isolation region 2 between elements is formed. In this case, the buffer oxide film 3 is formed to mitigate damage of the semiconductor substrate 1 due to subsequent well-formed ion implantation.
그리고, 도1b에 도시한 바와같이 상기 버퍼산화막(3)을 통해 피형 불순물이온을 반도체기판(1) 내에 주입하여 피형웰(4)을 형성한다. 이때, 불순물이온은 8.0×1012/cm2의 붕소(B+)를 300KeV의 에너지로 1차 주입하고, 펀치쓰루(punch-through)를 방지하기 위해서 2.0×1012/cm2의 붕소(B+)를 150KeV의 에너지로 2차 주입한 후, 채널의 문턱전압을 조절하기 위해서 2.0×1012/cm2의 붕소(B+)를 20KeV의 에너지로 3차 이온주입하며, 3차까지의 이온주입이 완료되면 어닐링(annealing)을 수행한다.As shown in FIG. 1B, the impurity ions are implanted into the semiconductor substrate 1 through the buffer oxide film 3 to form the wells 4. At this time, impurity ions are first injected with 8.0 × 10 12 / cm 2 of boron (B + ) at 300 KeV energy, and 2.0 × 10 12 / cm 2 of boron (B 2 ) to prevent punch-through. After the secondary injection of + ) with energy of 150 KeV, boron (B + ) of 2.0 × 10 12 / cm 2 is injected into the energy of 20 KeV to adjust the threshold voltage of the channel. When the injection is completed, annealing is performed.
한편, 여기서는 엔모스 트랜지스터를 형성하기 위해서 피형 불순물이온을 주입하여 피형웰(4)을 형성하였으나, 피모스 트랜지스터를 형성하기 위해서 엔형 불순물이온을 주입하여 엔형웰을 형성하여도 무방하다.On the other hand, the implanted well 4 is formed by implanting the impurity ions to form the NMOS transistor. However, the en-well may be formed by implanting the N-type impurity ions to form the PMOS transistor.
그리고, 도1c에 도시한 바와같이 상기 피형웰(4)의 상부에 산화공정을 수행하여 게이트산화막(5)을 70Å 정도 성장시킨 후, 그 게이트산화막(5)의 상부에 도핑된 폴리실리콘(6), WSix막(7), 산화막(8) 및 질화막(9)을 순차적으로 형성한다. 이때, 폴리실리콘(6)은 500Å 정도의 두께로 형성하고, WSix막(7)은 1000Å 정도의 두께로 형성하며, 산화막(8)은 고온저압(HLD)으로 100Å 정도의 두께로 형성하고, 질화막(9)은 1500Å 정도의 두께로 형성하는 것이 바람직하다.As shown in FIG. 1C, the gate oxide film 5 is grown by about 70 kV by performing an oxidation process on the top of the well 4, and then doped with polysilicon 6 doped on the gate oxide film 5. ), The WSix film 7, the oxide film 8 and the nitride film 9 are sequentially formed. At this time, the polysilicon 6 is formed to a thickness of about 500 kPa, the WSix film 7 is formed to a thickness of about 1000 kPa, the oxide film 8 is formed to a thickness of about 100 kPa by high temperature low pressure (HLD), and the nitride film It is preferable to form (9) in the thickness of about 1500 kPa.
그리고, 도1d에 도시한 바와같이 상기 질화막(9)의 상부에 사진식각공정을 통해 감광막(미도시) 패턴을 형성하고, 이를 적용하여 질화막(9), 산화막(8), WSix막(7) 및 폴리실리콘(6)을 순차적으로 식각하여 상기 피형웰(4)의 상부에 소자간 분리영역과 일정한 거리가 이격되는 적층구조의 제1 게이트(first gate)를 형성한다.As shown in FIG. 1D, a photosensitive film (not shown) pattern is formed on the nitride film 9 through a photolithography process, and the nitride film 9, the oxide film 8, and the WSix film 7 are applied to the nitride film 9. And sequentially etching the polysilicon 6 to form a first gate of a stacked structure in which a predetermined distance is spaced apart from an isolation region between devices on the top of the well.
그리고, 도1e에 도시한 바와같이 상기 적층구조의 제1 게이트를 마스크로 하여 피형웰(4) 내에 저농도의 엔형 불순물이온을 주입한다. 이때, 불순물이온은 5.0×1013/cm2의 인(P+)을 20KeV의 에너지로 주입한다.As shown in Fig. 1E, a low concentration of N-type impurity ions is implanted into the wells 4 using the first gate of the stacked structure as a mask. At this time, the impurity ion is injected with phosphorus (P + ) of 5.0 × 10 13 / cm 2 with an energy of 20 KeV.
그리고, 도1f에 도시한 바와같이 상기 저농도의 엔형 불순물이온이 주입된 구조물의 상부에 질화막을 700Å 정도의 두께로 형성한 후, 에치-백(etch-back)하여 상기 적층구조의 제1 게이트 측면에 질화막측벽(10)을 형성한다.In addition, as shown in FIG. 1F, a nitride film is formed on the upper portion of the structure in which the low concentration of the N-type impurity ion is implanted to a thickness of about 700 μs, and then etched back to form a first gate side surface of the stacked structure. The nitride film side wall 10 is formed.
그리고, 도1g에 도시한 바와같이 상기 적층구조의 제1 게이트 및 질화막측벽(10)을 마스크로 하여 피형웰(4) 내에 고농도의 엔형 불순물이온을 주입한 후, 어닐링을 수행하여 엘디디(lightly doped drain : LDD)의 소스/드레인(11)을 형성한다. 이때, 불순물이온은 2.0×1015/cm2의 비소(As+)를 50KeV의 에너지로 주입한다.As shown in FIG. 1G, a high concentration of en-type impurity ions is implanted into the wells 4 using the first gate and the nitride film side walls 10 of the stacked structure as masks, and then annealing is performed to lightly The source / drain 11 of the doped drain (LDD) is formed. At this time, the impurity ion is implanted with arsenic (As + ) of 2.0 × 10 15 / cm 2 with an energy of 50 KeV.
그리고, 도1h에 도시한 바와같이 상기 소스/드레인(11)이 형성된 구조물의 상부에 고온저압산화막(12)을 2000Å HSG막(13)을 5000Å 정도의 두께로 증착한 후, 화학기계적 연마(chemical mechanical polishing : CMP)를 통해 평탄화 한다.Then, as shown in FIG. 1H, a high temperature low pressure oxide film 12 is deposited on the top of the structure on which the source / drain 11 is formed, and the 2000 HSG film 13 is deposited to a thickness of about 5000 kPa, followed by chemical mechanical polishing (chemical mechanical polishing (CMP).
그리고, 도1i에 도시한 바와같이 사진식각공정을 통해 상기 HSG막(13) 및 고온저압산화막(12)의 일부를 식각하여 상기 소스/드레인(11)이 노출되는 콘택홀(14,15)을 형성한다.In addition, as shown in FIG. 1I, a portion of the HSG film 13 and the high temperature low pressure oxide film 12 is etched through a photolithography process to contact the contact holes 14 and 15 to which the source / drain 11 is exposed. Form.
그리고, 도1j에 도시한 바와같이 상기 콘택홀(14,15)이 형성된 구조물의 상부에 콘택홀(14,15)이 완전히 매립되도록 금속층을 형성한 후, 패터닝하여 플러그(16,17)를 형성한다.As shown in FIG. 1J, a metal layer is formed to completely fill the contact holes 14 and 15 on the structure where the contact holes 14 and 15 are formed, and then patterned to form plugs 16 and 17. do.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 펀치쓰루 방지 이온주입을 적용하고, 사용 가능한 최저수준의 에너지로 엘디디의 할로(halo) 이온주입을 적용하더라도, 엘디디영역의 확산에 따른 한계로 인해 0.3㎛급 이하 모스 전계효과 트랜지스터의 채널길이 감소에 따른 공정 마진을 확보할 수 없으며, 또한 게이트의 형성을 위한 사진식각공정에서 KrF 노광을 사용하더라도, 0.25㎛ 이하의 게이트 패턴을 형성하기 어려운 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above is limited by the diffusion of the LED region, even if the punch-through prevention ion implantation is applied and the LED of halo ion implantation is applied with the lowest energy available. As a result, process margins cannot be secured due to the decrease in channel length of the MOS field effect transistors of 0.3 µm or less, and it is difficult to form gate patterns of 0.25 µm or less even when KrF exposure is used in the photolithography process for forming gates. There was a problem.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 0.2㎛급 이하의 모스전계효과 트랜지스터의 제조공정을 단순화함과 아울러 채널길이의 감소에 따른 공정마진을 확보할 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to simplify the manufacturing process of the Mohs field effect transistor of 0.2 ㎛ or less and to secure the process margin according to the reduction of the channel length The present invention provides a method for manufacturing a semiconductor device.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:반도체기판 22:분리영역21: semiconductor substrate 22: separation area
23:버퍼산화막 24:피형웰23: buffer oxide film 24: corrugated well
25:저농도영역 26,32:고온저압산화막25: low concentration region 26, 32: high temperature low pressure oxide film
27,33,34:콘택홀 28:질화막측벽27, 33, 34: contact hole 28: nitride film side wall
29:게이트산화막 30:폴리실리콘29: gate oxide film 30: polysilicon
31:WSix막 35:소스/드레인31: WSix Film 35: Source / Drain
36,37:플러그36,37: Plug
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 소자간 분리영역이 형성된 반도체기판 내에 제1도전형 불순물이온을 주입하여 웰을 형성하는 공정과; 상기 웰 내에 저농도의 제2도전형 불순물이온을 주입하여 저농도영역을 형성하는 공정과; 상기 저농도영역이 형성된 구조물의 상부에 제1절연막을 형성한 후, 사진식각공정을 통해 식각하여 게이트가 형성될 영역에 제1콘택홀을 형성하는 공정과; 상기 제1콘택홀이 형성된 구조물의 상부에 제2절연막을 증착한 후, 에치-백하여 제1콘택홀의 측면에 절연막측벽을 형성하는 공정과; 상기 제1콘택홀 하부 웰 내의 저농도 영역을 식각한 후, 그 식각된 영역에 채널의 문턱전압 조절을 위한 제1도전형 불순물이온을 주입하는 공정과; 상기 제1도전형 불순물이온이 주입된 웰의 상부에 게이트산화막을 형성하는 공정과; 상기 게이트산화막이 형성된 구조물의 상부에 게이트전극 물질을 증착하여 제1콘택홀을 매립한 후, 평탄화하여 게이트를 형성하는 공정과; 상기 게이트가 형성된 구조물의 상부에 제3절연막을 형성한 후, 사진식각공정을 통해 제3절연막 및 제1절연막의 일부를 식각하여 상기 웰 내에 형성된 저농도영역의 일부가 노출되도록 제2,제3콘택홀을 형성하는 공정과; 상기 제2,제3콘택홀을 통해 고농도의 제2도전형 불순물이온을 주입하여 소스/드레인을 형성하는 공정과; 상기 소스/드레인이 형성된 구조물의 상부에 도전성 물질을 증착하여 제2,제3콘택홀을 매립한 후, 패터닝하여 제1,제2플러그를 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.One preferred embodiment of the semiconductor device manufacturing method for achieving the object of the present invention as described above is a step of forming a well by injecting a first conductive type impurity ions into a semiconductor substrate formed with an isolation region between devices; Forming a low concentration region by injecting a low concentration of a second conductivity type impurity ion into the well; Forming a first contact hole in the region where the gate is to be formed by etching through a photolithography process after forming a first insulating layer on the structure where the low concentration region is formed; Depositing a second insulating film on the structure where the first contact hole is formed, and then etching back to form an insulating film side wall at a side of the first contact hole; Etching a low concentration region in the lower well of the first contact hole, and implanting first conductive impurity ions for adjusting a threshold voltage of the channel into the etched region; Forming a gate oxide layer on the well into which the first conductive impurity ion is implanted; Depositing a gate electrode material on the structure where the gate oxide film is formed to fill the first contact hole, and then planarize to form a gate; After the third insulating layer is formed on the structure where the gate is formed, the second and third contacts are exposed by etching a portion of the third insulating layer and the first insulating layer through a photolithography process to expose a portion of the low concentration region formed in the well. Forming a hole; Implanting a high concentration of second conductive impurity ions through the second and third contact holes to form a source / drain; And filling the second and third contact holes by depositing a conductive material on the structure on which the source / drain is formed, and then patterning the first and second plugs.
상기한 바와같은 본 발명에 의한 반도체소자 제조방법의 바람직한 일 실시예를 도2a 내지 도2k에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to the cross-sectional view shown in FIGS. 2A to 2K.
먼저, 도2a에 도시한 바와같이 소자간 분리영역(22)이 형성된 반도체기판(21) 상에 버퍼산화막(23)을 100Å 정도 성장시킨다. 이때, 버퍼산화막(23)은 종래와 동일하게 후속 웰형성 이온주입에 따른 반도체기판(21)의 손상을 완화한다.First, as shown in FIG. 2A, the buffer oxide film 23 is grown on the semiconductor substrate 21 on which the isolation region 22 between elements is formed. At this time, the buffer oxide film 23 mitigates the damage of the semiconductor substrate 21 due to subsequent well-formed ion implantation as in the prior art.
그리고, 도2b에 도시한 바와같이 상기 버퍼산화막(23)을 통해 제1도전형으로 예를 들어 피형 불순물이온을 반도체기판(21) 내에 주입하여 피형웰(24)을 형성한다. 이때, 불순물이온은 8.0×1012/cm2의 붕소(B+)를 450KeV의 에너지로 1차 주입하고, 펀치쓰루를 방지하기 위해서 2.0×1012/cm2의 붕소(B+)를 200KeV의 에너지로 2차 주입하며, 이와같은 이온주입이 완료되면 어닐링을 수행한다.As shown in FIG. 2B, the impurity ions, for example, implanted impurity ions are implanted into the semiconductor substrate 21 through the buffer oxide film 23 to form the wells 24. At this time, impurity ions are first injected with 8.0 × 10 12 / cm 2 of boron (B + ) with 450 KeV of energy, and to prevent punch-through, 2.0 × 10 12 / cm 2 of boron (B + ) of 200 KeV of Second injection with energy, annealing is performed when such ion implantation is complete.
그리고, 도2c에 도시한 바와같이 제2도전형으로 예를 들어 엔형 불순물이온을 상기 피형웰(24) 내에 저농도로 주입하여 저농도영역(25)을 형성한다. 이때, 불순물이온은 마스크를 사용하지 않고, 블랭킷(blanket)으로 3.0×1014/cm2의 인(P+)을 20KeV의 에너지로 주입하며, 피모스 트랜지스터가 형성되는 영역(미도시)은 카운터 도핑(counter doping)을 통해 공정을 단순화할 수 있다.As shown in FIG. 2C, for example, N-type impurity ions are injected into the wells 24 at low concentrations to form the low concentration regions 25 as the second conductivity type. In this case, impurity ions are implanted with a blanket (P + ) of 3.0 × 10 14 / cm 2 with energy of 20 KeV without using a mask, and the region (not shown) where the PMOS transistor is formed Counter doping can simplify the process.
그리고, 도2d에 도시한 바와같이 상기 저농도영역(25)이 형성된 구조물의 상부에 제1절연막으로 예를 들어 고온저압산화막(26)을 5000Å 정도의 두께로 형성한 후, I-라인 스테퍼(stepper)장비를 이용한 사진식각공정을 통해 식각하여 게이트가 형성될 영역에 콘택홀(27)을 형성한다.As shown in FIG. 2D, a high temperature low pressure oxide film 26 is formed on the upper portion of the structure in which the low concentration region 25 is formed to have a thickness of, for example, about 5000 kV, as a first insulating film, and then an I-line stepper is formed. The contact hole 27 is formed in the region where the gate is to be formed by etching through a photolithography process using the equipment.
그리고, 도2e에 도시한 바와같이 상기 콘택홀(27)이 형성된 구조물의 상부에 제2절연막으로 예를 들어 질화막을 1000Å 정도의 두께로 형성한 후, 에치-백하여 상기 콘택홀(27)의 측면에 질화막측벽(28)을 형성한다. 이때, 질화막측벽(28)이 게이트가 형성될 영역의 콘택홀(27) 내벽에 형성됨에 따라 후속공정에서 콘택홀(27) 내에 형성되는 게이트를 I-라인 스테퍼장비의 한계 해상력보다 작게 할 수 있다.As shown in FIG. 2E, for example, a nitride film is formed on the upper portion of the structure where the contact hole 27 is formed as a second insulating layer, for example, about 1000 GPa thick, and then etched back to form a contact hole 27. The nitride film side wall 28 is formed in the side surface. At this time, since the nitride film side wall 28 is formed in the inner wall of the contact hole 27 in the region where the gate is to be formed, the gate formed in the contact hole 27 in the subsequent process may be smaller than the limit resolution of the I-line stepper equipment. .
그리고, 도2f에 도시한 바와같이 상기 콘택홀(27) 하부 피형웰(24) 내의 저농도영역(25)을 700Å 정도 습식식각한 후, 그 식각된 영역에 채널의 문턱전압 조절을 위한 피형 불순물이온으로 2.0×1012/cm2의 붕소(B+)를 20KeV의 에너지로 주입한다.Then, as shown in FIG. 2F, after wet etching the low concentration region 25 in the contact hole 27 lower surface well 24 for about 700 Å, the implanted impurity ions for adjusting the threshold voltage of the channel in the etched region. Then, 2.0 × 10 12 / cm 2 of boron (B + ) is injected at an energy of 20 KeV.
이때, 상기 채널의 문턱전압 조절을 위한 불순물이온의 주입은 상기 콘택홀(27) 하부 피형웰(24) 내의 저농도영역(25)이 식각된 영역에 희생산화막(미도시)을 500Å 정도의 두께로 형성하는 단계와; 상기 희생산화막을 습식식각하는 단계와; 제1버퍼산화막(미도시)을 100Å 정도의 두께로 형성하는 단계와; 채널의 문턱전압 조절을 위한 피형 불순물이온을 주입하는 단계와; 상기 제1버퍼산화막을 습식식각하는 단계로 이루어지는 것이 바람직하며, 이와같이 피형웰(24)을 식각하여 채널의 문턱전압 조절을 위한 피형 불순물이온을 주입함에 따라 0.2㎛급 이하 모스 전계효과 트랜지스터의 채널길이 감소에 따른 공정 마진을 확보할 수 있게 된다.In this case, the implantation of impurity ions for controlling the threshold voltage of the channel may be performed to form a sacrificial oxide film (not shown) in the region where the low concentration region 25 is etched in the contact hole 27 lowered well 24. Forming; Wet etching the sacrificial oxide film; Forming a first buffer oxide film (not shown) to a thickness of about 100 GPa; Implanting the dopant ions for controlling the threshold voltage of the channel; Preferably, the first buffer oxide layer is wet-etched. The channel length of the MOS field effect transistor is 0.2 μm or less as the implanted impurity ions are implanted to etch the wells 24 to control the threshold voltage of the channel. It is possible to secure process margins due to the reduction.
그리고, 도2g에 도시한 바와같이 상기 문턱전압 조절을 위한 불순물이온이 주입된 피형웰(24)의 상부에 게이트산화막(29)을 70Å 정도의 두께로 성장시킨다.As shown in FIG. 2G, the gate oxide film 29 is grown to a thickness of about 70 kHz on the implanted well 24 into which the impurity ions are injected to adjust the threshold voltage.
그리고, 도2h에 도시한 바와같이 상기 게이트산화막(29)이 형성된 구조물의 상부에 게이트전극 물질로 예를 들어 도핑된 폴리실리콘(30)과 WSix막(31)을 순차적으로 증착하여 콘택홀(27)을 매립한 후, 화학기계적 연마를 통해 평탄화하여 게이트를 형성한다. 이때, 폴리실리콘(30)은 500Å 정도의 두께로 증착하고, WSix막(31)은 1000Å 정도의 두께로 증착하는 것이 바람직하다.As shown in FIG. 2H, the polysilicon 30 doped with the gate electrode material and the WSix layer 31 are sequentially deposited on the structure on which the gate oxide layer 29 is formed. ), And then planarized by chemical mechanical polishing to form a gate. At this time, the polysilicon 30 is deposited to a thickness of about 500 kPa, and the WSix film 31 is preferably deposited to a thickness of about 1000 kPa.
그리고, 도2i에 도시한 바와같이 상기 게이트가 형성된 구조물의 상부에 제3절연막으로 예를 들어 고온저압산화막(32)을 2000Å 정도의 두께로 증착한 후, 사진식각공정을 통해 고온저압산화막(32,26)의 일부를 식각하여 상기 피형웰(24) 내에 형성된 저농도영역(25)의 일부가 노출되도록 콘택홀(33,34)을 형성한다.As shown in FIG. 2I, a high temperature low pressure oxide film 32 is deposited on the structure of the gate on which the high temperature low pressure oxide film 32 is formed to a thickness of about 2000 microseconds, and the high temperature low pressure oxide film 32 is formed through a photolithography process. A portion of, 26 is etched to form contact holes 33 and 34 to expose a portion of the low concentration region 25 formed in the well.
그리고, 도2j에 도시한 바와같이 상기 콘택홀(33,34)을 통해 고농도의 엔형 불순물이온을 주입하여 소스/드레인(35)을 형성한다. 이때, 불순물이온은 2.0×1015/cm2의 비소(As+)를 30KeV의 에너지로 주입하는 것이 바람직하다.As shown in FIG. 2J, a high concentration of N-type impurity ions is implanted through the contact holes 33 and 34 to form a source / drain 35. At this time, it is preferable that the impurity ion is implanted with 2.0 × 10 15 / cm 2 of arsenic (As + ) at an energy of 30 KeV.
그리고, 도2k에 도시한 바와같이 상기 소스/드레인(35)이 형성된 구조물의 상부에 도전성 물질을 증착하여 상기 콘택홀(33,34)을 매립한 후, 패터닝하여 플러그(36,37)를 형성한다.2K, a conductive material is deposited on the structure on which the source / drain 35 is formed to fill the contact holes 33 and 34, and then patterned to form plugs 36 and 37. do.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 I-라인 스테퍼장비를 이용한 사진식각공정을 통해 제1절연막을 식각하여 게이트가 형성될 영역에 제1콘택홀을 형성하고, 그 제1콘택홀의 내벽에 절연막측벽을 형성함에 따라 게이트를 I-라인 스테퍼장비의 한계 해상력보다 작게 형성할 수 있으며, 또한 제1콘택홀의 하부 웰을 습식식각하여 채널을 형성함에 따라 채널이 게이트의 하면뿐만 아니라 측면에까지 형성되므로, 채널길이 감소에 따른 공정 마진을 확보할 수 있게 되어 0.2㎛급 이하 모스 전계효과 트랜지스터의 집적도를 향상시킬 수 있는 효과와 아울러 게이트가 형성된 후의 구조물이 평탄화되므로, 후속 공정의 적용이 용이한 효과가 있으며, 저농도 엔형 불순물이온을 블랭킷으로 주입하고, 피모스 트랜지스터가 형성되는 영역을 카운터 도핑하여 공정을 단순화할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, the first insulating layer is etched through a photolithography process using an I-line stepper device to form a first contact hole in a region where a gate is to be formed, and the first contact thereof. By forming the insulation side wall on the inner wall of the hole, the gate can be formed smaller than the limit resolution of the I-line stepper equipment, and the channel is formed by wet etching the lower well of the first contact hole to form the channel as well as the lower surface of the gate. Since the process margin can be secured by reducing the channel length, the degree of integration of the MOS field effect transistor of 0.2 μm or less can be improved, and the structure after the gate is flattened, so that subsequent processes can be easily applied. It has an effect, and a low concentration of en-type impurity ions are implanted into the blanket, and the region where the PMOS transistor is formed The counter has an effect that can be doped to simplify the process.
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